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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 44 ++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b42e5848cc..cd86597172 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2514,11 +2514,16 @@ static void disas_b_exc_sys(DisasContext *s, uint32= _t insn) * races in multi-threaded linux-user and when MTTCG softmmu is * enabled. */ -static void gen_load_exclusive(DisasContext *s, int rt, int rt2, - TCGv_i64 addr, int size, bool is_pair) +static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn, + int size, bool is_pair) { int idx =3D get_mem_index(s); MemOp memop =3D s->be_data; + TCGv_i64 dirty_addr, clean_addr; + + s->is_ldex =3D true; + dirty_addr =3D cpu_reg_sp(s, rn); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, size); =20 g_assert(size <=3D 3); if (is_pair) { @@ -2526,7 +2531,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ memop |=3D MO_64 | MO_ALIGN; - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32= , 32); @@ -2544,7 +2549,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 memop |=3D MO_128 | MO_ALIGN_16 | MO_ATMAX_8; - tcg_gen_qemu_ld_i128(t16, addr, idx, memop); + tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop); =20 tcg_gen_extr_i128_i64(cpu_exclusive_val, cpu_exclusive_high, t= 16); tcg_temp_free_i128(t16); @@ -2559,14 +2564,14 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, } } else { memop |=3D size | MO_ALIGN; - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } - tcg_gen_mov_i64(cpu_exclusive_addr, addr); + tcg_gen_mov_i64(cpu_exclusive_addr, clean_addr); } =20 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, - TCGv_i64 addr, int size, int is_pair) + int rn, int size, int is_pair) { /* if (env->exclusive_addr =3D=3D addr && env->exclusive_val =3D=3D [a= ddr] * && (!is_pair || env->exclusive_high =3D=3D [addr + datasize])) { @@ -2582,9 +2587,12 @@ static void gen_store_exclusive(DisasContext *s, int= rd, int rt, int rt2, */ TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); - TCGv_i64 tmp; + TCGv_i64 tmp, dirty_addr, clean_addr; =20 - tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); + dirty_addr =3D cpu_reg_sp(s, rn); + clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, size); + + tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 tmp =3D tcg_temp_new_i64(); if (is_pair) { @@ -2774,9 +2782,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); + gen_store_exclusive(s, rs, rt, rt2, rn, size, false); return; =20 case 0x4: /* LDXR */ @@ -2784,10 +2790,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, false); + gen_load_exclusive(s, rt, rt2, rn, size, false); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2839,9 +2842,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); + gen_store_exclusive(s, rs, rt, rt2, rn, size, true); return; } if (rt2 =3D=3D 31 @@ -2858,10 +2859,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, true); + gen_load_exclusive(s, rt, rt2, rn, size, true); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } --=20 2.34.1