From nobody Wed Feb 11 05:47:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676516497; cv=none; d=zohomail.com; s=zohoarc; b=X4OGu6DF8KJoq8nomablV31d7HWSaInKsIN2aZOlTQmWy1LdIvHtFeWFb2HwcKtIeT8N+nwp+44Mrgo37nb2u9ciGwzDjIJdope0yCei6I/ihrx2FqFnkUenpUcq3bB1f16Fc03gpLtN0wgbs45A2tR8AR6JHppSWDjAx9l9Mb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676516497; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=c3rh4A690IymlOf10Atd7nhBNH65J0XD/I+q4xGnotk=; b=UQVBbzOPAuwoUyLCgV+GdE1w8BNhDOcQT1q2FjhH4p9Sfz6Qq3gBkm2dreinQsSQR0CCAq96hkRjTWBzrfbbarr7YnZ7lLQ0Lf0e1KBD1y8I4o/LDx++2o3bL6K0qc58aXhq8OWxFwX8bTtHvwdiLJDdTAA2hz0g8LvnY/SIMEQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676516497802400.48267923412743; Wed, 15 Feb 2023 19:01:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pSUTI-0003VJ-FW; Wed, 15 Feb 2023 21:58:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pSUTG-0003Ts-45 for qemu-devel@nongnu.org; Wed, 15 Feb 2023 21:58:06 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pSUTE-0005kp-6n for qemu-devel@nongnu.org; Wed, 15 Feb 2023 21:58:05 -0500 Received: by mail-pf1-x429.google.com with SMTP id r17so574427pff.9 for ; Wed, 15 Feb 2023 18:58:03 -0800 (PST) Received: from stoup.. (rrcs-74-87-59-234.west.biz.rr.com. [74.87.59.234]) by smtp.gmail.com with ESMTPSA id e14-20020a62aa0e000000b005a816b7c3e8sm89655pff.24.2023.02.15.18.58.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 18:58:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=c3rh4A690IymlOf10Atd7nhBNH65J0XD/I+q4xGnotk=; b=zC0NiHMscGMuivRf6wqzv3Ts33GYnj5IVrnKJWRRTFdRXAQT/VGrkUJkeDl2qH5MjL LFuuWPHgTGCjqu6NNnImppH+WIi0yCMRvTZGQCyZ0ac2+DoSZpy7wUco6tXwCMErUo2v s2D36Re+AmVQy0Y+DBaIYRenMxX9OOs9pJX/TB4jWQpVGsLIYNA9lWHnoPjEp78B3odu K0PyTibrQVXUuLakSw4VZT6D0XEAjB3gl0hTwof0kvtbxcwps6MMOzoG72NAtx/146Uc q08pdpaH7JeU9vcQygE8ewyUwAn0yy1D0Z8h63HiHN0tsZssZwF9VLwxNZHuAff2qds/ Xeqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c3rh4A690IymlOf10Atd7nhBNH65J0XD/I+q4xGnotk=; b=Km3ko4WzOD6craiUKXAmkumDT9CDB4D0fN6XjGNb6Ex0NyNymg+0nCiZ9WS/szG6q5 0Lb5kORvdm8YOinJLvI4k8pa4fF4wgHjQpEGxfkwdY/DL5EFPOxRlRpGMQ39xLJ2cFo9 B9maKULiNnjZMCz0Rrn4N+SV9wL0pZxFI9gowtwTV0fUMyefE9P0XQEP1ytrWhcoabzX T7gjwkGqlcL0NclHpiEwdLm1Rhxn7ttzHCA4Ptwg1rGofnyukklZS9qG9a7Dhko5GSSB YUPOAu3OZKMVTqCL3bgYSFBCnq1R8lutrqeLeojnFMNH8abnwh2rwMGrjNz6ESin1iBc RTEA== X-Gm-Message-State: AO0yUKXsLGbnxiNXUSpLs5iExFhCuPfiLk04LrMMD+9IUqV7SF0k0/Sh n4HistMOiaZZ4IrG/vwFPgZbXOsjlfEoz7KeaCo= X-Google-Smtp-Source: AK7set+2qvCPMhRsjlQZv5NCyZ/WP6YgjVU3SYsVf0Ps3JPD5/cn2y3yuMeJlSVn9XBpB+56EjXKTw== X-Received: by 2002:aa7:9d01:0:b0:5a8:cb5f:94d4 with SMTP id k1-20020aa79d01000000b005a8cb5f94d4mr4092598pfp.32.1676516282619; Wed, 15 Feb 2023 18:58:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/30] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc Date: Wed, 15 Feb 2023 16:57:24 -1000 Message-Id: <20230216025739.1211680-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216025739.1211680-1-richard.henderson@linaro.org> References: <20230216025739.1211680-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676516499881100003 Content-Type: text/plain; charset="utf-8" Hosts using Intel and AMD AVX cpus are quite common. Add fast paths through ldst_atomicity using this. Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 76 +++++++++++++++++++++++++++------- 1 file changed, 60 insertions(+), 16 deletions(-) diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index c7999e0ef1..07982e021d 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -35,6 +35,14 @@ =20 #if defined(CONFIG_ATOMIC128) # define HAVE_al16_fast true +#elif defined(CONFIG_TCG_INTERPRETER) +/* + * FIXME: host specific detection this is in tcg/$host/, + * but we're using tcg/tci/ instead. + */ +# define HAVE_al16_fast false +#elif defined(__x86_64__) +# define HAVE_al16_fast likely(have_atomic16) #else # define HAVE_al16_fast false #endif @@ -162,6 +170,12 @@ load_atomic16(void *pv) =20 r.u =3D qatomic_read__nocheck(p); return r.s; +#elif defined(__x86_64__) + Int128Alias r; + + /* Via HAVE_al16_fast, have_atomic16 is true. */ + asm("vmovdqa %1, %0" : "=3Dx" (r.u) : "m" (*(Int128 *)pv)); + return r.s; #else qemu_build_not_reached(); #endif @@ -380,6 +394,24 @@ load_atom_extract_al16_or_al8(void *pv, int s) r =3D qatomic_read__nocheck(p16); } return r >> shr; +#elif defined(__x86_64__) + uintptr_t pi =3D (uintptr_t)pv; + int shr =3D (pi & 7) * 8; + uint64_t a, b; + + /* Via HAVE_al16_fast, have_atomic16 is true. */ + pv =3D (void *)(pi & ~7); + if (pi & 8) { + uint64_t *p8 =3D __builtin_assume_aligned(pv, 16, 8); + a =3D qatomic_read__nocheck(p8); + b =3D qatomic_read__nocheck(p8 + 1); + } else { + asm("vmovdqa %2, %0\n\tvpextrq $1, %0, %1" + : "=3Dx"(a), "=3Dr"(b) : "m" (*(__uint128_t *)pv)); + } + asm("shrd %b2, %1, %0" : "+r"(a) : "r"(b), "c"(shr)); + + return a; #else qemu_build_not_reached(); #endif @@ -696,23 +728,35 @@ static inline void ATTRIBUTE_ATOMIC128_OPT store_atomic16(void *pv, Int128Alias val) { #if defined(CONFIG_ATOMIC128) - __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); - qatomic_set__nocheck(pu, val.u); -#elif defined(CONFIG_CMPXCHG128) - __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); - __uint128_t o; - - /* - * Without CONFIG_ATOMIC128, __atomic_compare_exchange_n will always - * defer to libatomic, so we must use __sync_val_compare_and_swap_16 - * and accept the sequential consistency that comes with it. - */ - do { - o =3D *pu; - } while (!__sync_bool_compare_and_swap_16(pu, o, val.u)); -#else - qemu_build_not_reached(); + { + __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); + qatomic_set__nocheck(pu, val.u); + return; + } #endif +#if defined(__x86_64__) + if (HAVE_al16_fast) { + asm("vmovdqa %1, %0" : "=3Dm"(*(__uint128_t *)pv) : "x" (val.u)); + return; + } +#endif +#if defined(CONFIG_CMPXCHG128) + { + __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); + __uint128_t o; + + /* + * Without CONFIG_ATOMIC128, __atomic_compare_exchange_n will alwa= ys + * defer to libatomic, so we must use __sync_val_compare_and_swap_= 16 + * and accept the sequential consistency that comes with it. + */ + do { + o =3D *pu; + } while (!__sync_bool_compare_and_swap_16(pu, o, val.u)); + return; + } +#endif + qemu_build_not_reached(); } =20 /** --=20 2.34.1