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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GY8+XZXt1WwhGHNe4w41pwNJufQrqsV0Unpbj9QQTJg=; b=AAXYLp84X55v1PCIKEBERUmfIlyxGUSALhz8UOrF/T8CniZEX1VHLyQAwuAkueLI6c QfnsN2Br7mQxaRXboBU2iSAUBz2ogo/loYjjVx05p6clJNlSiglTvpTjdQ/bhaH8J9K/ YwTokqCjq4EleEzelBi/ee8L9tf44hFcuVGw6DWzMNpfOuT+53W/p0R5+HLdvi54CE07 V9eA7UKsvTJL/bOtC2K8BtARV0Ap8ZZ2aoNkAvUPHEevULO4iTwvtqWywb5XWeiZCv8m zUCoUSfnArlMGhzATOZYYiIaO0jOBFSdBRBjaHU9rZcuWppuoAG3Gfz8aT3wkPJF5gCD eH9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GY8+XZXt1WwhGHNe4w41pwNJufQrqsV0Unpbj9QQTJg=; b=YyCJNvCBqEaei5C69Bitnpo3wZa8Q3favSGwR5x9ep3AlkpjPZVyDBGJYqghye0pBd VnJwrkovvGc4zg55qgykuXx0/Bk/cj4VHxJVjDWRqlKKtxIHIUPlCIAwEknbs5yNPtse BhDoK/N0AzB2+UfFwunuLXTVkhEtkSYpImyJTAw1dvlZ2qqBKpbPJjhjIP3JWssDtQ5k 3esfmW2zN1bFx31FCn08VL6itJbDyATsp60+rs61U7qmi//LveIb+lCqFWaX3/M8wKoI rpUGamkoAQepmmUmaOWICEWx2PxMuf77E8M+nT5AN0Kk0UJd8z/uJEgVJEa9BHpfj6TZ MxMA== X-Gm-Message-State: AO0yUKVJsTu0BhoX8kPjtNLTukS+FWWvJdDc32h4qxjaj9WyVqNdn/S5 xOHMeWRCgBAYSszVuSi8bMAy1TUXKGywXft4/hM= X-Google-Smtp-Source: AK7set8y75kEdclW3cPAcGPsPOHoy/WGKQcjmVfp2xaBXCcd5yqfbwJ6z0/1gkpamUdNTYedFUjD8w== X-Received: by 2002:a62:848e:0:b0:5a8:4de2:e94e with SMTP id k136-20020a62848e000000b005a84de2e94emr2560366pfd.33.1676392273135; Tue, 14 Feb 2023 08:31:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH 14/14] target/arm: Support reading m-profile system registers from gdb Date: Tue, 14 Feb 2023 06:30:48 -1000 Message-Id: <20230214163048.903964-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676392303560100001 Content-Type: text/plain; charset="utf-8" From: David Reiss Follows a fairly similar pattern to the existing special register debug support. Only reading is implemented, but it should be possible to implement writes. Signed-off-by: David Reiss [rth: Split out from two other patches; Use an enumeration to locally number the registers. Use a structure to list and control runtime visibility. Handle security extension with the same code.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/gdbstub.c | 169 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 170 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c9f768f945..536e60d48c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -867,6 +867,7 @@ struct ArchCPU { =20 DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_m_systemreg_xml; =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 062c8d447a..a8848c7fee 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,6 +322,167 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, i= nt base_reg) return cpu->dyn_sysreg_xml.num; } =20 +enum { + M_SYSREG_MSP =3D 0, + M_SYSREG_PSP =3D 1, + M_SYSREG_PRIMASK =3D 2, + M_SYSREG_CONTROL =3D 3, + M_SYSREG_BASEPRI =3D 4, + M_SYSREG_FAULTMASK =3D 5, + M_SYSREG_MSPLIM =3D 6, + M_SYSREG_PSPLIM =3D 7, + M_SYSREG_REG_MASK =3D 7, + + /* + * NOTE: MSP, PSP, MSPLIM, PSPLIM technically don't exist if the + * secure extension is present (replaced by MSP_S, MSP_NS, et al). + * However, the MRS instruction is still allowed to read from MSP and = PSP, + * and will return the value associated with the current security stat= e. + * We replicate this behavior for the convenience of users, who will s= ee + * GDB behave similarly to their assembly code, even if they are obliv= ious + * to the security extension. + */ + M_SYSREG_CURRENT =3D 0 << 3, + M_SYSREG_NONSECURE =3D 1 << 3, + M_SYSREG_SECURE =3D 2 << 3, + M_SYSREG_MODE_MASK =3D 3 << 3, +}; + +static const struct { + const char *name; + int feature; +} m_systemreg_def[] =3D { + [M_SYSREG_MSP] =3D { "msp", ARM_FEATURE_M }, + [M_SYSREG_PSP] =3D { "psp", ARM_FEATURE_M }, + [M_SYSREG_PRIMASK] =3D { "primask", ARM_FEATURE_M }, + [M_SYSREG_CONTROL] =3D { "control", ARM_FEATURE_M }, + [M_SYSREG_BASEPRI] =3D { "basepri", ARM_FEATURE_M_MAIN }, + [M_SYSREG_FAULTMASK] =3D { "faultmask", ARM_FEATURE_M_MAIN }, + [M_SYSREG_MSPLIM] =3D { "msplim", ARM_FEATURE_V8 }, + [M_SYSREG_PSPLIM] =3D { "psplim", ARM_FEATURE_V8 }, +}; + +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int = reg) +{ + int mode =3D reg & M_SYSREG_MODE_MASK; + bool secure; + uint32_t val; + + switch (mode) { + case M_SYSREG_CURRENT: + secure =3D env->v7m.secure; + break; + case M_SYSREG_NONSECURE: + secure =3D false; + break; + case M_SYSREG_SECURE: + secure =3D true; + break; + default: + return 0; + } + + reg &=3D M_SYSREG_REG_MASK; + if (reg >=3D ARRAY_SIZE(m_systemreg_def)) { + return 0; + } + if (!arm_feature(env, m_systemreg_def[reg].feature)) { + return 0; + } + + /* NOTE: This implementation shares a lot of logic with v7m_mrs. */ + switch (reg) { + case M_SYSREG_MSP: + val =3D *arm_v7m_get_sp_ptr(env, secure, false, true); + break; + case M_SYSREG_PSP: + val =3D *arm_v7m_get_sp_ptr(env, secure, true, true); + break; + case M_SYSREG_MSPLIM: + val =3D env->v7m.msplim[secure]; + break; + case M_SYSREG_PSPLIM: + val =3D env->v7m.psplim[secure]; + break; + case M_SYSREG_PRIMASK: + val =3D env->v7m.primask[secure]; + break; + case M_SYSREG_BASEPRI: + val =3D env->v7m.basepri[secure]; + break; + case M_SYSREG_FAULTMASK: + val =3D env->v7m.faultmask[secure]; + break; + case M_SYSREG_CONTROL: + /* + * NOTE: CONTROL has a mix of banked and non-banked bits. + * For "current", we emulate the MRS instruction. + * Unfortunately, this gives GDB no way to read the SFPA bit + * when the CPU is in a non-secure state. + */ + if (mode =3D=3D M_SYSREG_CURRENT) { + val =3D arm_v7m_mrs_control(env, secure); + } else { + val =3D env->v7m.control[secure]; + } + break; + default: + g_assert_not_reached(); + } + + return gdb_get_reg32(buf, val); +} + +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* TODO: Implement. */ + return 0; +} + +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + GString *s =3D g_string_new(NULL); + int i, ret; + + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, "\n"); + + QEMU_BUILD_BUG_ON(M_SYSREG_CURRENT !=3D 0); + ret =3D ARRAY_SIZE(m_systemreg_def); + + for (i =3D 0; i < ret; i++) { + if (arm_feature(env, m_systemreg_def[i].feature)) { + g_string_append_printf(s, + "\n", + m_systemreg_def[i].name, base_reg + i); + } + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + for (i =3D 0; i < ret; i++) { + g_string_append_printf(s, + "\= n", + m_systemreg_def[i].name, base_reg + (i | M_SYSREG_NONSECUR= E)); + } + for (i =3D 0; i < ret; i++) { + g_string_append_printf(s, + "\n= ", + m_systemreg_def[i].name, base_reg + (i | M_SYSREG_SECURE)); + } + QEMU_BUILD_BUG_ON(M_SYSREG_SECURE < M_SYSREG_NONSECURE); + ret |=3D M_SYSREG_SECURE; + } + + g_string_append_printf(s, ""); + + cpu->dyn_m_systemreg_xml.desc =3D g_string_free(s, false); + cpu->dyn_m_systemreg_xml.num =3D ret; + return ret; +} + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -330,6 +491,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const= char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") =3D=3D 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "arm-m-system.xml") =3D=3D 0) { + return cpu->dyn_m_systemreg_xml.desc; } return NULL; } @@ -389,4 +552,10 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), "system-registers.xml", 0); =20 + if (arm_feature(env, ARM_FEATURE_M)) { + gdb_register_coprocessor(cs, + arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, + arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), + "arm-m-system.xml", 0); + } } --=20 2.34.1