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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id d17-20020aa78691000000b0058d99337381sm10337011pfo.172.2023.02.14.08.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 08:31:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GVeEC1XgZv+0JDQi5rIgvqYs5+9oYvw4P4dYcheYUZc=; b=wNJcnkVeCLUUWJubZMojCT5vM33rZUwaNBdOfrZByqXZVgjWShKPi3ZIl/U9tr1cfU DUcNaKmEZ/Pgqz2FwcFx2qIh1LyhVE3zP7kAXHChGWA3FMOiGKb18Vm+T9pjrl74HZkw gc2u3egOHWkSN9ibzQTMf3HTb+9/oNR8mt7qSWaC6CEIggk/5MLMgrVTvrE6mPK+/D42 JzgLihajVUP1A3xnp03DVZxHTBuQAMAmnorI7N+5yKAtJws0dsSMwT6WkXJ5iAT1M3zi 2ZpFvgqkMKRnBePnTlkOAHWe1A3rbkkoCuhpcaOuuJYexVkTUTd9Ei6VVkQUvnVNWLI1 k/4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GVeEC1XgZv+0JDQi5rIgvqYs5+9oYvw4P4dYcheYUZc=; b=WVGbSfOA4okYDge9enjTOM9lRDHmx1PSJQf9KSLYkRFB1rkipuDBwMUxu2K4SJFmiP ETnTA2sWRB9E+6f5HPwhCx+uVAw3llPS6s/OoM7IREVyDy6SnvOVTloOd6AVYI5oi93z h/azYh2IszI+Ar2MTrQeGA8VCz+1a8mCZXmN0x+w3k2v8PFDOqH1kA6+yN62rF6izYPZ xSveMzDNLndXsQAFOFiYGhqFj1aUTxmtucMIfk4J4qOGUachBWugbcd5MBAElQ4QakDb 0vxJALq0uJZCWYUxUkFS/gD2yMyM+WVo1HZL2tsNalC3YnHjaSgYICv5MjCycS/yd7Ai 6Yog== X-Gm-Message-State: AO0yUKUD5riYYH8Kh+RgOsIhK04v1wHxc0xabZQKz/ARHYnpEP9bdAlE iNrfDVHEOv2imSi4oo+nt9RJcsI6KXKQYAehFQ4= X-Google-Smtp-Source: AK7set9wgg6/Gv2ua2B6pRDwxlyb4NtBY5B9J70eJTUVl7sg0MTOvFtIpzNM3EMi2i8kUCOjxZmyoQ== X-Received: by 2002:a62:1a46:0:b0:58d:b8f8:5e2f with SMTP id a67-20020a621a46000000b0058db8f85e2fmr2333523pfa.10.1676392271554; Tue, 14 Feb 2023 08:31:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH 13/14] target/arm: Export arm_v7m_get_sp_ptr Date: Tue, 14 Feb 2023 06:30:47 -1000 Message-Id: <20230214163048.903964-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230214163048.903964-1-richard.henderson@linaro.org> References: <20230214163048.903964-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676392335779100001 Content-Type: text/plain; charset="utf-8" From: David Reiss Allow the function to be used outside of m_helper.c. Move to be outside of ifndef CONFIG_USER_ONLY block. Rename from get_v7m_sp_ptr. Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 10 +++++ target/arm/m_helper.c | 84 +++++++++++++++++++++--------------------- 2 files changed, 51 insertions(+), 43 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 127a425961..6ad14048db 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1356,6 +1356,16 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp= ); /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); =20 +/* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + */ +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, + bool threadmode, bool spsel); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index c20bcac977..87e30c59a8 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -605,42 +605,6 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) arm_rebuild_hflags(env); } =20 -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool thread= mode, - bool spsel) -{ - /* - * Return a pointer to the location where we currently store the - * stack pointer for the requested security state and thread mode. - * This pointer will become invalid if the CPU state is updated - * such that the stack pointers are switched around (eg changing - * the SPSEL control bit). - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). - * Unlike that pseudocode, we require the caller to pass us in the - * SPSEL control bit value; this is because we also use this - * function in handling of pushing of the callee-saves registers - * part of the v8M stack frame (pseudocode PushCalleeStack()), - * and in the tailchain codepath the SPSEL bit comes from the exception - * return magic LR value from the previous exception. The pseudocode - * opencodes the stack-selection in PushCalleeStack(), but we prefer - * to make this utility function generic enough to do the job. - */ - bool want_psp =3D threadmode && spsel; - - if (secure =3D=3D env->v7m.secure) { - if (want_psp =3D=3D v7m_using_psp(env)) { - return &env->regs[13]; - } else { - return &env->v7m.other_sp; - } - } else { - if (want_psp) { - return &env->v7m.other_ss_psp; - } else { - return &env->v7m.other_ss_msp; - } - } -} - static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, uint32_t *pvec) { @@ -765,8 +729,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t= lr, bool dotailchain, !mode; =20 mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, pr= iv); - frame_sp_p =3D get_v7m_sp_ptr(env, M_REG_S, mode, - lr & R_V7M_EXCRET_SPSEL_MASK); + frame_sp_p =3D arm_v7m_get_sp_ptr(env, M_REG_S, mode, + lr & R_V7M_EXCRET_SPSEL_MASK); want_psp =3D mode && (lr & R_V7M_EXCRET_SPSEL_MASK); if (want_psp) { limit =3D env->v7m.psplim[M_REG_S]; @@ -1611,10 +1575,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * use 'frame_sp_p' after we do something that makes it invalid. */ bool spsel =3D env->v7m.control[return_to_secure] & R_V7M_CONTROL_= SPSEL_MASK; - uint32_t *frame_sp_p =3D get_v7m_sp_ptr(env, - return_to_secure, - !return_to_handler, - spsel); + uint32_t *frame_sp_p =3D arm_v7m_get_sp_ptr(env, return_to_secure, + !return_to_handler, spse= l); uint32_t frameptr =3D *frame_sp_p; bool pop_ok =3D true; ARMMMUIdx mmu_idx; @@ -1920,7 +1882,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) threadmode =3D !arm_v7m_is_handler_mode(env); spsel =3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; =20 - frame_sp_p =3D get_v7m_sp_ptr(env, true, threadmode, spsel); + frame_sp_p =3D arm_v7m_get_sp_ptr(env, true, threadmode, spsel); frameptr =3D *frame_sp_p; =20 /* @@ -2856,6 +2818,42 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t a= ddr, uint32_t op) =20 #endif /* !CONFIG_USER_ONLY */ =20 +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmod= e, + bool spsel) +{ + /* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). + * Unlike that pseudocode, we require the caller to pass us in the + * SPSEL control bit value; this is because we also use this + * function in handling of pushing of the callee-saves registers + * part of the v8M stack frame (pseudocode PushCalleeStack()), + * and in the tailchain codepath the SPSEL bit comes from the exception + * return magic LR value from the previous exception. The pseudocode + * opencodes the stack-selection in PushCalleeStack(), but we prefer + * to make this utility function generic enough to do the job. + */ + bool want_psp =3D threadmode && spsel; + + if (secure =3D=3D env->v7m.secure) { + if (want_psp =3D=3D v7m_using_psp(env)) { + return &env->regs[13]; + } else { + return &env->v7m.other_sp; + } + } else { + if (want_psp) { + return &env->v7m.other_ss_psp; + } else { + return &env->v7m.other_ss_msp; + } + } +} + ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, bool secstate, bool priv, bool negpri) { --=20 2.34.1