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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 08/12] hw/pci-host/q35: Turn PCI hole properties into class properties Date: Tue, 14 Feb 2023 14:14:37 +0100 Message-Id: <20230214131441.101760-9-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1676380661385100003 Content-Type: text/plain; charset="utf-8" These properties are class properties in i440fx. No need to handle them differently in q35. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 468bbfde51..2fc047a9c6 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -199,6 +199,22 @@ static void q35_host_class_init(ObjectClass *klass, vo= id *data) dc->user_creatable =3D false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name =3D "pci"; + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32= ", + q35_host_get_pci_hole_start, + NULL, NULL, NULL); + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32", + q35_host_get_pci_hole_end, + NULL, NULL, NULL); + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint= 64", + q35_host_get_pci_hole64_start, + NULL, NULL, NULL); + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64= ", + q35_host_get_pci_hole64_end, + NULL, NULL, NULL); } =20 static void q35_host_initfn(Object *obj) @@ -216,22 +232,6 @@ static void q35_host_initfn(Object *obj) qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); =20 - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", - q35_host_get_pci_hole_start, - NULL, NULL, NULL); - - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", - q35_host_get_pci_hole_end, - NULL, NULL, NULL); - - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", - q35_host_get_pci_hole64_start, - NULL, NULL, NULL); - - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", - q35_host_get_pci_hole64_end, - NULL, NULL, NULL); - object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, &pehb->size, OBJ_PROP_FLAG_READ); =20 --=20 2.39.1