From nobody Mon Feb 9 06:02:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1676281944; cv=none; d=zohomail.com; s=zohoarc; b=OKvOxpLlx0BinZrQuiyk4KimP12YZ9UJUdqK+vQ7VFFtrwlLL6to78251nL/dh0XQpxIQgOMfw+X+i7Pq9C/XNRS5iPyCThyYBaz3+sRrgc7Jwg28WXubegozRIif75kRlrW6mJIamNKGBtx4Zu73A0xPgUo6keNdkkgyG/pZew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676281944; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4QKkAudAos2AjBPPlJ+CdcOsr21B0VpLDJ2+88KdE5c=; b=Xt/segLhKZBN2PgQ1+7QIE1526MhJoIcboG6YlWt54/aR8U5ltTeH0HMBQBsWTcnSXTbX5R2wm4Sz6t6JislMlBbSQi2t11nuivy7CGIFckcsqFv7mqoY7X2GdUlgHEfJba51lGqh1yxz3f9FW78KDIV0NjghQDipPPpSGS0aEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676281944123544.1096964009272; Mon, 13 Feb 2023 01:52:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRVQG-0002zi-8Z; Mon, 13 Feb 2023 04:46:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRVPa-0001b7-IN for qemu-devel@nongnu.org; Mon, 13 Feb 2023 04:46:20 -0500 Received: from mga12.intel.com ([192.55.52.136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRVPU-0002o2-MQ for qemu-devel@nongnu.org; Mon, 13 Feb 2023 04:46:13 -0500 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Feb 2023 01:45:34 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.112]) by fmsmga007.fm.intel.com with ESMTP; 13 Feb 2023 01:45:30 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676281568; x=1707817568; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LbIBx9OtUQnbbe6kZCQOlJq8E9y1jdZtSG9kZ/TN2oM=; b=BxKAVdwXpeg64VmBwjN72KVFkuxcdBrrShOuY0LkD0rhBiML2c+eAR9L p6Bf94BTCjeJoGs5VAnINL2vGQhSMwFSzviEGIjfw/yYllpbEScio40Oz LHpjSEjPJMW4faPQ+U1kM8k3pgUSsmyX7wLJcsUFmTvClqXQyAigWAHxU 4du3svBgyjebYSUivPLRG4PWmkQgV4pwzX/GwNFMSh/j0YZ/drv2pHTMw N89kTvv2BD3aqlb8MVr4DXYn2xGlL1S8JZP2tBAM+WW1v69Cb9VhvJ+Fs 5xJ531QjruO4rKexmL0Hkn9j93hrFY3/VrIlYO7FmR7kd9ghtbZ5BptS/ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="310487067" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="310487067" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10619"; a="670760633" X-IronPort-AV: E=Sophos;i="5.97,293,1669104000"; d="scan'208";a="670760633" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini , Eric Blake , Markus Armbruster Cc: qemu-devel@nongnu.org, Zhenyu Wang , Dapeng Mi , Zhuocheng Ding , Robert Hoo , Sean Christopherson , Like Xu , Zhao Liu Subject: [RFC 38/52] i386: Introduce hybrid_core_type to CPUX86State Date: Mon, 13 Feb 2023 17:50:21 +0800 Message-Id: <20230213095035.158240-39-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230213095035.158240-1-zhao1.liu@linux.intel.com> References: <20230213095035.158240-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.136; envelope-from=zhao1.liu@linux.intel.com; helo=mga12.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1676281944720100005 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, x86 only supports two hybrid core types: Intel Core and Intel Atom [1], so add the core type definations for Intel Core and Intel Atom, and add hybrid_core_type in CPUX86State. [1]: SDM, vol.2, ch.3, 3.3 Instructions (A-L), CPUID, CPUID.1AH:EAX[bits 31-24]. Co-Developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu --- hw/i386/x86.c | 4 ++++ target/i386/cpu.c | 1 + target/i386/cpu.h | 8 ++++++++ 3 files changed, 13 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index a09df6d33fff..f381fdc43180 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -383,6 +383,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, CPUArchId *cpu_slot; X86CPUTopoIDs topo_ids; X86CPU *cpu =3D X86_CPU(dev); + CPUX86State *env =3D &cpu->env; MachineState *ms =3D MACHINE(hotplug_dev); X86MachineState *x86ms =3D X86_MACHINE(hotplug_dev); X86ApicidTopoInfo apicid_topo; @@ -564,6 +565,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } =20 + env->hybrid_core_type =3D + machine_topo_get_hybrid_core_type(ms, cpu->cluster_id, cpu->core_i= d); + cs =3D CPU(cpu); cs->cpu_index =3D idx; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7d6722ab3292..266e981b79e2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6845,6 +6845,7 @@ static void x86_cpu_initfn(Object *obj) X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); CPUX86State *env =3D &cpu->env; =20 + env->hybrid_core_type =3D INVALID_HYBRID_TYPE; cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 30b2aa6ab10d..bb4e370f9768 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1543,6 +1543,12 @@ typedef struct CPUCaches { CPUCacheInfo *l3_cache; } CPUCaches; =20 +typedef enum { + INVALID_HYBRID_TYPE =3D 0, + INTEL_ATOM_TYPE, + INTEL_CORE_TYPE, +} X86HybridCoreType; + typedef struct HVFX86LazyFlags { target_ulong result; target_ulong auxbits; @@ -1825,6 +1831,8 @@ typedef struct CPUArchState { uint32_t umwait; =20 TPRAccess tpr_access_type; + + X86HybridCoreType hybrid_core_type; } CPUX86State; =20 struct kvm_msrs; --=20 2.34.1