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[5.69.146.176]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b003da28dfdedcsm6312144wmq.5.2023.02.10.08.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 08:39:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=usy+gvwS+JxR9gEW4rdKIjKndc55aNyj2tFUAGWHkSo=; b=x9N9jFjug6CynwRuwkXCHfbmzOxpXYLc+dJdMrWTjdIRw3HhXJ6E5Pcjxstq5FF7gT 5mBwiCl+sMpYZ6mvzprOmVAhXFblo64VWEfl+gKyPu0b7vft+M09XJMjNh0IUkFExE6l UwW/i68WxR0y3J1d0dc2SHAVX+tMisjmx+5C5qpXg8qshNNZZB/gyzqNvFTg4DkSpfw+ 0dk5XCJRAd+SHMuQ8XOz30H3NOgfkc5wIlUQF07mkJfDu/zOAuu1UNOk+1aC4Jtni7vl UVczrnxJmIZU8h79CrpJKdup1RvL9Tko9+XGNoXX9gZQBrMyyglUf4iX60b9XP29IML5 qKhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=usy+gvwS+JxR9gEW4rdKIjKndc55aNyj2tFUAGWHkSo=; b=nYTwws3K/XIGeV316xzHbe41P6Ja3MXIoludFTZkU3khpldFOuq6+UHwhxCL3CyoRd RheNUszSrsGV6ez/WvGbDx7Xw+fLwURtZXlFDbR9f0/JzXqt2b9XufGriuzkARAmG/9e 0YUTAUNAL7jKJxoIRnwpN8WRS+4RjOcnrPc+ALxFy1C+0/crn2ypLp6sd+FvC7slYDh/ srlD5mS/NkgVSH2iDOV7kbwEr0ZttXlOrfJ9V0L6SxX3DHSI+x3ylVOiy8Bm6vXTAk0b KqC7mzmmkkAb6oH5bcNcNqhsIxc9gc2X/qopJNvcEix/M9SbckPnm30VUIb5WNzKCt0Y sxJQ== X-Gm-Message-State: AO0yUKURmfIvoZIot903/SqWLFE1IioqNdFWavlkIFK+zccam8UfsTsJ YbdpeEQTHZUUh8ykv+/P8O4scg== X-Google-Smtp-Source: AK7set99VAHRyUNQDOTmxUxPXwWlHsjlTjYFBzsERYN3LJTkMqBW/xtoc34/Njcs40dRrPjChBgLGg== X-Received: by 2002:a05:600c:4919:b0:3df:a04a:1a7 with SMTP id f25-20020a05600c491900b003dfa04a01a7mr13488556wmp.22.1676047178494; Fri, 10 Feb 2023 08:39:38 -0800 (PST) From: Jean-Philippe Brucker To: eric.auger@redhat.com Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, ola.hugosson@arm.com, Jean-Philippe Brucker Subject: [PATCH 0/2] hw/arm/smmu: Fixes for TTB1 Date: Fri, 10 Feb 2023 16:37:30 +0000 Message-Id: <20230210163731.970130-1-jean-philippe@linaro.org> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=jean-philippe@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676047209392100001 Content-Type: text/plain; charset="utf-8" Two small changes to support TTB1. Note that I had to modify the Linux driver in order to test this (see below), but other OSes might use TTB1. Jean-Philippe Brucker (2): hw/arm/smmu-common: Support 64-bit addresses hw/arm/smmu-common: Fix TTB1 handling hw/arm/smmu-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- 8< --- Linux hacks: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 8d772ea8a583..bf0ff699b64b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -276,6 +276,11 @@ #define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) #define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) #define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12) +#define CTXDESC_CD_0_TCR_T1SZ GENMASK_ULL(21, 16) +#define CTXDESC_CD_0_TCR_TG1 GENMASK_ULL(23, 22) +#define CTXDESC_CD_0_TCR_IRGN1 GENMASK_ULL(25, 24) +#define CTXDESC_CD_0_TCR_ORGN1 GENMASK_ULL(27, 26) +#define CTXDESC_CD_0_TCR_SH1 GENMASK_ULL(29, 28) #define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14) #define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30) @@ -293,6 +298,7 @@ #define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48) #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) +#define CTXDESC_CD_2_TTB1_MASK GENMASK_ULL(51, 4) /* * When the SMMU only supports linear context descriptor tables, pick a diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index f2425b0f0cd6..3a4343e60a54 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1075,8 +1075,8 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *s= mmu_domain, int ssid, * this substream's traffic */ } else { /* (1) and (2) */ - cdptr[1] =3D cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); - cdptr[2] =3D 0; + cdptr[1] =3D 0; + cdptr[2] =3D cpu_to_le64(cd->ttbr & CTXDESC_CD_2_TTB1_MASK); cdptr[3] =3D cpu_to_le64(cd->mair); /* @@ -2108,13 +2108,13 @@ static int arm_smmu_domain_finalise_s1(struct arm_s= mmu_domain *smmu_domain, cfg->cd.asid =3D (u16)asid; cfg->cd.ttbr =3D pgtbl_cfg->arm_lpae_s1_cfg.ttbr; - cfg->cd.tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | - FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | - FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | - FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | - FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | + cfg->cd.tcr =3D FIELD_PREP(CTXDESC_CD_0_TCR_T1SZ, tcr->tsz) | + FIELD_PREP(CTXDESC_CD_0_TCR_TG1, tcr->tg) | + FIELD_PREP(CTXDESC_CD_0_TCR_IRGN1, tcr->irgn) | + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN1, tcr->orgn) | + FIELD_PREP(CTXDESC_CD_0_TCR_SH1, tcr->sh) | FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | - CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; + CTXDESC_CD_0_TCR_EPD0 | CTXDESC_CD_0_AA64; cfg->cd.mair =3D pgtbl_cfg->arm_lpae_s1_cfg.mair; /* @@ -2212,6 +2212,7 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain, .pgsize_bitmap =3D smmu->pgsize_bitmap, .ias =3D ias, .oas =3D oas, + .quirks =3D IO_PGTABLE_QUIRK_ARM_TTBR1, .coherent_walk =3D smmu->features & ARM_SMMU_FEAT_COHERENCY, .tlb =3D &arm_smmu_flush_ops, .iommu_dev =3D smmu->dev, diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 38434203bf04..3fe154c9782d 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -677,6 +677,10 @@ static int dma_info_to_prot(enum dma_data_direction di= r, bool coherent, } } +/* HACK */ +#define VA_SIZE 39 +#define VA_MASK (~0ULL << VA_SIZE) + static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain, size_t size, u64 dma_limit, struct device *dev) { @@ -706,7 +710,7 @@ static dma_addr_t iommu_dma_alloc_iova(struct iommu_dom= ain *domain, iova =3D alloc_iova_fast(iovad, iova_len, dma_limit >> shift, true); - return (dma_addr_t)iova << shift; + return (dma_addr_t)iova << shift | VA_MASK; } static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie, @@ -714,6 +718,7 @@ static void iommu_dma_free_iova(struct iommu_dma_cookie= *cookie, { struct iova_domain *iovad =3D &cookie->iovad; + iova &=3D ~VA_MASK; /* The MSI case is only ever cleaning up its most recent allocation */ if (cookie->type =3D=3D IOMMU_DMA_MSI_COOKIE) cookie->msi_iova -=3D size;