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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=debug@rivosinc.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1675924396600100003 Content-Type: text/plain; charset="utf-8" zisslpcfi protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpcll` short for landing pad and check lower label value. If target of an indirect call or jmp is not `lpcll` then cpu/hart must raise an illegal instruction exception. This patch implements the mechanism using TCG. Target architecture branch instruction must define the end of a TB. Using this property, during translation of branch instruction, TB flag =3D FCFI_LP_EXPECTED can be set. Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a flag (fcfi_lp_expected) can be set in DisasContext. If `lpcll` gets translated, fcfi_lp_expected flag in DisasContext can be cleared. Else it'll fault. This patch also also adds flag for forward and backward cfi in DisasContext. Signed-off-by: Deepak Gupta Signed-off-by: Kip Walker --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 12 +++++++++ target/riscv/translate.c | 52 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8803ea6426..98b272bcad 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -644,6 +644,9 @@ FIELD(TB_FLAGS, VMA, 25, 1) /* Native debug itrigger */ FIELD(TB_FLAGS, ITRIGGER, 26, 1) =20 +/* Zisslpcfi needs a TB flag to track indirect branches */ +FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 63377abc2f..d15918f534 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -129,6 +129,18 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } =20 + if (cpu->cfg.ext_cfi) { + /* + * For Forward CFI, only the expectation of a lpcll at + * the start of the block is tracked (which can only happen + * when FCFI is enabled for the current processor mode). A jump + * or call at the end of the previous TB will have updated + * env->elp to indicate the expectation. + */ + flags =3D FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, + env->elp !=3D NO_LP_EXPECTED); + } + #ifdef CONFIG_USER_ONLY flags |=3D TB_FLAGS_MSTATUS_FS; flags |=3D TB_FLAGS_MSTATUS_VS; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..7d43d20fc3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -41,6 +41,7 @@ static TCGv load_val; /* globals for PM CSRs */ static TCGv pm_mask; static TCGv pm_base; +static TCGOp *cfi_lp_check; =20 #include "exec/gen-icount.h" =20 @@ -116,6 +117,10 @@ typedef struct DisasContext { bool itrigger; /* TCG of the current insn_start */ TCGOp *insn_start; + /* CFI extension */ + bool bcfi_enabled; + bool fcfi_enabled; + bool fcfi_lp_expected; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1166,11 +1171,44 @@ static void riscv_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); + ctx->bcfi_enabled =3D cpu_get_bcfien(env); + ctx->fcfi_enabled =3D cpu_get_fcfien(env); + ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); ctx->zero =3D tcg_constant_tl(0); } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) { + DisasContext *ctx =3D container_of(db, DisasContext, base); + + if (ctx->fcfi_lp_expected) { + /* + * Since we can't look ahead to confirm that the first + * instruction is a legal landing pad instruction, emit + * compare-and-branch sequence that will be fixed-up in + * riscv_tr_tb_stop() to either statically hit or skip an + * illegal instruction exception depending on whether the + * flag was lowered by translation of a CJLP or JLP as + * the first instruction in the block. + */ + TCGv_i32 immediate; + TCGLabel *l; + l =3D gen_new_label(); + immediate =3D tcg_temp_local_new_i32(); + tcg_gen_movi_i32(immediate, 0); + cfi_lp_check =3D tcg_last_op(); + tcg_gen_brcondi_i32(TCG_COND_EQ, immediate, 0, l); + tcg_temp_free_i32(immediate); + gen_exception_illegal(ctx); + gen_set_label(l); + /* + * Despite the use of gen_exception_illegal(), the rest of + * the TB needs to be generated. The TCG optimizer will + * clean things up depending on which path ends up being + * active. + */ + ctx->base.is_jmp =3D DISAS_NEXT; + } } =20 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) @@ -1225,6 +1263,7 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPURISCVState *env =3D cpu->env_ptr; =20 switch (ctx->base.is_jmp) { case DISAS_TOO_MANY: @@ -1235,6 +1274,19 @@ static void riscv_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cpu) default: g_assert_not_reached(); } + + if (ctx->fcfi_lp_expected) { + /* + * If the "lp expected" flag is still up, the block needs to take = an + * illegal instruction exception. + */ + tcg_set_insn_param(cfi_lp_check, 1, tcgv_i32_arg(tcg_constant_i32(= 1))); + } else { + /* + * LP instruction requirement was met, clear up LP expected + */ + env->elp =3D NO_LP_EXPECTED; + } } =20 static void riscv_tr_disas_log(const DisasContextBase *dcbase, --=20 2.25.1