From nobody Thu Apr 10 23:07:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675764615800663.547458030077; Tue, 7 Feb 2023 02:10:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPKuK-0000yS-UU; Tue, 07 Feb 2023 05:09:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPKuC-0000k0-Jl; Tue, 07 Feb 2023 05:08:52 -0500 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pPKuA-0002UP-0o; Tue, 07 Feb 2023 05:08:52 -0500 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4P9zNw6VMTz4wgv; Tue, 7 Feb 2023 21:08:48 +1100 (AEDT) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4P9zNt6CN8z4xwl; Tue, 7 Feb 2023 21:08:46 +1100 (AEDT) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 21/25] hw/arm/aspeed_ast10x0: Map the secure SRAM Date: Tue, 7 Feb 2023 11:07:40 +0100 Message-Id: <20230207100744.698694-22-clg@kaod.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230207100744.698694-1-clg@kaod.org> References: <20230207100744.698694-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=a43c=6D=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1675764617502100003 From: Philippe Mathieu-Daud=C3=A9 Some SRAM appears to be used by the Secure Boot unit and crypto accelerators. Name it 'secure sram'. Note, the SRAM base address was already present but unused (the 'SBC' index is used for the MMIO peripheral). Interestingly using CFLAGS=3D-Winitializer-overrides reports: ../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior in= itialization of this subobject [-Winitializer-overrides] [ASPEED_DEV_SBC] =3D 0x7E6F2000, ^~~~~~~~~~ ../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here [ASPEED_DEV_SBC] =3D 0x79000000, ^~~~~~~~~~ This fixes with Zephyr: uart:~$ rsa test rsa test vector[0]: [00:00:26.156,000] os: ***** BUS FAULT ***** [00:00:26.157,000] os: Precise data bus error [00:00:26.157,000] os: BFAR Address: 0x79000000 [00:00:26.158,000] os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a= 3: 0x00001800 [00:00:26.158,000] os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/l= r: 0x0001098d [00:00:26.158,000] os: xpsr: 0x81000000 [00:00:26.158,000] os: Faulting instruction address (r15/pc): 0x000= 1e1bc [00:00:26.158,000] os: >>> ZEPHYR FATAL ERROR 0: CPU exception on C= PU 0 [00:00:26.158,000] os: Current thread: 0x38248 (shell_uart) [00:00:26.165,000] os: Halting system Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Delevoryas [ clg: Fixed size of Secure Boot Controller Memory ] Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 +++ hw/arm/aspeed_ast10x0.c | 11 ++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9a5e3c0bac..bd1e03e78a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -71,6 +71,7 @@ struct AspeedSoCState { AspeedSMCState spi[ASPEED_SPIS_NUM]; EHCISysBusState ehci[ASPEED_EHCIS_NUM]; AspeedSBCState sbc; + MemoryRegion secsram; UnimplementedDeviceState sbc_unimplemented; AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; @@ -105,6 +106,7 @@ struct AspeedSoCClass { const char *cpu_type; uint32_t silicon_rev; uint64_t sram_size; + uint64_t secsram_size; int spis_num; int ehcis_num; int wdts_num; @@ -143,6 +145,7 @@ enum { ASPEED_DEV_SCU, ASPEED_DEV_ADC, ASPEED_DEV_SBC, + ASPEED_DEV_SECSRAM, ASPEED_DEV_EMMC_BC, ASPEED_DEV_VIDEO, ASPEED_DEV_SRAM, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 1a06269cb1..592a19d988 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -21,7 +21,7 @@ =20 static const hwaddr aspeed_soc_ast1030_memmap[] =3D { [ASPEED_DEV_SRAM] =3D 0x00000000, - [ASPEED_DEV_SBC] =3D 0x79000000, + [ASPEED_DEV_SECSRAM] =3D 0x79000000, [ASPEED_DEV_IOMEM] =3D 0x7E600000, [ASPEED_DEV_PWM] =3D 0x7E610000, [ASPEED_DEV_FMC] =3D 0x7E620000, @@ -221,6 +221,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], &s->sram); + memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram", + sc->secsram_size, &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], + &s->secsram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -400,6 +408,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *= klass, void *data) sc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); sc->silicon_rev =3D AST1030_A1_SILICON_REV; sc->sram_size =3D 0xc0000; + sc->secsram_size =3D 0x40000; /* 256 * KiB */ sc->spis_num =3D 2; sc->ehcis_num =3D 0; sc->wdts_num =3D 4; --=20 2.39.1