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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675685899972100001 armv7m_nvic_neg_prio_requested() is called via arm_cpu_reset_hold() during CPU realize() time, when the NVIC isn't yet realized: (lldb) bt * frame #0: 0x10059ed5c armv7m_nvic_neg_prio_requested(opaque=3D0x118008= 7b0, secure=3Dtrue) at armv7m_nvic.c:404:9 frame #1: 0x100383018 arm_v7m_mmu_idx_for_secstate [inlined] arm_v7m_m= mu_idx_for_secstate_and_priv(...) at m_helper.c:2882:19 frame #2: 0x10038300c arm_v7m_mmu_idx_for_secstate(..., secstate=3Dtru= e) at m_helper.c:2893:12 frame #3: 0x10036e9bc arm_mmu_idx_el(...) at helper.c:11799:16 [artifi= cial] frame #4: 0x100366cd4 arm_rebuild_hflags [inlined] rebuild_hflags_inte= rnal(env=3D0x118411f30) at helper.c:12129:25 frame #5: 0x100366c18 arm_rebuild_hflags(env=3D0x118411f30) at helper.= c:12142:19 frame #6: 0x10035f1c4 arm_cpu_reset_hold(...) at cpu.c:541:5 [artifici= al] frame #7: 0x10066b354 resettable_phase_hold(obj=3D0x118410000, opaque= =3D0x000000000, ...) at resettable.c:0 frame #8: 0x10066ac40 resettable_assert_reset(obj=3D0x118410000, ...) = at resettable.c:60:5 frame #9: 0x10066ab1c resettable_reset(obj=3D0x118410000, type=3DRESET= _TYPE_COLD) at resettable.c:45:5 frame #10: 0x100669568 device_cold_reset(...) at qdev.c:255:5 [artifici= al] frame #11: 0x10000ca28 cpu_reset(cpu=3D0x118410000) at cpu-common.c:114= :5 frame #12: 0x10035ec74 arm_cpu_realizefn(dev=3D0x118410000, errp=3D0x16= fdfb910) at cpu.c:2145:5 frame #13: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13 frame #14: 0x100671b98 property_set_bool(obj=3D0x118410000, ...) at obj= ect.c:2285:5 frame #15: 0x10066fdf4 object_property_set(obj=3D0x118410000, name=3D"r= ealized", ...) at object.c:1420:5 frame #16: 0x100673da8 object_property_set_qobject(...) at qom-qobject.= c:28:10 frame #17: 0x10067026c object_property_set_bool(...) at object.c:1489:15 frame #18: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial] frame #19: 0x1003101bc armv7m_realize(dev=3D0x118008480, ...) at armv7m= .c:344:10 frame #20: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13 frame #21: 0x100671b98 property_set_bool(obj=3D0x118008480, ...) at obj= ect.c:2285:5 frame #22: 0x10066fdf4 object_property_set(obj=3D0x118008480, name=3D"r= ealized", ...) at object.c:1420:5 frame #23: 0x100673da8 object_property_set_qobject(...) at qom-qobject.= c:28:10 frame #24: 0x10067026c object_property_set_bool(...) at object.c:1489:15 frame #25: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial] frame #26: 0x100092da8 sysbus_realize(...) at sysbus.c:256:12 [artifici= al] frame #27: 0x100350e1c armsse_realize(dev=3D0x118008150, ...) at armsse= .c:1043:14 frame #28: 0x10066a3e0 device_set_realized(...) at qdev.c:519:13 frame #29: 0x100671b98 property_set_bool(obj=3D0x118008150, ...) at obj= ect.c:2285:5 frame #30: 0x10066fdf4 object_property_set(obj=3D0x118008150, name=3D"r= ealized", ...) at object.c:1420:5 frame #31: 0x100673da8 object_property_set_qobject(...) at qom-qobject.= c:28:10 frame #32: 0x10067026c object_property_set_bool(...) at object.c:1489:15 frame #33: 0x100669600 qdev_realize(...) at qdev.c:292:12 [artificial] frame #34: 0x100092da8 sysbus_realize(...) at sysbus.c:256:12 [artifici= al] frame #35: 0x100349354 mps2tz_common_init(machine=3D0x118008000) at mps= 2-tz.c:834:5 frame #36: 0x10008e6b8 machine_run_board_init(machine=3D0x118008000, ..= .) at machine.c:1405:5 (lldb) frame select 12 frame #12: 0x10035ec74 arm_cpu_realizefn(dev=3D0x118410000, errp=3D0x16fdfb= 910) at cpu.c:2145:5 2142 } 2143 2144 qemu_init_vcpu(cs); -> 2145 cpu_reset(cs); 2146 2147 acc->parent_realize(dev, errp); 2148 } Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/armv7m_nvic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e54553283f..d9c7e414bc 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -399,6 +399,11 @@ bool armv7m_nvic_neg_prio_requested(NVICState *s, bool= secure) * mean we don't allow FAULTMASK_NS to actually make the execution * priority negative). Compare pseudocode IsReqExcPriNeg(). */ + + if (!DEVICE(s)->realized) { /* XXX Why are we called while not realize= d? */ + return false; + } + if (s->cpu->env.v7m.faultmask[secure]) { return true; } --=20 2.38.1