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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id t4-20020a17090ad14400b00219220edf0dsm7451215pjw.48.2023.01.30.13.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 13:49:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/VaqdvyZanWttEJ3248OXSPTZwbXJrxyYFWhISw3Lc=; b=Pnpu+NeYSfflk2/uS35/5KA7hdSiTsPug2q2gR+3oLHBL1fq+HbGedzOsBe2lx3I7R 74laWPid4oGjAjt1q7774F3CS7wSOMchjN4itDJIfnmqSt70xm9a5aa3rGaWr3c+Hi4S oEZY4iNggFnJSlmcIwIzvU36MjtBpmdx+kbPYjcx4pUGsaQRxaMYN1GYFqBLtl1NaYfG hT3BUnTDn8q1Pffmft0qRJJ4LqF/YF9c5xM4Utq5OC6CfxMzUjkE4z+m7PZ7vPbyXM7Q pfsjRaNBwVQTIFEDPETtkRvBMh4p8DuIGv6dk3JzN/ZZ2iBGx67JlkzTY+PBTY2jykdI WYhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/VaqdvyZanWttEJ3248OXSPTZwbXJrxyYFWhISw3Lc=; b=hGWukw80xoyhnOVECMhP3Mzo3EFmk0miaXGKswuzDshfIzadJJ+Olx/apdZZ/Q/Kqu 1a+6XpfkC6ZNvK5sanPOe8p2DjFDMHwEqr1ZWa3Izy2bRJP4pfSW3mujsrnDLBqnYoNT qhlCl52ykLGDMjzMl9ffkPwnm/DwC/sts5U/oGf7xmdyULBBtx3RbleP465DCy+EjIgs VOkcXT9x0ay12MkhpE+EWTjAhrUhY4AMsPfpZIZZfP/5IQM0V1mvQe5YgaIvHHYgTVeU TkwamqhH0BgoA4/1Jbs8hySuR6no4pTEDYK4sLEhFEqMyR10zpSx2MGFBymIB1zZPMNV 9Qdw== X-Gm-Message-State: AFqh2krhL0MBJoONEM6yq//a/9JFv3N2Osf75osKfYHrqC5N7adaVnpa 5NsNxMtlREFZQea8kYfy98Lu0a2On4dnePIp X-Google-Smtp-Source: AMrXdXv6CKX4+Akk/Rj5GjLs3h+rdAKyCLQSfOLsD5b/t4jlj50i5uevKRpbCxjxgDwQqqsZbWxqxQ== X-Received: by 2002:a17:90a:b798:b0:229:d641:9ef2 with SMTP id m24-20020a17090ab79800b00229d6419ef2mr45754474pjr.40.1675115346647; Mon, 30 Jan 2023 13:49:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v6 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Mon, 30 Jan 2023 11:48:19 -1000 Message-Id: <20230130214844.1158612-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230130214844.1158612-1-richard.henderson@linaro.org> References: <20230130214844.1158612-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1675115402034100003 Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now, but only fill in slots required for the call we're about to make. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 3 +++ tcg/tcg.c | 19 +++++++++++++++++ tcg/tci.c | 44 ++++++++++++++++++++-------------------- tcg/tci/tcg-target.c.inc | 10 ++++----- 4 files changed, 49 insertions(+), 27 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1414ab4d5b..7140a76a73 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -160,10 +160,13 @@ typedef enum { #if TCG_TARGET_REG_BITS =3D=3D 32 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index edc6185bf4..5792d72e08 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -570,6 +570,22 @@ static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { + /* + * libffi does not support __int128_t, so we have forced Int128 + * to use the structure definition instead of the builtin type. + */ + static ffi_type *ffi_type_i128_elements[3] =3D { + &ffi_type_uint64, + &ffi_type_uint64, + NULL + }; + static ffi_type ffi_type_i128 =3D { + .size =3D 16, + .alignment =3D __alignof__(Int128), + .type =3D FFI_TYPE_STRUCT, + .elements =3D ffi_type_i128_elements, + }; + switch (argmask) { case dh_typecode_void: return &ffi_type_void; @@ -583,6 +599,8 @@ static ffi_type *typecode_to_ffi(int argmask) return &ffi_type_sint64; case dh_typecode_ptr: return &ffi_type_pointer; + case dh_typecode_i128: + return &ffi_type_i128; } g_assert_not_reached(); } @@ -613,6 +631,7 @@ static void init_ffi_layouts(void) /* Ignoring the return type, find the last non-zero field. */ nargs =3D 32 - clz32(typemask >> 3); nargs =3D DIV_ROUND_UP(nargs, 3); + assert(nargs <=3D MAX_CALL_IARGS); =20 ca =3D g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); ca->cif.rtype =3D typecode_to_ffi(typemask & 7); diff --git a/tcg/tci.c b/tcg/tci.c index eeccdde8bc..022fe9d0f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -470,12 +470,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; - void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; - /* Other call_slots entries initialized at first use (see below). */ - call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -498,26 +495,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - /* - * Set up the ffi_avalue array once, delayed until now - * because many TB's do not make any calls. In tcg_gen_callN, - * we arranged for every real argument to be "left-aligned" - * in each 64-bit slot. - */ - if (unlikely(call_slots[0] =3D=3D NULL)) { - for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { - call_slots[i] =3D &stack[i]; - } - } - - tci_args_nl(insn, tb_ptr, &len, &ptr); - - /* Helper functions may need to access the "return address" */ - tci_tb_ptr =3D (uintptr_t)tb_ptr; - { - void **pptr =3D ptr; - ffi_call(pptr[1], pptr[0], stack, call_slots); + void *call_slots[MAX_CALL_IARGS]; + ffi_cif *cif; + void *func; + unsigned i, s, n; + + tci_args_nl(insn, tb_ptr, &len, &ptr); + func =3D ((void **)ptr)[0]; + cif =3D ((void **)ptr)[1]; + + n =3D cif->nargs; + for (i =3D s =3D 0; i < n; ++i) { + ffi_type *t =3D cif->arg_types[i]; + call_slots[i] =3D &stack[s]; + s +=3D DIV_ROUND_UP(t->size, 8); + } + + /* Helper functions may need to access the "return address= " */ + tci_tb_ptr =3D (uintptr_t)tb_ptr; + ffi_call(cif, func, stack, call_slots); } =20 switch (len) { @@ -542,6 +539,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, */ memcpy(®s[TCG_REG_R0], stack, 8); break; + case 3: /* Int128 */ + memcpy(®s[TCG_REG_R0], stack, 16); + break; default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e3b0ff303f..c1d34d7bd1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -203,7 +203,7 @@ static const int tcg_target_call_iarg_regs[] =3D { }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); - tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); return TCG_REG_R0 + slot; } =20 @@ -573,11 +573,11 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *func, =20 if (cif->rtype =3D=3D &ffi_type_void) { which =3D 0; - } else if (cif->rtype->size =3D=3D 4) { - which =3D 1; } else { - tcg_debug_assert(cif->rtype->size =3D=3D 8); - which =3D 2; + tcg_debug_assert(cif->rtype->size =3D=3D 4 || + cif->rtype->size =3D=3D 8 || + cif->rtype->size =3D=3D 16); + which =3D ctz32(cif->rtype->size) - 1; } new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); insn =3D deposit32(insn, 0, 8, INDEX_op_call); --=20 2.34.1