From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708210; cv=none; d=zohomail.com; s=zohoarc; b=Gpw6IqjpM1mxNMfccWbfoDKwDjWJb/fxM4uuLcgr53S5hCLVfpdeQp7Z/o/3AqfjloWPCS0btbcuc5nrv8Mut7sV2zRnn+xhGZOIPpcmRsRNUyRGBcKterlMdT598rSKunAmOM57q9MDVzCXdMm42iLe68gjoExfAUhlMo07rUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708210; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uYhih3WzBvljJJYreEPqLN+cqoryMajrlaD+6+DuEUE=; b=NibM6xDnmCZeLLyzDFcxwFRqgTy+lX/v7FFsyphvRqB0Y/QEx2NHD2bZGOUUw1pGYvScUk0T3Fd+rju0RwBYCUmJZ7AfGGfqEpH3SPnWbdOt6mkSWYfRBIQGsRLsTMR8iXQty5ZO7ZGO0tJ2V+SqWTB/Q6kNRbA4xneDwN0xskw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708210240800.6374003756059; Wed, 25 Jan 2023 20:43:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu28-00008u-Fn; Wed, 25 Jan 2023 23:38:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu25-00006k-97 for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:41 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu22-0004OJ-0l for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:40 -0500 Received: by mail-pl1-x636.google.com with SMTP id a18so929857plm.2 for ; Wed, 25 Jan 2023 20:38:30 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uYhih3WzBvljJJYreEPqLN+cqoryMajrlaD+6+DuEUE=; b=QB7XvaAqwKb4rD54eZlKGzqsNTqdxS49BBmc11l7JBsY0yShF5aXtE/4D2/KvLydBD m1dARh+pxH6xkhNAb4/MZZf27iqisM0ZgsFoiR9umk0DSWfSBHlQwe7tmCEHSo3/+WDo 36bSzuvu/ecdKbDEwoB05p7WhlnYJnR9b+C4qA0yCxSugsqGOB4Mm2SHn5b/G7CDzuA+ aGvBrXf8nORTyA68UTYtui2Dh/VJGtbyFer0T6cF3P0dmrkudkMD6QTxfGhWiDhGFovz 7+eXeWSV7xkoHUHlA2cyEvVsg+Kb/ZR3e4xd5iZ5jyiHeLnUGCuilEN5lF5OBybY63Xm qsZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uYhih3WzBvljJJYreEPqLN+cqoryMajrlaD+6+DuEUE=; b=dzqap4O23bKubZLCXulvUwa0DsCjTt85T0dyWtnZWX7hbJ3dUOMVp8Ip+Z06eja5Wa 5t18/nLt5MtU702q5wFino49CdoNYPojzfd6kkSdLGBnVI8FXiNVn5BuC3o+vwEJoJq2 +ZYLHVz5cQGk6g19RtslnxjgLQTL4UyHSotE+7wcqtVHmOA37GKRktHNrYK3UpaXOp7w BzxXPyuLPUClwJX43w56PxFjFMIETqwGLf5IJLzt33w03TvENBT6eSN8l/TDbuBCvILU ozdEDsdHdfm1bL3yP+O8MBmggMfvpIpdRoko+RuuR5bOGqbewoNAeIlVp39W0n7nBd2v M2gw== X-Gm-Message-State: AO0yUKU2lZf4BlCgj+6zrfCBh+Fcu/YVxsNXMQ6fiuYbdBCQaeGDk15Q toLWb8TLkfVtEYEvZ8VXelNGg+r/idHsCreOByQ= X-Google-Smtp-Source: AK7set9ryFzEqUW/4+bqQ6hqY1Lp1gdMRKBACOO1c/eAVrr8PyRCxEBVbH+JZLgx68m8+Rf8cWoSgA== X-Received: by 2002:a17:90a:182:b0:22b:ec6a:be66 with SMTP id 2-20020a17090a018200b0022bec6abe66mr780352pjc.31.1674707909491; Wed, 25 Jan 2023 20:38:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 01/36] tcg: Define TCG_TYPE_I128 and related helper macros Date: Wed, 25 Jan 2023 18:37:49 -1000 Message-Id: <20230126043824.54819-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708211982100011 Begin staging in support for TCGv_i128 with Int128. Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 7 +++++++ include/tcg/tcg.h | 17 ++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index bc6698b19f..b8d1140dc7 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_i128 i128 #define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 @@ -40,6 +41,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_i128 Int128 #define dh_ctype_f16 uint32_t #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 @@ -71,6 +73,7 @@ #define dh_retvar_decl0_noreturn void #define dh_retvar_decl0_i32 TCGv_i32 retval #define dh_retvar_decl0_i64 TCGv_i64 retval +#define dh_retval_decl0_i128 TCGv_i128 retval #define dh_retvar_decl0_ptr TCGv_ptr retval #define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) =20 @@ -78,6 +81,7 @@ #define dh_retvar_decl_noreturn #define dh_retvar_decl_i32 TCGv_i32 retval, #define dh_retvar_decl_i64 TCGv_i64 retval, +#define dh_retvar_decl_i128 TCGv_i128 retval, #define dh_retvar_decl_ptr TCGv_ptr retval, #define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) =20 @@ -85,6 +89,7 @@ #define dh_retvar_noreturn NULL #define dh_retvar_i32 tcgv_i32_temp(retval) #define dh_retvar_i64 tcgv_i64_temp(retval) +#define dh_retvar_i128 tcgv_i128_temp(retval) #define dh_retvar_ptr tcgv_ptr_temp(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) =20 @@ -95,6 +100,7 @@ #define dh_typecode_i64 4 #define dh_typecode_s64 5 #define dh_typecode_ptr 6 +#define dh_typecode_i128 7 #define dh_typecode_int dh_typecode_s32 #define dh_typecode_f16 dh_typecode_i32 #define dh_typecode_f32 dh_typecode_i32 @@ -104,6 +110,7 @@ =20 #define dh_callflag_i32 0 #define dh_callflag_i64 0 +#define dh_callflag_i128 0 #define dh_callflag_ptr 0 #define dh_callflag_void 0 #define dh_callflag_noreturn TCG_CALL_NO_RETURN diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9a0ae7d20b..8b7e61e7a5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -270,6 +270,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_I128, =20 TCG_TYPE_V64, TCG_TYPE_V128, @@ -351,13 +352,14 @@ typedef tcg_target_ulong TCGArg; in tcg/README. Target CPU front-end code uses these types to deal with TCG variables as it emits TCG code via the tcg_gen_* functions. They come in several flavours: - * TCGv_i32 : 32 bit integer type - * TCGv_i64 : 64 bit integer type - * TCGv_ptr : a host pointer type - * TCGv_vec : a host vector type; the exact size is not exposed - to the CPU front-end code. - * TCGv : an integer type the same size as target_ulong - (an alias for either TCGv_i32 or TCGv_i64) + * TCGv_i32 : 32 bit integer type + * TCGv_i64 : 64 bit integer type + * TCGv_i128 : 128 bit integer type + * TCGv_ptr : a host pointer type + * TCGv_vec : a host vector type; the exact size is not exposed + to the CPU front-end code. + * TCGv : an integer type the same size as target_ulong + (an alias for either TCGv_i32 or TCGv_i64) The compiler's type checking will complain if you mix them up and pass the wrong sized TCGv to a function. =20 @@ -377,6 +379,7 @@ typedef tcg_target_ulong TCGArg; =20 typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; +typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708157720552.6560484767488; Wed, 25 Jan 2023 20:42:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu26-00007W-Sg; Wed, 25 Jan 2023 23:38:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu25-00006h-5r for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:41 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu21-0004ON-Tq for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:40 -0500 Received: by mail-pj1-x1031.google.com with SMTP id o13so538635pjg.2 for ; Wed, 25 Jan 2023 20:38:31 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+sAayCS/0n8o12l1+Nu9dY41aCtQpJmApolHzbMbLL8=; b=NeYD11B0N8/wIy7wpHawxSplemFxpN57G8mMXJCwRdpTVg1rn/af4aTTh3i//6UDLl epD4E22y5l/Rr2cHGAY/+Sb1UhL/fKF/PBW5gXmIOWzQ9Okt/pvVUktKkte96GjMmDYI s+cZcL8wCw8k5o/jhP/Moub+bYdOcg69Hws5CDmBLngMh6aGgV7/0Xe6/hIFL/vObNvR 4PoDNV2RFkFLoy28WShcNvH1p59PoPOrMHdVd0ptor1a3rFVUmLYPo/1EObSdemTmD+o JndqK7yjAFnRrmq1TUm+8kVmTChxzBda3vrYmfxpvSvTvVnXm0nI997BeAGU7EMeAiaU 1nxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+sAayCS/0n8o12l1+Nu9dY41aCtQpJmApolHzbMbLL8=; b=unznZcPwb6UkB09v9LzJGN0rCBmNtjyqNuTjnv0Dzo4FS0oeOT/zLVIZMsWKyGLx3m RoxkRtncJ7hNXik58XPr+Z0uzigL9t4GDdjhuJt2h7kmGpZ+BSxwYalZcQnJqqeJ7N5M ScUD+eUtpX+LFgftT3ruagCNRAwunoMJViP1/Qj7jzUahNLLAZ3k+Qt3OSufONBUn4uV B4whyKKRW3r91613R8KcxcZLNeNib+ijG5PAj5gRZwqXrtCJgvFGyaim8Vbs5z9bPpQU rFT/dlCzu2HbJZ73+p+ps9EAswhvfh5XYXF0FJjCPUF6oQtchNtABZIHmA41NKItJ6q7 Fq5Q== X-Gm-Message-State: AFqh2kpbV/RQmwAMLtOfwek4coTbi+1J/JcSonfJK98Fj3lYysahPu02 ZbfGtSA9fz+ItqPaND7cU4oXF00vsrawFwjCJfI= X-Google-Smtp-Source: AMrXdXs0RzvCIKTV8Ag1u9a2KDTnreQ55d2KV2JR0EPrmu9aZ45VQj/xwSLEwjxP2LM3T9+wnuTm8w== X-Received: by 2002:a17:90a:d344:b0:229:ef6c:4139 with SMTP id i4-20020a17090ad34400b00229ef6c4139mr25572738pjx.22.1674707910921; Wed, 25 Jan 2023 20:38:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 02/36] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL Date: Wed, 25 Jan 2023 18:37:50 -1000 Message-Id: <20230126043824.54819-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1674708159782100003 Many hosts pass and return 128-bit quantities like sequential 64-bit quantities. Treat this just like we currently break down 64-bit quantities for a 32-bit host. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index d502327be2..ffddda96ed 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -707,11 +707,22 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out =3D 64 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; + assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); + break; + case dh_typecode_i128: + info->nr_out =3D 128 / TCG_TARGET_REG_BITS; + info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ + switch (/* TODO */ TCG_CALL_RET_NORMAL) { + case TCG_CALL_RET_NORMAL: + assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); + break; + default: + qemu_build_not_reached(); + } break; default: g_assert_not_reached(); } - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); =20 /* * Parse and place function arguments. @@ -733,6 +744,9 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_ptr: type =3D TCG_TYPE_PTR; break; + case dh_typecode_i128: + type =3D TCG_TYPE_I128; + break; default: g_assert_not_reached(); } @@ -772,6 +786,19 @@ static void init_call_layout(TCGHelperInfo *info) } break; =20 + case TCG_TYPE_I128: + switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + case TCG_CALL_ARG_EVEN: + layout_arg_even(&cum); + /* fall through */ + case TCG_CALL_ARG_NORMAL: + layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); + break; + default: + qemu_build_not_reached(); + } + break; + default: g_assert_not_reached(); } @@ -1690,11 +1717,13 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) op->args[pi++] =3D temp_arg(ret); break; case 2: + case 4: tcg_debug_assert(ret !=3D NULL); - tcg_debug_assert(ret->base_type =3D=3D ret->type + 1); + tcg_debug_assert(ret->base_type =3D=3D ret->type + ctz32(n)); tcg_debug_assert(ret->temp_subindex =3D=3D 0); - op->args[pi++] =3D temp_arg(ret); - op->args[pi++] =3D temp_arg(ret + 1); + for (i =3D 0; i < n; ++i) { + op->args[pi++] =3D temp_arg(ret + i); + } break; default: g_assert_not_reached(); --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708166; cv=none; d=zohomail.com; s=zohoarc; b=H7s3sadMUgJqSXHXT6P6Uhfbt27xlQCV5pj+8tLn00rEO5ERiim66urTqFNYRAlXJkypD6GsySNJBCnnGU4jZmGlet5NckhtI9BnMIHW5kL4GXb34N1/56DkWM/7DIc9zN3NCwiNzmSgDXbiJFBHkh2nM+VxkGTPiTCIFkJv2qA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708166; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P9o9Kqlm4R8WHQAINVfaYH28J5DgA1McwtQxHNZ+nmQ=; b=HLqZdIk8hT29kXtkICD8fWjQgn3uHmI4TtzH6/hURjSk7AlccVEwXSqZyPrHWf/cd4qAZ+spCzHXoRZ/7PnvrsgPYDlFTOzGDMfyyZSUFgsTQBvF4Mcp/Yl9IkBGgi2wPtjfM4enIj+uLHks2k/WitBpsu4D2Dm8vB5ibxRxRE8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708166860343.0791791775764; Wed, 25 Jan 2023 20:42:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu27-00007y-B9; Wed, 25 Jan 2023 23:38:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu23-00006N-Gd for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:40 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu21-0004OR-TW for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:39 -0500 Received: by mail-pl1-x636.google.com with SMTP id z13so912795plg.6 for ; Wed, 25 Jan 2023 20:38:33 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P9o9Kqlm4R8WHQAINVfaYH28J5DgA1McwtQxHNZ+nmQ=; b=i+6TR3WypDeSkb5T1+LwAjTNom+Yf8SM7IBIzWXbFHMZuYkBnP43Ni+tfT+MDvQVZw wf7tg0OkDXu3kbWEDxlB3hpvyuUxY9HMEjp9q2JIBm1tCbXYMOsO3eBjr3dn1qTYncOd Y+/mQiRwfH7lg8GfcEyCeuxjqxnKoPdXTNneCv4mxqdPfiaCKqqQ23NteAziPHLyI1pm zAE5TZ7Sry6FXEa0M2JpIqy2g/sZUGoFYNhTdzR7YbytPGcrKOYAdt3noYeXvU4aRA9U VFbnBTMcLYtRPiSy26rSS0RN9vtxWhI5c+0ScKM6rsU412qag9S/SLFEoduDhKtgwzr4 f4jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P9o9Kqlm4R8WHQAINVfaYH28J5DgA1McwtQxHNZ+nmQ=; b=HN1DMQLn6jnQyxtjW6yI7OXOqOBf6AFVzmBpX2XmwBjzcuCF6Wr0f+xPjcOYNK3DuY eu/P2gPIbDZxMsRtSwHy3AENeXlul5V1pmcnc2pIk3t4hfpxga8o65Na8hnvF6DMBRQ9 N0DEEYHKGyCJaKYJzJCV3L0UnZqsWHOQTphaEIzcV3sdi3uWcOA7J1hRvR5nSb8wbNl7 aM26l3sZXmt32CEX574NFC2vjwnaB/k3zvEXKI2A8VoQEUbh/Li25SgzbdYSHms/mIUU NbHKsBJ5JPKe3pPFI2UrTDdNjEip9fM23c821N/YHSD0jeKArApCITKoP9EWecfliQZS Nk4w== X-Gm-Message-State: AO0yUKXPU/WzBHrD/JGFtEYhjtEPKJkCOZfhhEUISzzVcb+NzbdLALX9 ecscLtBqAA2RqD9JhCDTIHVLVMK9ZnXnTPhSl4c= X-Google-Smtp-Source: AK7set+eOxFwVO7ZJa84DpuV4a5NWuJYuxFzwpFBMXJ/wDPoCwW2KQYSC/0WEWAJ98NqRxR2Lnk2Eg== X-Received: by 2002:a17:90a:1da:b0:22b:e2ef:6845 with SMTP id 26-20020a17090a01da00b0022be2ef6845mr10552033pjd.41.1674707912408; Wed, 25 Jan 2023 20:38:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Date: Wed, 25 Jan 2023 18:37:51 -1000 Message-Id: <20230126043824.54819-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708167777100001 Content-Type: text/plain; charset="utf-8" When allocating a temp to the stack frame, consider the base type and allocate all parts at once. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index ffddda96ed..ff30f5e141 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3264,11 +3264,12 @@ static bool liveness_pass_2(TCGContext *s) =20 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - int size =3D tcg_type_size(ts->type); - int align; intptr_t off; + int size, align; =20 - switch (ts->type) { + /* When allocating an object, look at the full type. */ + size =3D tcg_type_size(ts->base_type); + switch (ts->base_type) { case TCG_TYPE_I32: align =3D 4; break; @@ -3299,13 +3300,26 @@ static void temp_allocate_frame(TCGContext *s, TCGT= emp *ts) tcg_raise_tb_overflow(s); } s->current_frame_offset =3D off + size; - - ts->mem_offset =3D off; #if defined(__sparc__) - ts->mem_offset +=3D TCG_TARGET_STACK_BIAS; + off +=3D TCG_TARGET_STACK_BIAS; #endif - ts->mem_base =3D s->frame_temp; - ts->mem_allocated =3D 1; + + /* If the object was subdivided, assign memory to all the parts. */ + if (ts->base_type !=3D ts->type) { + int part_size =3D tcg_type_size(ts->type); + int part_count =3D size / part_size; + + ts -=3D ts->temp_subindex; + for (int i =3D 0; i < part_count; ++i) { + ts[i].mem_offset =3D off + i * part_size; + ts[i].mem_base =3D s->frame_temp; + ts[i].mem_allocated =3D 1; + } + } else { + ts->mem_offset =3D off; + ts->mem_base =3D s->frame_temp; + ts->mem_allocated =3D 1; + } } =20 /* Assign @reg to @ts, and update reg_to_temp[]. */ --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708186; cv=none; d=zohomail.com; s=zohoarc; b=PbhLLhqVcSce0IKFljDyZhEoaRDHyHIXudPlBqCGqK5Lq85QdgRvBZir8QsypqEIPsURagcVSE74i2ZOUBzzmAkt3Biq7WHBUCBErRX8e2NNpvkG+rYYsb1/v+NAxmV9lagdczpjdL/YeS8PLPDhD0XzNw9qeKGzZarQO7hjhuc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708186; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/EDu6W1nQrzLPv/TIoFL920trAdqJMEoGNsBxL3KJJk=; b=HLz+ZHAw4voTj/3UtufSTQhmNGakkDg/86xfnS9mI2dQbMCDHhhncfx5cbgBGqw17THPNquSwX8FmC/dAJq6hCxPcmAHyF3+ceK6rFmA0Pd/cVYtP2V5NhszkmoZvO5kyvXSUiQPoF6Y5r9iK/O867+RIsiLAtrI4/ouKIU+MxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708186824311.38446569288215; Wed, 25 Jan 2023 20:43:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu28-00009H-Lv; Wed, 25 Jan 2023 23:38:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu25-00006v-FD for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:41 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu22-0004OX-0m for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:41 -0500 Received: by mail-pl1-x62f.google.com with SMTP id jl3so901689plb.8 for ; Wed, 25 Jan 2023 20:38:35 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/EDu6W1nQrzLPv/TIoFL920trAdqJMEoGNsBxL3KJJk=; b=CuWPi6UR0aNb/T+Lme1tNJJzreWcwO0Srxtyhvv6VUFl7vYbSNbvZbgfaAgdjnQY98 0wnN9+8HnzFkKaXI5iS3USGp/jzCVT2J8/zf7Yxi042rz+LYbyHTMbOllDSzbeE6eiyg WC3THFCy7+H2fIsZ+IptfL51eXmLAHp8WZtsSeot6hyMVFx3wQWEkUGbdr6FCxKJ3PV6 Ta7FC0PgRZ7xhpsOSot3tXtomfPkJkxg70+T7A8cSR7rO9EXcctuqtWh3UI4MvidyE6T iPRj9c0vJPP6Ov4KC3yf5cTT3hOtVZPfU2p3AfVqRTiV/ySn8vSSmRiWNu2L9z82ufrw 2Hzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/EDu6W1nQrzLPv/TIoFL920trAdqJMEoGNsBxL3KJJk=; b=ajbECYfrBRt1RHeWO7f8cAo9W43H8EoD2IWRdNyhK0z4h//JoJAuG6xpviBXVACQ61 7JEddYyDj42ZWRXskr1Rgbrboq385mGqFOIGJKoIYUleyLhVj7IJxp0fw6IwvN2/8fEt vbGcedQEvY5ONp1NEW0KLEP87wDALnGez5LkAOXkgCMDT+Y+S8YjZ3T0LTh3FkPEe+iF pbboCMzxZRJEfPjYUXD1wViA31dUc5X5cpfnKFHgDVusxSIiMjGcApcQjyH6hUCX/qbD bW2IQx4dFasR/V+ly75UAnv98z6WamTd1XVj/ptlsyfS6hOeWO9PCkk9S1w8hDi7TdL8 ucPg== X-Gm-Message-State: AO0yUKXiMtzv0iVmzpAWG/EgryPU2NLQ9ROWOgV0rguM7rvmPzheCnJy leOY/5ZA8aRJy6HJRaCy1p8hUltlBlIgI58zCIw= X-Google-Smtp-Source: AK7set9mMO4OaKYL4GVIIHGzwScxahJMNYgilVFN8Xm06IhyXCdqLpyHv8TtlrnebTShdsYdYWcZqQ== X-Received: by 2002:a17:90b:384c:b0:22b:f895:54bc with SMTP id nl12-20020a17090b384c00b0022bf89554bcmr681605pjb.47.1674707914067; Wed, 25 Jan 2023 20:38:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Daniel Henrique Barboza Subject: [PATCH v5 04/36] tcg: Introduce tcg_out_addi_ptr Date: Wed, 25 Jan 2023 18:37:52 -1000 Message-Id: <20230126043824.54819-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708187963100001 Implement the function for arm, i386, and s390x, which will use it. Add stubs for all other backends. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++++++ tcg/arm/tcg-target.c.inc | 20 ++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 8 ++++++++ tcg/loongarch64/tcg-target.c.inc | 7 +++++++ tcg/mips/tcg-target.c.inc | 7 +++++++ tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 7 +++++++ tcg/s390x/tcg-target.c.inc | 7 +++++++ tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 7 +++++++ 11 files changed, 86 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index ff30f5e141..a561ef3ced 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -104,6 +104,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g) + __attribute__((unused)); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 330d26b395..bd6da72678 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1102,6 +1102,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg rd, tcg_out_insn(s, 3305, LDR, 0, rd); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + /* Define something more legible for general use. */ #define tcg_out_ldst_r tcg_out_insn_3310 =20 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0f5f9f4925..6e9e9b9b3f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2581,6 +2581,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + int enc, opc =3D ARITH_ADD; + + /* All of the easiest immediates to encode are positive. */ + if (imm < 0) { + imm =3D -imm; + opc =3D ARITH_SUB; + } + enc =3D encode_imm(imm); + if (enc >=3D 0) { + tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); + tcg_out_dat_reg(s, COND_AL, opc, rd, rs, + TCG_REG_TMP, SHIFT_IMM_LSL(0)); + } +} + /* Type is always V128, with I64 elements. */ static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg r= h) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c71c3e664d..7b573bd287 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1069,6 +1069,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val =3D=3D (int8_t)val) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index ce4a153887..b6e2ff6213 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -417,6 +417,13 @@ static void tcg_out_addi(TCGContext *s, TCGType type, = TCGReg rd, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_andi(s, ret, arg, 0xff); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 6e000d8e69..d419c4c1fc 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -550,6 +550,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int fla= gs) { /* ret and arg can't be register tmp0 */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 8d6899cf40..85f84fe59e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1125,6 +1125,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg ret, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static bool mask_operand(uint32_t c, int *mb, int *me) { uint32_t lsb, test; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 01cb67ef7b..383331025a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -559,6 +559,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 218318feb2..d8fd755ef0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1073,6 +1073,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTyp= e type, TCGArg val, return false; } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); +} + static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, int msb, int lsb, int ofs, int z) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index dd406bc065..4b834f3f1e 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -496,6 +496,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index bc452007c6..33551b43dc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -557,6 +557,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, const TCGHelperInfo *info) { --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fb2fdMOMcanVFyUwDsIR4Y1AU3aUWkiDhIm8eRBZLcI=; b=mPr8hDqGfvxlSTOaxygQFGmktopCI4txoZeYFN5Qah5J3BxcM75r3uulrAZxYdWGM9 oEQIPYyezeNXQ7T8kfEfa/JrOqKGLLLcU3Q9Ec8A/jDGAPFnd9UPRrJwhseN3Z5X38k7 zuaDgPRKaZZXWuJIQTMsuvTLhNZmOUZLP5J14S3xgQx5ES5ngbDNSH1DzA289EHqaMio h9jAJL15aw+WeOG7v/gvtVbnsyvzFNBq4Ns+0gzivERt5tk/bvor4jdWHyJlc7u1ZtWq Vuy0FqD8/1X9VVCEyUUvvTI/WPc5v18tEV/aElS7f3ed0IxFUXQifCD8VnpaQQ/gU/st PbrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fb2fdMOMcanVFyUwDsIR4Y1AU3aUWkiDhIm8eRBZLcI=; b=iW6qSJh11Oi+cRK+zeLoV7GZowSn0RtnuKmwGB4h23W+0ihmG875lVJEJ0/l9fcA03 iri5fSreH0J8ivO5ZluKzy5QmTCg6ixaiYY4JkZkYT8B8Lp2Y8DzuY6ByWx+WpPEV4nM NR3famdRbkBZnmemG6hvh87hXBgzHXwZSPd4YllM2AhgXSxfaUsX7FI+/pVn1lCAekvB +of8Rf3oJQO+ecMJnJuGSCeBei9e4dAgliwV9/BwT9KDLy9hZnpYaHTUR3Mu3qwWciqy OcNTV9Fzxz1qastfhizSW6mDLRCwvNJXgZ1q9zoN51Tsn5FUBkOPTnzGAA39uUDA/JCW WEZg== X-Gm-Message-State: AFqh2kp347DEZlx6FegZlUc7W/HjBn96EBWAqoWN5HID/mt5ikLZcc6n OR5EY7dmdroLLYbhfR9/cczZZOW9G2i/zTcFGH0= X-Google-Smtp-Source: AMrXdXslPSp+ulQ096vqlbi+T53/FSxtK0Aq/nKhNWENYbShWzHzuYwKsmejgEXWKVy9mV3s85T3wg== X-Received: by 2002:a17:90a:fa43:b0:229:e620:6c19 with SMTP id dt3-20020a17090afa4300b00229e6206c19mr28121844pjb.0.1674707915653; Wed, 25 Jan 2023 20:38:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Date: Wed, 25 Jan 2023 18:37:53 -1000 Message-Id: <20230126043824.54819-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708199947100002 Content-Type: text/plain; charset="utf-8" These will be used by some hosts, both 32 and 64-bit, to pass and return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 3 + tcg/tcg.c | 135 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 135 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 6e50aeba3a..2ec1ea01df 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -36,6 +36,7 @@ */ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference */ } TCGCallReturnKind; =20 typedef enum { @@ -44,6 +45,8 @@ typedef enum { TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ + TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ } TCGCallArgumentKind; =20 typedef struct TCGCallArgumentLoc { diff --git a/tcg/tcg.c b/tcg/tcg.c index a561ef3ced..644dc53196 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -104,8 +104,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g) - __attribute__((unused)); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, @@ -683,6 +682,38 @@ static void layout_arg_normal_n(TCGCumulativeArgs *cum, cum->arg_slot +=3D n; } =20 +static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc =3D &info->in[cum->info_in_idx]; + int n =3D 128 / TCG_TARGET_REG_BITS; + + /* The first subindex carries the pointer. */ + layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); + + /* + * The callee is allowed to clobber memory associated with + * structure pass by-reference. Therefore we must make copies. + * Allocate space from "ref_slot", which will be adjusted to + * follow the parameters on the stack. + */ + loc[0].ref_slot =3D cum->ref_slot; + + /* + * Subsequent words also go into the reference slot, but + * do not accumulate into the regular arguments. + */ + for (int i =3D 1; i < n; ++i) { + loc[i] =3D (TCGCallArgumentLoc){ + .kind =3D TCG_CALL_ARG_BY_REF_N, + .arg_idx =3D cum->arg_idx, + .tmp_subindex =3D i, + .ref_slot =3D cum->ref_slot + i, + }; + } + cum->info_in_idx +=3D n; + cum->ref_slot +=3D n; +} + static void init_call_layout(TCGHelperInfo *info) { int max_reg_slots =3D ARRAY_SIZE(tcg_target_call_iarg_regs); @@ -718,6 +749,14 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_RET_NORMAL: assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); break; + case TCG_CALL_RET_BY_REF: + /* + * Allocate the first argument to the output. + * We don't need to store this anywhere, just make it + * unavailable for use in the input loop below. + */ + cum.arg_slot =3D 1; + break; default: qemu_build_not_reached(); } @@ -796,6 +835,9 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_ARG_NORMAL: layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); break; + case TCG_CALL_ARG_BY_REF: + layout_arg_by_ref(&cum, info); + break; default: qemu_build_not_reached(); } @@ -811,7 +853,39 @@ static void init_call_layout(TCGHelperInfo *info) assert(cum.info_in_idx <=3D ARRAY_SIZE(info->in)); /* Validate the backend has enough argument space. */ assert(cum.arg_slot <=3D max_reg_slots + max_stk_slots); - assert(cum.ref_slot <=3D max_stk_slots); + + /* + * Relocate the "ref_slot" area to the end of the parameters. + * Minimizing this stack offset helps code size for x86, + * which has a signed 8-bit offset encoding. + */ + if (cum.ref_slot !=3D 0) { + int ref_base =3D 0; + + if (cum.arg_slot > max_reg_slots) { + int align =3D __alignof(Int128) / sizeof(tcg_target_long); + + ref_base =3D cum.arg_slot - max_reg_slots; + if (align > 1) { + ref_base =3D ROUND_UP(ref_base, align); + } + } + assert(ref_base + cum.ref_slot <=3D max_stk_slots); + + if (ref_base !=3D 0) { + for (int i =3D cum.info_in_idx - 1; i >=3D 0; --i) { + TCGCallArgumentLoc *loc =3D &info->in[i]; + switch (loc->kind) { + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: + loc->ref_slot +=3D ref_base; + break; + default: + break; + } + } + } + } } =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; @@ -1738,6 +1812,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) =20 switch (loc->kind) { case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: op->args[pi++] =3D temp_arg(ts); break; =20 @@ -4404,6 +4480,27 @@ static void load_arg_normal(TCGContext *s, const TCG= CallArgumentLoc *l, } } =20 +static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, + intptr_t ref_off, TCGRegSet *allocated_regs) +{ + TCGReg reg; + int stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); + + if (stk_slot < 0) { + reg =3D tcg_target_call_iarg_regs[arg_slot]; + tcg_reg_free(s, reg, *allocated_regs); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_regset_set_reg(*allocated_regs, reg); + } else { + reg =3D tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], + *allocated_regs, 0, false); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + stk_slot * sizeof(tcg_target_long)); + } +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs =3D TCGOP_CALLO(op); @@ -4427,6 +4524,16 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) case TCG_CALL_ARG_EXTEND_S: load_arg_normal(s, loc, ts, &allocated_regs); break; + case TCG_CALL_ARG_BY_REF: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + loc->ref_slot * sizeof(tcg_target_long), + &allocated_regs); + break; + case TCG_CALL_ARG_BY_REF_N: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + break; default: g_assert_not_reached(); } @@ -4458,6 +4565,19 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) save_globals(s, allocated_regs); } =20 + /* + * If the ABI passes a pointer to the returned struct as the first + * argument, load that now. Pass a pointer to the output home slot. + */ + if (info->out_kind =3D=3D TCG_CALL_RET_BY_REF) { + TCGTemp *ts =3D arg_temp(op->args[0]); + + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_r= egs); + } + tcg_out_call(s, tcg_call_func(op), info); =20 /* Assign output registers and emit moves if needed. */ @@ -4474,6 +4594,15 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) ts->mem_coherent =3D 0; } break; + + case TCG_CALL_RET_BY_REF: + /* The callee has performed a write through the reference. */ + for (i =3D 0; i < nb_oargs; i++) { + TCGTemp *ts =3D arg_temp(op->args[i]); + ts->val_type =3D TEMP_VAL_MEM; + } + break; + default: g_assert_not_reached(); } --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708224; cv=none; d=zohomail.com; s=zohoarc; b=Zg+hpSpIOxmrRYjzUE9ZuWGz9RZEZQzvlJLvanRWbjZuvXmsWzTdPph11y5EgY5qfK18z5FzWuPXUwW9FqoAqvcYoK3cAFzTA10r7R+Sj00pnDEo7V6+GLmHqQ4cZBRyholrCTWmF17VRu2hwjfMA7alvlF2+Nzdz1JskJegQgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708224; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HtofnOjW26HEs26DUdRP/wQozgYxE2HJ6TDjGcvyj3E=; b=OA1rc+br+zLJ3YCxU78uov6wcPwuQxBfaohED4fU4EYWkQ6I2j8WBmFTpl9iuMeIVFcdNXi9CC2mCU5qy7izpXILzhA0Ea08cOHW+QCAfxpyTuGx7A+vCcC5bgEFLXVy4wLyPQQT5Pv6eUG3OE+dIcnEM15600qFu+MM2FTtaQs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708224050916.5510815248939; Wed, 25 Jan 2023 20:43:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2A-00009h-Fc; Wed, 25 Jan 2023 23:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu27-00007k-7x for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:43 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu22-0004Om-Kl for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:42 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9so896446pll.9 for ; Wed, 25 Jan 2023 20:38:38 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HtofnOjW26HEs26DUdRP/wQozgYxE2HJ6TDjGcvyj3E=; b=vopGOk79IRE+FcWMcndRFzRuZ8Q2GTUOxxAw5Byz35WYY1PKwNC62H9SpvF6xNlyZg pIwtLLijnOUm3KOeqg13TXvATqK3FJcHiFUE5RkQaCukyxfIWrGmkdUDu9cdnIGZ3NdP 8LlRMsXxogOUTKk3BkwHFJjk8nsAKF3XqLH4H5LEoBLX7DPp5C8Fpf+rughwKWe+BbhI S0A1ppfGpUtQkyy1iTu/li3io3wS1hVzrj5TQi0MCBk53ufbOvgkDkV0rHVlOk6IMIsE +h8l7u8YMziCYZioev4/a8cImmf+b8dmvgkMXdM+oQ2G9aSGFgG6fRrwliRyJQS7k9mg S1pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HtofnOjW26HEs26DUdRP/wQozgYxE2HJ6TDjGcvyj3E=; b=sLm7i/t7tj2GZxfDpMDY2WLyec4Kn6KEm8T154GlQsvyh5YUVv0FQRPhEZl9KJV6pF Qd8YpxBJWB0OigShfV8VCQAgisPL4UTF+O/YEXNqkvP37OJ/9mzrt6Iq4ZbZOmBlK8hC Nwuo/6XSpzBrUFoU16q6wCbtVzGH7An9mxeYMqfYaxoWZ4c61ladvsYwciAlgGMEpCig 48HHlEjxTRSqe+TSLKZ4PAOyzwfoHEhVJNFIbadb2AFJHZAe9S2GWzWBOZjpeS58essm 4YYOPBQm6dGx20QkqYLpBP5Tof1S6ITitmj77ny6xjzpyTXOs+vZkrp76UTjIo5efQ0A 0M7g== X-Gm-Message-State: AO0yUKUAOkuzjeKtqHQ5NA03rZm2CWqmKR13vOHvDYJmlXJtPkor4rM5 WQQUAkz3vQYK+Z77MBNvI8b2ZeVXXzivnAIEUCk= X-Google-Smtp-Source: AK7set+DfQ4owLmqHqHj7WOI5bTr/uT5sRXQI5D99b/pdR6lpdm0Ic3uBWZqGbYMJDXXrrAH/bJFbQ== X-Received: by 2002:a17:90b:1d08:b0:22c:1331:9c53 with SMTP id on8-20020a17090b1d0800b0022c13319c53mr3120257pjb.14.1674707917157; Wed, 25 Jan 2023 20:38:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Daniel Henrique Barboza Subject: [PATCH v5 06/36] tcg: Introduce tcg_target_call_oarg_reg Date: Wed, 25 Jan 2023 18:37:54 -1000 Message-Id: <20230126043824.54819-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708226070100006 Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Extend the set of registers for ARM to r0-r3 to match the ABI: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#result= -return Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 ++++++--- tcg/aarch64/tcg-target.c.inc | 10 +++++++--- tcg/arm/tcg-target.c.inc | 10 +++++++--- tcg/i386/tcg-target.c.inc | 16 ++++++++++------ tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 10 ++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ tcg/tci/tcg-target.c.inc | 12 ++++++------ 11 files changed, 72 insertions(+), 46 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 644dc53196..72ac76926a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -151,6 +151,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, const TCGHelperInfo *info); +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -740,14 +741,16 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out =3D 64 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ switch (/* TODO */ TCG_CALL_RET_NORMAL) { case TCG_CALL_RET_NORMAL: - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case TCG_CALL_RET_BY_REF: /* @@ -4585,7 +4588,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) case TCG_CALL_RET_NORMAL: for (i =3D 0; i < nb_oargs; i++) { TCGTemp *ts =3D arg_temp(op->args[i]); - TCGReg reg =3D tcg_target_call_oarg_regs[i]; + TCGReg reg =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i= ); =20 /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bd6da72678..fde3b30ad1 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] =3D { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 }; -static const int tcg_target_call_oarg_regs[1] =3D { - TCG_REG_X0 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_X0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6e9e9b9b3f..d06ac60c15 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -79,9 +79,13 @@ static const int tcg_target_reg_alloc_order[] =3D { static const int tcg_target_call_iarg_regs[4] =3D { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 }; -static const int tcg_target_call_oarg_regs[2] =3D { - TCG_REG_R0, TCG_REG_R1 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_R0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 7b573bd287..2f0a9521bf 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -109,12 +109,16 @@ static const int tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_EDX -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + switch (kind) { + case TCG_CALL_RET_NORMAL: + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return slot ? TCG_REG_EDX : TCG_REG_EAX; + default: + g_assert_not_reached(); + } +} =20 /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index b6e2ff6213..c5f55afd68 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #ifndef CONFIG_SOFTMMU #define USE_GUEST_BASE (guest_base !=3D 0) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d419c4c1fc..80748d892e 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const TCGReg tcg_target_call_oarg_regs[2] =3D { - TCG_REG_V0, - TCG_REG_V1 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_V0 + slot; +} =20 static const tcg_insn_unit *tb_ret_addr; static const tcg_insn_unit *bswap32_addr; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 85f84fe59e..f3fec14118 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R10 }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R3, - TCG_REG_R4 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_R3 + slot; +} =20 static const int tcg_target_callee_save_regs[] =3D { #ifdef _CALL_DARWIN diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 383331025a..558de127ef 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d8fd755ef0..844532156b 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -402,9 +402,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R6, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R2, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_R2; +} =20 #define S390_CC_EQ 8 #define S390_CC_LT 4 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4b834f3f1e..ccc4144f7c 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -132,12 +132,12 @@ static const int tcg_target_call_iarg_regs[6] =3D { TCG_REG_O5, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_O0 + slot; +} =20 #define INSN_OP(x) ((x) << 30) #define INSN_OP2(x) ((x) << 22) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 33551b43dc..e3b0ff303f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -200,12 +200,12 @@ static const int tcg_target_reg_alloc_order[] =3D { /* No call arguments via registers. All will be stored on the "stack". */ static const int tcg_target_call_iarg_regs[] =3D { }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_R1 -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + return TCG_REG_R0 + slot; +} =20 #ifdef CONFIG_DEBUG_TCG static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708216; cv=none; d=zohomail.com; s=zohoarc; b=ES0rKwOLRvCSPq+khwDttPG9d/G+0oa6bPs3lok1GXngYykaaTrh+WTBcXQkT9pH0F5sG6ecjOeTdAi3c+WXswBmtGZqekEGd2DxGNEH1ZroMdtbIXxKTevUWYTRsNQs9V+I68KgsdCODbBJCTWfJ0vWzhrpZpES1WJ9K56SxAg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708216; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IayjR5zNq60WEhTjWTVhpDuC8xofWVLS8FB3KMbySkk=; b=dj0fWgOqsYzU+gsTAToWVAUjGeXeoRanhZzN1e7rsIox/KparQqtxF7uhrhI7cDRisuFl//j19cuHT+7557sSrzW77pkVFJcg9JGA2dGXKeYQJ0JSqlRmDFkhhDcCx5vOvFkYNPIdddxazPDCu5soanueKTaAmQmVIsWn6PUIS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708216683666.8893134136553; Wed, 25 Jan 2023 20:43:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2A-00009a-5w; Wed, 25 Jan 2023 23:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu26-00007M-HR for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:42 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu24-0004P7-Ru for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:42 -0500 Received: by mail-pj1-x102b.google.com with SMTP id o13so538805pjg.2 for ; Wed, 25 Jan 2023 20:38:39 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IayjR5zNq60WEhTjWTVhpDuC8xofWVLS8FB3KMbySkk=; b=E2aF/CV7GEEdbqctV19XbNXYt9hI1iB3wvMIN4VT7w9rbkLvrFVVooBOq9PBPXXYWF RYzBGuidaFITG335vizaLK7o8E+r6KHAvU1l0Cee5TJ6uI1epr9eRNyXrrHrDeCCdJLd sAYeKZy2COuMQFq391VTIGDIG27+ROCqx0Mhsa7RYuoIyN7k3wmvuJaDtF6EoWh8vBMn TRgWBLSmbAZSnbk5jQxR/8s5R6vmorNjO4clVLa1PjU0fLWieFnslSpBLoFzVG5MmS8L pRC/tWPGcBRqkLbIaQjJi+//bUgZGhhRArpGJSDHskoRFR+bmfHt0PElpweWKwqMDbV3 gw8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IayjR5zNq60WEhTjWTVhpDuC8xofWVLS8FB3KMbySkk=; b=pI0fYtgdXKGCnzp+Yw1wwKCF1fTszsTGAH+3r78T+kYYvUoE1juuJ+T7+MR7A2lUYB 2CbK/Hf10QEv73HaJ2ca4zbUzCMukb4J/Qdrn2nJc4m0QWrH/7HkraZe6VvIZijq+0SA Nua6ogiBMBmuW+GhlQzVanrVv6+aVQye4AHpiRp8W7eLuFN4eO/Mu1AFxV8X9res7Wb+ 1MVHbGqy8wzO2FqCSU3JM+Gk6PySuZrUnjaMCw0xVdK2sOJo/yNJhiescPQxLZGViTSr oJ+SwOD4pmI62H2I9wP9YTlSQQAhNHtPlsOvDxosj7NgDtl9BUDg3wjtZmG5LTgeqbkz oirA== X-Gm-Message-State: AFqh2krohY5XpdZnN2Mjou0yp3bLx5+ecgEzuOLjO3FHOTQgRyB/ycfL oZUEfQ0KkcVqU3/iWRn86w6Cb2Bg/brkI061vu8= X-Google-Smtp-Source: AMrXdXtBSIOJEmjsGz3BOMCbXWrkyzRnxek8u7LUWNkSqE+aoJAVCBKLgjKG2OICE/K68h1K7nQgcg== X-Received: by 2002:a17:90b:1112:b0:21a:1f5f:e798 with SMTP id gi18-20020a17090b111200b0021a1f5fe798mr36008904pjb.48.1674707918652; Wed, 25 Jan 2023 20:38:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 07/36] tcg: Add TCG_CALL_RET_BY_VEC Date: Wed, 25 Jan 2023 18:37:55 -1000 Message-Id: <20230126043824.54819-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708217989100001 This will be used by _WIN64 to return i128. Not yet used, because allocation is not yet enabled. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2ec1ea01df..33f1d8b411 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -37,6 +37,7 @@ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ TCG_CALL_RET_BY_REF, /* for i128, by reference */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ } TCGCallReturnKind; =20 typedef enum { diff --git a/tcg/tcg.c b/tcg/tcg.c index 72ac76926a..084e3c3a54 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -752,6 +752,10 @@ static void init_call_layout(TCGHelperInfo *info) /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; + case TCG_CALL_RET_BY_VEC: + /* Query the single register now to trigger any assert early. = */ + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); + break; case TCG_CALL_RET_BY_REF: /* * Allocate the first argument to the output. @@ -4598,6 +4602,21 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) } break; =20 + case TCG_CALL_RET_BY_VEC: + { + TCGTemp *ts =3D arg_temp(op->args[0]); + + tcg_debug_assert(ts->base_type =3D=3D TCG_TYPE_I128); + tcg_debug_assert(ts->temp_subindex =3D=3D 0); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + tcg_out_st(s, TCG_TYPE_V128, + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), + ts->mem_base->reg, ts->mem_offset); + } + /* fall through to mark all parts in memory */ + case TCG_CALL_RET_BY_REF: /* The callee has performed a write through the reference. */ for (i =3D 0; i < nb_oargs; i++) { --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708223; cv=none; d=zohomail.com; s=zohoarc; b=TVegBXlWnoad8QN5ayHXceJar9ZWmx41KAPZ7Bm2SedEuLO5htSNhTqgU0etXD/TgHpe9tRFGMo6tTyL5Svg50gZHfne8SrYsOzmHGc4GyrOWXCZ5ZeEEfgpRZoZb7BXBJ93fEDM4yNsHlUHr6THv/RecdK3DtT6Y3AkgZ4aFhs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708223; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Hbm3ifGwuCI4UMEGM6ZiBOelwkHZlrSPUn3TtCQ2uk=; b=TFBk5T9I2/Tm7u5Fngk77+nbxAC1gm7svJrADRiRNtOR6DmTCfr3snorul4n47n9Nup0WoYrjOi5hTgHgJASx4PmyF8E1JpjUUX8YlsEDBzAXde2ouBi2DRuVKg03hr/8w0iHj3SiETMjKvyTgeeYs76hIE8k+2Qw9fNNmP3s3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167470822388079.69642434377943; Wed, 25 Jan 2023 20:43:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2A-0000AH-PR; Wed, 25 Jan 2023 23:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu27-00008a-JA for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:43 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu25-0004Qk-PK for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:43 -0500 Received: by mail-pj1-x102b.google.com with SMTP id v6-20020a17090ad58600b00229eec90a7fso5407419pju.0 for ; Wed, 25 Jan 2023 20:38:41 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5Hbm3ifGwuCI4UMEGM6ZiBOelwkHZlrSPUn3TtCQ2uk=; b=flaj75ZQRCZCDy3NcxKoufINa8DhnySheEHIGtoJ0s+p045IVhYzYzH2+P3f3a/1Qg D+SOE9VzQcHcWUZ4GzbwAbiuvmS3egjAjbQ3BoCC4wm4YkmILdTZ1RFnnuizmginrGjm kosNrZNO5vPYT+TVBwPNdz5elkksuQ1e0ANi/gyhZGhrrcWd3/dA+U2rFnANGUC303SA G3WFFv+KLqqZmzQycV1TpaWk4HGHVRvvPzl4MU9Ys7lEdpoMzcdiRmbgTUzwrgVzktHR tby7YSJqiL4kGb88RjRfM5eeKt3ksk2dJRH+CVH1MVJdRTZGDik12FZN5HBRtxPegr0e 6slQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Hbm3ifGwuCI4UMEGM6ZiBOelwkHZlrSPUn3TtCQ2uk=; b=EGBaHgENvTpNvYb3Zfqnd9AnMLwT2MQsU8W7C9/BHxKiVfCAvhpq3xgXZAPg6wd9BP OOoTezaJi91BKSoGmrIwOmfbwgigCRhyc3gZzMyroE3/llTxSWA33h7qQ0/NKcO2OLIi VFe//QpL1Ylnl+xCX5E5nWscElQmU5onZ2H9sFTCXH91+X4kgL3HTFuQ5amQOnVEoi73 O/sGJ0SyKxGORghfsH4MCFrNK+hFMobRn+rnwmheq5gjqNxCWyzCxgHukRvy3Ku7JyO4 h8QwFjlrB3hfACNRDJ93uuQAut2gOGiYVdvU5M19EQ4Mb/weLi+W3LPgJAZyhhWW6nTR oRHg== X-Gm-Message-State: AFqh2krEGunsv04jFUshSv7DoeUNNb4IwNIeR+oaaCpq2EHbVhYPpiv6 RVe45VjveSa59bbFOSNjrr7UdNP7UtjnQTS2C7c= X-Google-Smtp-Source: AMrXdXs6Rt2OdiTL2jPc3/XAtGUIZQMV5UwDDwzVtxmEaCcxalW7Mr25yqdZgGHTBmPWOIDSju8YjQ== X-Received: by 2002:a17:90b:2395:b0:226:f35f:923b with SMTP id mr21-20020a17090b239500b00226f35f923bmr36287673pjb.2.1674707920316; Wed, 25 Jan 2023 20:38:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 08/36] include/qemu/int128: Use Int128 structure for TCI Date: Wed, 25 Jan 2023 18:37:56 -1000 Message-Id: <20230126043824.54819-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708226046100005 We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure. In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this. We cannot modify Int128 itself, as any changed alignment would also break libffi. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/qemu/atomic128.h | 29 +++++++++++++++++++++------ include/qemu/int128.h | 25 +++++++++++++++++++++--- util/int128.c | 42 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 9 deletions(-) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index adb9a1a260..d0ba0b9c65 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -44,13 +44,23 @@ #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return qatomic_cmpxchg__nocheck(ptr, cmp, new); + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(CONFIG_CMPXCHG128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return __sync_val_compare_and_swap_16(ptr, cmp, new); + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(__aarch64__) @@ -89,12 +99,18 @@ Int128 QEMU_ERROR("unsupported atomic") #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_read(Int128 *ptr) { - return qatomic_read__nocheck(ptr); + Int128Alias r; + + r.i =3D qatomic_read__nocheck((__int128_t *)ptr); + return r.s; } =20 static inline void atomic16_set(Int128 *ptr, Int128 val) { - qatomic_set__nocheck(ptr, val); + Int128Alias v; + + v.s =3D val; + qatomic_set__nocheck((__int128_t *)ptr, v.i); } =20 # define HAVE_ATOMIC128 1 @@ -132,7 +148,8 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) static inline Int128 atomic16_read(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ - return atomic16_cmpxchg(ptr, 0, 0); + Int128 z =3D int128_make64(0); + return atomic16_cmpxchg(ptr, z, z); } =20 static inline void atomic16_set(Int128 *ptr, Int128 val) @@ -141,7 +158,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) do { cmp =3D old; old =3D atomic16_cmpxchg(ptr, cmp, val); - } while (old !=3D cmp); + } while (int128_ne(old, cmp)); } =20 # define HAVE_ATOMIC128 1 diff --git a/include/qemu/int128.h b/include/qemu/int128.h index d2b76ca6ac..f62a46b48c 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -3,7 +3,12 @@ =20 #include "qemu/bswap.h" =20 -#ifdef CONFIG_INT128 +/* + * With TCI, we need to use libffi for interfacing with TCG helpers. + * But libffi does not support __int128_t, and therefore cannot pass + * or return values of this type, force use of the Int128 struct. + */ +#if defined(CONFIG_INT128) && !defined(CONFIG_TCG_INTERPRETER) typedef __int128_t Int128; =20 static inline Int128 int128_make64(uint64_t a) @@ -460,8 +465,7 @@ Int128 int128_divu(Int128, Int128); Int128 int128_remu(Int128, Int128); Int128 int128_divs(Int128, Int128); Int128 int128_rems(Int128, Int128); - -#endif /* CONFIG_INT128 */ +#endif /* CONFIG_INT128 && !CONFIG_TCG_INTERPRETER */ =20 static inline void bswap128s(Int128 *s) { @@ -472,4 +476,19 @@ static inline void bswap128s(Int128 *s) #define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX) #define INT128_MIN int128_make128(0, INT64_MIN) =20 +/* + * When compiler supports a 128-bit type, define a combination of + * a possible structure and the native types. Ease parameter passing + * via use of the transparent union extension. + */ +#ifdef CONFIG_INT128 +typedef union { + Int128 s; + __int128_t i; + __uint128_t u; +} Int128Alias __attribute__((transparent_union)); +#else +typedef Int128 Int128Alias; +#endif /* CONFIG_INT128 */ + #endif /* INT128_H */ diff --git a/util/int128.c b/util/int128.c index ed8f25fef1..df6c6331bd 100644 --- a/util/int128.c +++ b/util/int128.c @@ -144,4 +144,46 @@ Int128 int128_rems(Int128 a, Int128 b) return r; } =20 +#elif defined(CONFIG_TCG_INTERPRETER) + +Int128 int128_divu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.u =3D a.u / b.u; + return r.s; +} + +Int128 int128_remu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.u =3D a.u % b.u; + return r.s; +} + +Int128 int128_divs(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.i =3D a.i / b.i; + return r.s; +} + +Int128 int128_rems(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.i =3D a.i % b.i; + return r.s; +} + #endif --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674707960; cv=none; d=zohomail.com; s=zohoarc; b=Uj9vVndga6V04tcin2wrMyz1Elea+3E3+w2z09whMgOWuwkAJwXLRSU7RbM6MTIn1s7aNMPe4rWkVe1/4/h4xWk7JTXAkT74vszDsRBgQqoO+uiyhY4RJ8NQw2ajtrMmb/msKWJfodFnyuJM4IOViVVyfcywJMLAQXmE4qWpas0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674707960; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LFuKtqFYTzofUHvDSF4HQif+epQY9AXs3XWktrGzXD4=; b=nh9xGF2752clrGBG6XFG07WHAWrCraUnL7WE8Wf2FU3RbXuVTQGSeMfxSe4j5fmFYfo64AtYdorZyxJZZsjtxXRBG6siJkfI70MDWrFbSMtSumaHIxE51M4kBWMXfWAlt4HSHfGFkrJrzG2Ns75GqaRavE8pMAmDDGxw+fQMGKM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674707960143296.10753686998044; Wed, 25 Jan 2023 20:39:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu29-00009Z-TO; Wed, 25 Jan 2023 23:38:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu29-00009K-1M for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:45 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu27-0004RI-AL for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:44 -0500 Received: by mail-pl1-x634.google.com with SMTP id 5so927509plo.3 for ; Wed, 25 Jan 2023 20:38:42 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LFuKtqFYTzofUHvDSF4HQif+epQY9AXs3XWktrGzXD4=; b=dR63xNwcFesK6pPwGhQvOaGuUP9jxliTSlTtjvrQvZ0vaknRo9+ZygHvyltTDAeglq b5bAJ5/0Ab7g5G6qHYyGxUIAmUhBJjDqpB3ns3iN7zigPVFIDlrvGRQMlSTC4yUjVaij mwa7OzM9fzP7y8S6vDSeUmer0CPr0STqs4S10WrbAI46dryMKgNLxQHxFjikhTVDjwPI xKaeC6okneVOb/TUjVZ6rzm0vFVBEnSbkrCSLhUSjur2WhGH3fcDnazwQbnryPEeyAuV +EdUQLygqW/0EeiZKAGjzj9rPMJm8Rb07b8OxW88hIf26PZfpXk8HOgnIsI7yWqGLcW1 AI7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LFuKtqFYTzofUHvDSF4HQif+epQY9AXs3XWktrGzXD4=; b=M7fZW+JdJSSJ0hBXhQTH7iZKPuoL68+gBnG0K0vtymirGS7lV66AypBK4PyTnar6iA N0qmhRDGQ5e/msYaYystgBMDAgTQ8HrBV8K47Z1GSzqRVVOVnSRUSJqbaUfUiTErUvwV HBSgMATNk4pjhnirwbAMzXZuB5DTcseep9Dc9UROTL3R5xlOjIpGpG0AXSIPnWYUv+hS Xu/xVBFZpJ3dVqiNKWb0LYREH17auFJNilrOjApd0C6oxXwG4f4VjkbcczeG42Obwkhn VvlmK/YYAJl2vMC/F6fOrMcQJLu8cSe8t/KSDPNjo31OuJiZx50gSbQzCpNGwQV9d5yY wlgA== X-Gm-Message-State: AO0yUKVXxzLsD4M1bTS901X+p3eF7MuefD/t96BDxbFF6K2i4naPnCIB gdTzqVyyp4l0I+Rf0Y9cUOXoP7OoN6ZoZ58xZj4= X-Google-Smtp-Source: AK7set9SoMjEzLJoBTQrw4KFvtM4BpYjurRBfGWsyCD7zQfJS/7KJqKITe48J9GOnX4Gq0NpYbsrdQ== X-Received: by 2002:a17:90a:1d7:b0:22b:b0cb:2925 with SMTP id 23-20020a17090a01d700b0022bb0cb2925mr765392pjd.30.1674707921748; Wed, 25 Jan 2023 20:38:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 09/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Wed, 25 Jan 2023 18:37:57 -1000 Message-Id: <20230126043824.54819-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674707961326100004 Content-Type: text/plain; charset="utf-8" Fill in the parameters for the host ABI for Int128. Adjust tcg_target_call_oarg_reg for _WIN64, and tcg_out_call for i386 sysv. Allow TCG_TYPE_V128 stores without AVX enabled. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.h | 10 ++++++++++ tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 5797a55ea0..d4f2a6f8c2 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -100,6 +100,16 @@ typedef enum { #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#if defined(_WIN64) +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC +#elif TCG_TARGET_REG_BITS =3D=3D 64 +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL +#else +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF +#endif =20 extern bool have_bmi1; extern bool have_popcnt; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 2f0a9521bf..883ced8168 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -115,6 +115,11 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) case TCG_CALL_RET_NORMAL: tcg_debug_assert(slot >=3D 0 && slot <=3D 1); return slot ? TCG_REG_EDX : TCG_REG_EAX; +#ifdef _WIN64 + case TCG_CALL_RET_BY_VEC: + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_XMM0; +#endif default: g_assert_not_reached(); } @@ -1188,9 +1193,16 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, * The gvec infrastructure is asserts that v128 vector loads * and stores use a 16-byte aligned offset. Validate that the * final pointer is aligned by using an insn that will SIGSEGV. + * + * This specific instance is also used by TCG_CALL_RET_BY_VEC, + * for _WIN64, which must have SSE2 but may not have AVX. */ tcg_debug_assert(arg >=3D 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + if (have_avx1) { + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg= 2); + } else { + tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); + } break; case TCG_TYPE_V256: /* @@ -1677,6 +1689,22 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *dest, const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); + +#ifndef _WIN32 + if (TCG_TARGET_REG_BITS =3D=3D 32 && info->out_kind =3D=3D TCG_CALL_RE= T_BY_REF) { + /* + * The sysv i386 abi for struct return places a reference as the + * first argument of the stack, and pops that argument with the + * return statement. Since we want to retain the aligned stack + * pointer for the callee, we do not want to actually push that + * argument before the call but rely on the normal store to the + * stack slot. But we do need to compensate for the pop in order + * to reset our correct stack pointer value. + * Pushing a garbage value back onto the stack is quickest. + */ + tcg_out_push(s, TCG_REG_EAX); + } +#endif } =20 static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674707993; cv=none; d=zohomail.com; s=zohoarc; b=n9Ymz8mSOqNqB+m0w4RcMDPvlR2j+a8XVIiELDf951vBveqZHzaP3sy+LpRcvEaizgGR4Aw/kOLbaEzH2Fzj7f+maq9gbCeXgxQP1Zz6fPNwCX92zhTRm1dxQ6ovOGUcFwnSAZirnp8wqUfwKobNwjsLkTqB2THjvu+2Ru3hl0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674707993; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DFQ2aG+VnTqrFSc5ewVcTvqiqhyOxzsEeJCA6dzv8VM=; b=T6FRk1H9a2btxKAjoutnjQncDDdkL+XTtzhYLoxIB7gXWJvwLLpr9VXolJxeEMqSyUmMRJKdig1DWBg5eBQSRLkChnIxylIG218rb7rgsYAsD9hgNhvW/hRdulsT7RZn3GZ9L8GEf6P8MXFPHyzeR9HKk4Euoo34BuFEHVbGtQw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674707993049517.6608794998218; Wed, 25 Jan 2023 20:39:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2B-0000Ak-Fk; Wed, 25 Jan 2023 23:38:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2A-00009c-Ae for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:46 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu28-0004Rg-Pb for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:46 -0500 Received: by mail-pj1-x1035.google.com with SMTP id z1-20020a17090a66c100b00226f05b9595so756540pjl.0 for ; Wed, 25 Jan 2023 20:38:44 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DFQ2aG+VnTqrFSc5ewVcTvqiqhyOxzsEeJCA6dzv8VM=; b=BkLKeQO0oYsSeC6knVpG1IG77MXOVvALgjfEkIQFFp/0mDGmx8HqiB9Se6GohpkjXA DzIyqRz6en1gnhqWOEOouXieCd9ALUPtd4aQlfQ85kC2Gh418DWoGvmwEHiY3/2cvd0v zFQ2SICXNUNRbM8FGj08SQg0dYbiFyE4mn44M92Ctb6xLCYCR1OoFv2M039kShWZ8iuB lk8l4s70P3fHk4Xgq2GuGWlfKHJrYWJuyQWZW81gYyXDVphRy7d8ZaR9jekS17I1EG3Q N4/LQH6gVh7/iYc7erWBm+znxyae6dcxG1bjYI6ca8YxzoUlo21ONS6nXcbLf7n9BTqs nbDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DFQ2aG+VnTqrFSc5ewVcTvqiqhyOxzsEeJCA6dzv8VM=; b=fBps2MjuQCQpbbXQiVtI7CWPkAMCAnqYGB2q9WcxeEo62YoSfx/qvS0bokIQI2Iwqc ZBu/qhirnWYnoulJ70c6c7XkSWdVWMV6BTNXYmUsSdJGIw1H0YKwerpOyvCrPQ8B327R vKLmJtp4PzAe+K2EEahoUUI2ndPnfDmyTWvioZ7SncioXWieNJ0jSnJ2nUGyiS29Rqnh jhGUGJRFnQyLVKIQFPfjUlH14CrnYwG8ARylyXb4FoXIweCPkGNdy94H0Tg9zRWFKTvr 8nHP4c7tnEXbjR8Dz+wnp/ou/+SzX5uI1v7q7DTI0GOGHVf2Rt+8I95PUBVpbCPUy7D0 M7Kg== X-Gm-Message-State: AO0yUKW1x0uEAEnIcg7sEsn8bsIe/Y7wfWRBcbrjwpX2GaQDS2zuSp4I V1GgRS+gg+3l+D9oDabXCB6tdmtneSYnRH1zdLk= X-Google-Smtp-Source: AK7set8OuS8+sHHSkyT7Z6L2ofs5AUMIFKdKRdU4ULacmN5xTY7EfQ3q0I+A+tRftcsqrtEnXL6FGw== X-Received: by 2002:a17:90b:1d91:b0:22b:ed4a:c46e with SMTP id pf17-20020a17090b1d9100b0022bed4ac46emr8942662pjb.30.1674707923426; Wed, 25 Jan 2023 20:38:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 10/36] tcg/tci: Fix big-endian return register ordering Date: Wed, 25 Jan 2023 18:37:58 -1000 Message-Id: <20230126043824.54819-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674707995130100001 We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 05a24163d3..eeccdde8bc 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, ffi_call(pptr[1], pptr[0], stack, call_slots); } =20 - /* Any result winds up "left-aligned" in the stack[0] slot. */ switch (len) { case 0: /* void */ break; case 1: /* uint32_t */ /* + * The result winds up "left-aligned" in the stack[0] slot. * Note that libffi has an odd special case in that it will * always widen an integral result to ffi_arg. */ - if (sizeof(ffi_arg) =3D=3D 4) { - regs[TCG_REG_R0] =3D *(uint32_t *)stack; - break; - } - /* fall through */ - case 2: /* uint64_t */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]= ); + if (sizeof(ffi_arg) =3D=3D 8) { + regs[TCG_REG_R0] =3D (uint32_t)stack[0]; } else { - regs[TCG_REG_R0] =3D stack[0]; + regs[TCG_REG_R0] =3D *(uint32_t *)stack; } break; + case 2: /* uint64_t */ + /* + * For TCG_TARGET_REG_BITS =3D=3D 32, the register pair + * must stay in host memory order. + */ + memcpy(®s[TCG_REG_R0], stack, 8); + break; default: g_assert_not_reached(); } --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708042; cv=none; d=zohomail.com; s=zohoarc; b=JZjWM7HMV46hS1Fy5rhx8bz/7+TWtlCO0KipBkggHEX6gGLxKux+RCLTkPSU4uDCClTOI7pOTt69Y6+9scQ2Xc8cgh8oKLamie3fwBbJVoM3qlgB591ccgI1VnbpBfQE/oKV+LQqEch21FF4vCRi0HGsv86jDR5bwCliQYyVFWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708042; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DFOekAAzxdgjwf5mHc+QvA7R7XGIkeJ4+D5yBekuh2Q=; b=cVJ5O0hzhlfnnsdhLgsfIs4AfOYwUeGBRhBAZruD7xN+2zhXkt1+lDrzbknDs2c047I3sSSf+NrDezMQUDal9AmHdr1aMOYzIpV06UvBoYbDWFN/PSJYMJrCAmCZt3O4lvWaH73t15eGyNFwFD0aAFqUGwqw9bGEMf+G++9IX04= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708042558620.415893117418; Wed, 25 Jan 2023 20:40:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2G-0000Be-IT; Wed, 25 Jan 2023 23:38:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2C-0000BE-9j for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:51 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2A-0004Rx-EZ for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:48 -0500 Received: by mail-pj1-x102c.google.com with SMTP id n20-20020a17090aab9400b00229ca6a4636so4274649pjq.0 for ; Wed, 25 Jan 2023 20:38:46 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DFOekAAzxdgjwf5mHc+QvA7R7XGIkeJ4+D5yBekuh2Q=; b=Q8/SycvwQoTUS549Sb1Jg6vHMRiWm/Ypy35ZaHvk1B01HtWE+dKufpOkz+rIY0vyTZ hmb7wr8a+bids01YVHgPja+zVB1TONTIVjqAAlLlcUKfQ2r770bwVaDsnUPzejZZbebA Fb+YaikiJZ47M1iokyrG6kRyfjmP5s8TmGp5Z2rE4kC2LghGH+5H6SAk9oycAllrrdad ocTNydtEGpWA3gfDV2rjrm67MioEYtwFEoAKQqT9VxdtKTd7Nwnqmty+bbIMpRC6PQZG 8AWzAK1dndvQ+l2P0uWWOU6gdmef3yBf6dFGNfC7BNXUeQZdXOx3Nh+oZFj9M9AnniLa Hk+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DFOekAAzxdgjwf5mHc+QvA7R7XGIkeJ4+D5yBekuh2Q=; b=IfZW0M+Rsn7Vyp6vtNRjVzCfqoZCgW1+vq5a5KxtqzgU/Z9kpHL2j7TznkUNQ8sZez XjHtbzMukqWcCNn/TP3nREGm529a6UEhDcoFGLmKJNblHVbZUTp5Alh3Ppp2A7Eh0GZo OIlgpU2BNVX4MSa5vPfuALFX4REhYhntSeKHoCj7uB5qFUefRUQ/spI7lOt+m03ppQdL HUxJaOkLxREVzKeBuGN4IuHfHlbAZgsj4XoRqupPFvLlhuczcYnZemhh+v18caxt4I9Z QM1eZpPkb2+GwFfG8VK9d8IUM+MH1K1ml86PRIwozpPfyZFQCnnT6IkrHstam2MKKtS6 eHyA== X-Gm-Message-State: AFqh2koc1IKa7cwN7z3FNMcUkUeN+XvN3DlLqTdlcyzB9VUpYUKhLtdJ VRUiiiQoeg4VrUIX5wNNTB0AO60sY84w1LoQ1bE= X-Google-Smtp-Source: AMrXdXvRSXRaJNL3/j69xqi4HpSfrdpAszj2mbrEN7TH6seoDUBYQw706IzttJ0WhePS5jJlL23Xdw== X-Received: by 2002:a17:90b:1d0c:b0:22b:b76b:5047 with SMTP id on12-20020a17090b1d0c00b0022bb76b5047mr22525503pjb.8.1674707924983; Wed, 25 Jan 2023 20:38:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Wed, 25 Jan 2023 18:37:59 -1000 Message-Id: <20230126043824.54819-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708043426100003 Content-Type: text/plain; charset="utf-8" Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now, but only fill in slots required for the call we're about to make. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci/tcg-target.h | 3 +++ tcg/tcg.c | 19 +++++++++++++++++ tcg/tci.c | 44 ++++++++++++++++++++-------------------- tcg/tci/tcg-target.c.inc | 10 ++++----- 4 files changed, 49 insertions(+), 27 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1414ab4d5b..7140a76a73 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -160,10 +160,13 @@ typedef enum { #if TCG_TARGET_REG_BITS =3D=3D 32 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index 084e3c3a54..4c43fd28ba 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -570,6 +570,22 @@ static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { + /* + * libffi does not support __int128_t, so we have forced Int128 + * to use the structure definition instead of the builtin type. + */ + static ffi_type *ffi_type_i128_elements[3] =3D { + &ffi_type_uint64, + &ffi_type_uint64, + NULL + }; + static ffi_type ffi_type_i128 =3D { + .size =3D 16, + .alignment =3D __alignof__(Int128), + .type =3D FFI_TYPE_STRUCT, + .elements =3D ffi_type_i128_elements, + }; + switch (argmask) { case dh_typecode_void: return &ffi_type_void; @@ -583,6 +599,8 @@ static ffi_type *typecode_to_ffi(int argmask) return &ffi_type_sint64; case dh_typecode_ptr: return &ffi_type_pointer; + case dh_typecode_i128: + return &ffi_type_i128; } g_assert_not_reached(); } @@ -613,6 +631,7 @@ static void init_ffi_layouts(void) /* Ignoring the return type, find the last non-zero field. */ nargs =3D 32 - clz32(typemask >> 3); nargs =3D DIV_ROUND_UP(nargs, 3); + assert(nargs <=3D MAX_CALL_IARGS); =20 ca =3D g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); ca->cif.rtype =3D typecode_to_ffi(typemask & 7); diff --git a/tcg/tci.c b/tcg/tci.c index eeccdde8bc..022fe9d0f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -470,12 +470,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; - void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; - /* Other call_slots entries initialized at first use (see below). */ - call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -498,26 +495,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - /* - * Set up the ffi_avalue array once, delayed until now - * because many TB's do not make any calls. In tcg_gen_callN, - * we arranged for every real argument to be "left-aligned" - * in each 64-bit slot. - */ - if (unlikely(call_slots[0] =3D=3D NULL)) { - for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { - call_slots[i] =3D &stack[i]; - } - } - - tci_args_nl(insn, tb_ptr, &len, &ptr); - - /* Helper functions may need to access the "return address" */ - tci_tb_ptr =3D (uintptr_t)tb_ptr; - { - void **pptr =3D ptr; - ffi_call(pptr[1], pptr[0], stack, call_slots); + void *call_slots[MAX_CALL_IARGS]; + ffi_cif *cif; + void *func; + unsigned i, s, n; + + tci_args_nl(insn, tb_ptr, &len, &ptr); + func =3D ((void **)ptr)[0]; + cif =3D ((void **)ptr)[1]; + + n =3D cif->nargs; + for (i =3D s =3D 0; i < n; ++i) { + ffi_type *t =3D cif->arg_types[i]; + call_slots[i] =3D &stack[s]; + s +=3D DIV_ROUND_UP(t->size, 8); + } + + /* Helper functions may need to access the "return address= " */ + tci_tb_ptr =3D (uintptr_t)tb_ptr; + ffi_call(cif, func, stack, call_slots); } =20 switch (len) { @@ -542,6 +539,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, */ memcpy(®s[TCG_REG_R0], stack, 8); break; + case 3: /* Int128 */ + memcpy(®s[TCG_REG_R0], stack, 16); + break; default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e3b0ff303f..c1d34d7bd1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -203,7 +203,7 @@ static const int tcg_target_call_iarg_regs[] =3D { }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); - tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); return TCG_REG_R0 + slot; } =20 @@ -573,11 +573,11 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *func, =20 if (cif->rtype =3D=3D &ffi_type_void) { which =3D 0; - } else if (cif->rtype->size =3D=3D 4) { - which =3D 1; } else { - tcg_debug_assert(cif->rtype->size =3D=3D 8); - which =3D 2; + tcg_debug_assert(cif->rtype->size =3D=3D 4 || + cif->rtype->size =3D=3D 8 || + cif->rtype->size =3D=3D 16); + which =3D ctz32(cif->rtype->size) - 1; } new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); insn =3D deposit32(insn, 0, 8, INDEX_op_call); --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708145; cv=none; d=zohomail.com; s=zohoarc; b=RzkrwYFqAGJ/A9AWr+k0DLO/JZviEQrnl22PVdNivyE1fzCWVvQZxVR53llwmehcD3vlrCP3nXtUmiGTRoq3hf3Fq2PmKGSSfdum/9Tpn+0fGJVwVYrXjOY780juFLDYbjOoQB+jds97Reod0DQT+mnB1nCmVP2lfbCUaQHVG6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708145; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wWb3S++T7GtjtUr7GRa/UKq+hniTgyl5bXR6FF9nkXs=; b=AiChNqYPI/kTX9LtCZ86qlJ+vPKnVotCnoutdZovQLyrBeCD5SWTvULHwEJVvVV5dWTF9W8lxGnDk86mF8yMmvqO9obIYtE3hqFYiica28KL2h1uXuOTrfUsN5nckfR90QQaOfHdv4bvkG8js7NMjOT/vlNmdxdRiFM7mxQKSUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708145104155.27004188565343; Wed, 25 Jan 2023 20:42:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2H-0000Bl-63; Wed, 25 Jan 2023 23:38:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2F-0000BS-Le for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:51 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2B-0004S7-Qm for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:49 -0500 Received: by mail-pl1-x631.google.com with SMTP id jm10so879072plb.13 for ; Wed, 25 Jan 2023 20:38:47 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wWb3S++T7GtjtUr7GRa/UKq+hniTgyl5bXR6FF9nkXs=; b=N7eGJIn4OhJwlqOWOAoy1yfOoGhAefKPlhnU6QYNYnbXXdGHqLdBRcO26fQMl8NAoX K81QKPvTMJ5yZQ5sPChEYCAvpxJzDrga8Hs+VR2wgPDUS6CFSKfr38ZKFy6c6mCqqzdJ wFkuxoanfpHnwQf9Fh9YB6Q8tw41Y3E0m5YgwHvHkgr1d+sNJdx+2vNfRhBS+ZOyjFzc EqgjkmdWNTgvaU5uhHX7CX/DDvM57lV7ZjM9uVwAyBTcUa5reVi0/I2iuLEGFrA0mDnz z0qqt8XgA2DIHyCkm6tuaCQVnS8s6ibCQz/xmnb8NlfO9OP2YlirWAvAD92VFPFSBUKn GCRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wWb3S++T7GtjtUr7GRa/UKq+hniTgyl5bXR6FF9nkXs=; b=x/b0ooV2FpotyYwxhvc3ICBqfzjlFA2rCktXG9m9eUl3cbXtLDlAsmzJUII/oIYvdR +XSPnVaIKErb9rCirejNX2k8mttvmOntMDQ8PtWS4fTFK7g3xCi+4u+jQOmPFQuouIlC /MWBBD6sIJMeRAYVkgY278ICvR9U11VCYHkbXBkpCdwRxwnBZV/PqMd4dLTHAvrXiZ87 4j/ek9qXNHwVEqEqKGhsm+YWQRBmYMz/wJqymemVGBxY0VAIRpIyJKP2mOptMePU0T2f SxXSFmegWI91JfhfpPegsB5N06AKrcouUtw0Fg46jSzsBUu9g6FoTAnUZh5c2P1VdtcK otkQ== X-Gm-Message-State: AFqh2kp9LpPBqlgjiTZ6ibA6YpQWbhOAk0BI0/V5VMxXk2UY09JNiNcM gY77aOg3DChXhBFOrYoagaMN7hf2cMCyKpAn80M= X-Google-Smtp-Source: AMrXdXseAia2nV/aReNfq4ccv8iwJP1IpL3SW7ykJ+xJ/4i7W5lg3COVKUW7REZvg3sS2hPiKDCioA== X-Received: by 2002:a05:6a20:b913:b0:b8:843f:e753 with SMTP id fe19-20020a056a20b91300b000b8843fe753mr33733352pzb.29.1674707926481; Wed, 25 Jan 2023 20:38:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Daniel Henrique Barboza Subject: [PATCH v5 12/36] tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Wed, 25 Jan 2023 18:38:00 -1000 Message-Id: <20230126043824.54819-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708145779100001 Content-Type: text/plain; charset="utf-8" Fill in the parameters for the host ABI for Int128 for those backends which require no extra modification. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 3 +++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tcg.c | 6 +++--- tcg/ppc/tcg-target.c.inc | 3 +++ 9 files changed, 21 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 8d244292aa..c0b0f614ba 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -54,6 +54,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 91b8954804..def2a189e6 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -91,6 +91,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 8b151e7f6f..17b8193aa5 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -92,6 +92,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 7bc8e15293..68b11e4d48 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,6 +89,8 @@ typedef enum { # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >=3D 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 1337bc1f1e..0deb33701f 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -85,9 +85,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS =3D=3D 32 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e597e47e60..a05b473117 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -169,6 +169,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 1d6a5c8b07..ffe22b1d21 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -73,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #if defined(__VIS__) && __VIS__ >=3D 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 4c43fd28ba..63e0753ded 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -765,8 +765,8 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; - info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ - switch (/* TODO */ TCG_CALL_RET_NORMAL) { + info->out_kind =3D TCG_TARGET_CALL_RET_I128; + switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); @@ -854,7 +854,7 @@ static void init_call_layout(TCGHelperInfo *info) break; =20 case TCG_TYPE_I128: - switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + switch (TCG_TARGET_CALL_ARG_I128) { case TCG_CALL_ARG_EVEN: layout_arg_even(&cum); /* fall through */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index f3fec14118..afadf9a1e3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -54,6 +54,9 @@ #else # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +/* Note sysv arg alignment applies only to 2-word types, not more. */ +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* For some memory operations, we need a scratch that isn't R0. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8/QoQU32OqScdUVawZ5i59sewqeYKfxZ8LNCjfWnBgc=; b=mgp5xI3BSl2Rp8QIa3tx8evvFgQTmhC+u2P4z2gfMDD6EtOdYjKB7dDYmnyfBMGyIB LSwH+7xJiWpwuxgVNCp27YYGkooEdYkgbjDMkUmaGoo1zwESHHhs4Bq33PH8l4s4uZMU wb3j3Y9qg0TZtwN8jmTCgwykrVgkqMKvsBklgzX0//ABxG8YTHnws6alawCUzNQbtVTv kyDmhEXfRXRg1ssd7Kg3BnQBwt7rThYSUvge5hTAyFMLGQNah6oqwdlkl9372WOxfa8h s/xI1j1vkl4dCXlQjR5QK+lYh9UewtU9fY7B6PU3rVSVMLEAB61EZTgoyforaU9HdAEB LAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8/QoQU32OqScdUVawZ5i59sewqeYKfxZ8LNCjfWnBgc=; b=pBNM0QnR8CW9OeJO0JhwuS/lSIuLbTmGpJ13W8TjCEwpGfV++6/aP6Hh0kWHdf4Ubv vzqCfARSPbiEnpTvOIHJwX35ZVKZI6TKo5/lz8kQibu5CFJ78c03qI4X22X6ubrEJimc zA/2n7cGNzWM4as5QJs7V4xRUYL/8gikCzcmg61+GUkVVYFj+HIcp6B8LeWD8y762Gnb CTIj9VLpYQYx/x7whe9mnJAAovx8gjZZBXK2RVIrnylw20Icj7g2nWzLwULY/EUfZUbX dVDnNhef8WglRr12pBOdI3J3YHqvz/zOj7aZ/U8hTrf0ZfDwboytN3zr+CsPy8nuTg9m IBZA== X-Gm-Message-State: AFqh2krqCZt7B8X2ZUBxNI6LPm81WqqVbrDs+wvr0P1HqJmAsEaUtJdZ XRrqo1xwr3KiG775CbqH+fIT7mZlWzb/l24gAqw= X-Google-Smtp-Source: AMrXdXtvZzQG5hmlwu7mBjzasLD7o9xNaXvna/Xr1ouhBC9iuDDBug/qfCAkKF6/2AWgEzUnEdsI4g== X-Received: by 2002:a17:90b:1d03:b0:22a:3d:4c22 with SMTP id on3-20020a17090b1d0300b0022a003d4c22mr24481720pjb.13.1674707928084; Wed, 25 Jan 2023 20:38:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 13/36] tcg: Add temp allocation for TCGv_i128 Date: Wed, 25 Jan 2023 18:38:01 -1000 Message-Id: <20230126043824.54819-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674707961317100001 This enables allocation of i128. The type is not yet usable, as we have not yet added data movement ops. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 32 +++++++++++++++++++++++++ tcg/tcg.c | 60 +++++++++++++++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 18 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 8b7e61e7a5..7a8e4bbdd7 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -685,6 +685,11 @@ static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) return tcgv_i32_temp((TCGv_i32)v); } =20 +static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) +{ + return tcgv_i32_temp((TCGv_i32)v); +} + static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { return tcgv_i32_temp((TCGv_i32)v); @@ -705,6 +710,11 @@ static inline TCGArg tcgv_i64_arg(TCGv_i64 v) return temp_arg(tcgv_i64_temp(v)); } =20 +static inline TCGArg tcgv_i128_arg(TCGv_i128 v) +{ + return temp_arg(tcgv_i128_temp(v)); +} + static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); @@ -726,6 +736,11 @@ static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) return (TCGv_i64)temp_tcgv_i32(t); } =20 +static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) +{ + return (TCGv_i128)temp_tcgv_i32(t); +} + static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { return (TCGv_ptr)temp_tcgv_i32(t); @@ -851,6 +866,11 @@ static inline void tcg_temp_free_i64(TCGv_i64 arg) tcg_temp_free_internal(tcgv_i64_temp(arg)); } =20 +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + static inline void tcg_temp_free_ptr(TCGv_ptr arg) { tcg_temp_free_internal(tcgv_ptr_temp(arg)); @@ -899,6 +919,18 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return temp_tcgv_i64(t); } =20 +static inline TCGv_i128 tcg_temp_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, false); + return temp_tcgv_i128(t); +} + +static inline TCGv_i128 tcg_temp_local_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, true); + return temp_tcgv_i128(t); +} + static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offse= t, const char *name) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 63e0753ded..d449bb0864 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1273,26 +1273,45 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool t= emp_local) tcg_debug_assert(ts->base_type =3D=3D type); tcg_debug_assert(ts->kind =3D=3D kind); } else { + int i, n; + + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + n =3D 1; + break; + case TCG_TYPE_I64: + n =3D 64 / TCG_TARGET_REG_BITS; + break; + case TCG_TYPE_I128: + n =3D 128 / TCG_TARGET_REG_BITS; + break; + default: + g_assert_not_reached(); + } + ts =3D tcg_temp_alloc(s); - if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D TCG_TYPE_I64) { - TCGTemp *ts2 =3D tcg_temp_alloc(s); + ts->base_type =3D type; + ts->temp_allocated =3D 1; + ts->kind =3D kind; =20 - ts->base_type =3D type; - ts->type =3D TCG_TYPE_I32; - ts->temp_allocated =3D 1; - ts->kind =3D kind; - - tcg_debug_assert(ts2 =3D=3D ts + 1); - ts2->base_type =3D TCG_TYPE_I64; - ts2->type =3D TCG_TYPE_I32; - ts2->temp_allocated =3D 1; - ts2->temp_subindex =3D 1; - ts2->kind =3D kind; - } else { - ts->base_type =3D type; + if (n =3D=3D 1) { ts->type =3D type; - ts->temp_allocated =3D 1; - ts->kind =3D kind; + } else { + ts->type =3D TCG_TYPE_REG; + + for (i =3D 1; i < n; ++i) { + TCGTemp *ts2 =3D tcg_temp_alloc(s); + + tcg_debug_assert(ts2 =3D=3D ts + i); + ts2->base_type =3D type; + ts2->type =3D TCG_TYPE_REG; + ts2->temp_allocated =3D 1; + ts2->temp_subindex =3D i; + ts2->kind =3D kind; + } } } =20 @@ -3381,9 +3400,14 @@ static void temp_allocate_frame(TCGContext *s, TCGTe= mp *ts) case TCG_TYPE_V64: align =3D 8; break; + case TCG_TYPE_I128: case TCG_TYPE_V128: case TCG_TYPE_V256: - /* Note that we do not require aligned storage for V256. */ + /* + * Note that we do not require aligned storage for V256, + * and that we provide alignment for I128 to match V128, + * even if that's above what the host ABI requires. + */ align =3D 16; break; default: --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UP8+uewyy5/Dp5hv7KFYTuYDZZ769Cjknfcg/UBdlzw=; b=mO8vhEYMEmZle3X/TKK4InC7EJZLvWKjj89gV1BbF8uXwK80CaKQRmwu9dxiwu15oh fdPBfbhHW68jZTskcY+tTNQoXyQgPzO7VrzBh2b+mym9wgU7u2W+wJ4yNhhoj1yjNCdD UKickLuayHfsaV5VAV7xuJlvSg/HYIaX0gD6sCXErgW6H406puDVZL41fmFJzXrBOoFu h6iFWrUyX/XJMEQZUnrrT1UFKF9Sb68hriPGjqjjwYyXyGjV1FO3QMMKySUxrgLgXIKh P5A0GEviPKTfd3MGvCBuWcGF7uiDdLyBH/wX63QhQY7f751/3B+fbFcTh6DlEehCZinw vj1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UP8+uewyy5/Dp5hv7KFYTuYDZZ769Cjknfcg/UBdlzw=; b=wD1yCAG0DTbXrBsMLrG9YqPnOneDz1+o+W2BH+Kp7U48OdQ3SRms6TzkIIkBKuJMLz MivZbhd+vxSmFVm5BRhrU/yH6VG1V+6ytleMoUEzvyjZcA1jtWljpNJ837E+DMsPWi9o 0kobaeixvwtphbFWh4ALfLxMzxnzIbJ1TkzyH1L5ovkF/4t4EwGol6cYuQ26jD5VX/RD xtn4Y+vXGQjz/3IsS3dst40uZeo9xBcs+RMB2X0PQrYItwByHj0C+gH6DX1objFRXJDn bzoPVyNb1d1FlQVNb4y3LX072eGS2Q2JA9GpyXz4GZAeeaGkNe4myCddlHOlGm57CL78 MI8g== X-Gm-Message-State: AO0yUKUOLcE5kGL6cSIkUUbCq+rcZi5GkjjCFuxj3VCFXbsl/+ANt28e qt8svz5/0kUFcf1fDl5xTFIIMPGHT58BfCT9weE= X-Google-Smtp-Source: AK7set9UDxqDNupUux6nSFD2GlzVPFHarOGyxl4MgblgUAFlf50mKIZCCDHvrmWunFf1EuEadjjx+Q== X-Received: by 2002:a17:90a:31a:b0:22b:b681:2bb3 with SMTP id 26-20020a17090a031a00b0022bb6812bb3mr761275pje.38.1674707929524; Wed, 25 Jan 2023 20:38:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 14/36] tcg: Add basic data movement for TCGv_i128 Date: Wed, 25 Jan 2023 18:38:02 -1000 Message-Id: <20230126043824.54819-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708221998100001 Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg-op.h | 4 ++++ tcg/tcg-internal.h | 13 +++++++++++++ tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 79b1cf786f..c4276767d1 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -712,6 +712,10 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); =20 +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i6= 4 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 33f1d8b411..e542a4e9b7 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -117,4 +117,17 @@ extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit = code path is reachable"); extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reacha= ble"); #endif =20 +static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) +{ + /* For 32-bit, offset by 2, which may then have TCGV_{LOW,HIGH} applie= d. */ + int o =3D HOST_BIG_ENDIAN ? 64 / TCG_TARGET_REG_BITS : 0; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + +static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) +{ + int o =3D HOST_BIG_ENDIAN ? 0 : 64 / TCG_TARGET_REG_BITS; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 326a9180ef..cb83d2375d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2747,6 +2747,26 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TC= Gv_i64 arg) tcg_gen_shri_i64(hi, arg, 32); } =20 +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg) +{ + tcg_gen_mov_i64(lo, TCGV128_LOW(arg)); + tcg_gen_mov_i64(hi, TCGV128_HIGH(arg)); +} + +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi) +{ + tcg_gen_mov_i64(TCGV128_LOW(ret), lo); + tcg_gen_mov_i64(TCGV128_HIGH(ret), hi); +} + +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src) +{ + if (dst !=3D src) { + tcg_gen_mov_i64(TCGV128_LOW(dst), TCGV128_LOW(src)); + tcg_gen_mov_i64(TCGV128_HIGH(dst), TCGV128_HIGH(src)); + } +} + /* QEMU specific operations. */ =20 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708027; cv=none; d=zohomail.com; s=zohoarc; b=jjTVjGZ4eJXSjdUp/7WqC8N3B2CA8Dy5p339I+qviiLMKK6YDh06BhYptMLZ+NuDnVJxXcjfvE4WJG7CDaKPzzN+QNkIZXkxadwGMvXyrjqnC19QlDaZqGfX9Q4RJ6xEd7DYYYgja9aoqUbPKIL1i6UE03WdGOl/E27i4LzsJMo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708027; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kn2QKpGVCxbEOA7DjmMQr+70sBzJpA0LnU+n2IBTsJE=; b=k06h5hLVSulqTac8clolBOeqzpQM8ktinL1hPzfndYBoDRQ+28+uiUjQ8tX0Sj603GTRXsh6Q/3/LJtJrFV+ac8Fy9YK3aeptba08wzHeLvkygT8wLy4kCmexsj4beTFgXyPXvRhIgdroqy5LiwGwLA/dVKlzoykQFSixiFNew8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708027406171.50766250312859; Wed, 25 Jan 2023 20:40:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2K-0000Dr-3V; Wed, 25 Jan 2023 23:38:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2J-0000Cy-0G for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:55 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2G-0004ST-BR for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:54 -0500 Received: by mail-pl1-x633.google.com with SMTP id k18so917917pll.5 for ; Wed, 25 Jan 2023 20:38:51 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kn2QKpGVCxbEOA7DjmMQr+70sBzJpA0LnU+n2IBTsJE=; b=e5To2xVqHUYhiQQyTU4Yl3FHxQJhmpxap9C718hkus7XVLKoVdxGUOJrSRF3dAluqZ BMTJQmeRLXS8iDH848olZwCmj+DLZQxZQ3sRGlvhdk9CYouPvScMnSmDX9IrvrIwwD+I 18yEJenpFC2IcKOJn1a/1ELrdmfBjagYIycemYxDA7w+H0nn5fxqs4gWNfPAA9SUjuAV 1St4eZd+ftAKniEVbVFpwSL9DhYXo6W411GLNS0t6KtDOIzw+b5t8uNVMVRduP5gKC08 HgHQd5EkKocThTjmAlJd4HdVDkYp4rDIbeMe3XKlSl7X23Sw/+ipOmc23iRP87RxF9jC wpCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kn2QKpGVCxbEOA7DjmMQr+70sBzJpA0LnU+n2IBTsJE=; b=AbqyY8bJH6AyzWwH5yvJcEsLJlnusCGKHoy0qHjRXfOHnYVJ9WqKlUz6OA4CY3TTgO fF3+d2IyMq6tLwTydpgGzaz9wZ3CBzFoTCby0O/urkdk446h9NVrJXAg94hIv62RarlO yy4ioO3LT/9+4wAJuUB4t+nAqpmfSikMzDFzwIuy/yi/v6VVWRU/ablUuMzUtUvL21lu c+3tjfdxLDhtW7+Q7/g3Rlr90osm7he10DMUEDrQIXrD246N2qcQ1psPbbPmiWd3wNNd VESn5vDSEH2B+jeJzpS/DMd+d9WOtyMLZNHEelvdADMhs9v4/YoWa8tQ9liGjW0+ZJaC 4Xdw== X-Gm-Message-State: AFqh2kpbOOgRLJ49aa8m00m3fo09b9sWVRCDhnjtgvnSfOLHWoAbzElB qs18FDmfGsRzuBqAfe8rhbyD5qKTVPqR9IWcPq8= X-Google-Smtp-Source: AMrXdXvpkf46gvrlh3Yu6U6PDBLURvbMjH3NF+NJ51EfDDKdbI96PI9ZMZ5YWb6jES5V2+w68t+ymg== X-Received: by 2002:a17:90a:b383:b0:219:d98d:19d with SMTP id e3-20020a17090ab38300b00219d98d019dmr35335863pjr.32.1674707931012; Wed, 25 Jan 2023 20:38:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 15/36] tcg: Add guest load/store primitives for TCGv_i128 Date: Wed, 25 Jan 2023 18:38:03 -1000 Message-Id: <20230126043824.54819-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708029377100002 Content-Type: text/plain; charset="utf-8" These are not yet considering atomicity of the 16-byte value; this is a direct replacement for the current target code which uses a pair of 8-byte operations. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 10 +++ include/tcg/tcg-op.h | 2 + accel/tcg/cputlb.c | 112 +++++++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 66 ++++++++++++++++++++ tcg/tcg-op.c | 134 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 324 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d0c7c0d5fe..09b55cc0ee 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -220,6 +220,11 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra); =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); + void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, MemOpIdx oi, uintptr_t ra); void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, @@ -235,6 +240,11 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, ui= nt32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); + uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index c4276767d1..e5f5b63c37 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -845,6 +845,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); =20 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4e040a1cb9..e3604ad313 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2187,6 +2187,64 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr a= ddr, return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + h =3D helper_be_ldq_mmu(env, addr, new_oi, ra); + l =3D helper_be_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + l =3D helper_le_ldq_mmu(env, addr, new_oi, ra); + h =3D helper_le_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + /* * Store Helpers */ @@ -2541,6 +2599,60 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong = addr, uint64_t val, cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + helper_be_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + helper_le_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + #include "ldst_common.c.inc" =20 /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a8eb63ab96..ae67d84638 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1031,6 +1031,42 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr a= ddr, return ret; } =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_BE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (!HOST_BIG_ENDIAN) { + ret =3D bswap128(ret); + } + return ret; +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_LE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (HOST_BIG_ENDIAN) { + ret =3D bswap128(ret); + } + return ret; +} + void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, MemOpIdx oi, uintptr_t ra) { @@ -1115,6 +1151,36 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr,= uint64_t val, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_BE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (!HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_LE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) { uint32_t ret; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cb83d2375d..33ef325f6e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3109,6 +3109,140 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, T= CGArg idx, MemOp memop) } } =20 +static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) +{ + MemOp mop_1 =3D orig, mop_2; + + tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); + + /* Use a memory ordering implemented by the host. */ + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (orig & MO_BSWAP)) { + mop_1 &=3D ~MO_BSWAP; + } + + /* Reduce the size to 64-bit. */ + mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; + + /* Retain the alignment constraints of the original. */ + switch (orig & MO_AMASK) { + case MO_UNALN: + case MO_ALIGN_2: + case MO_ALIGN_4: + mop_2 =3D mop_1; + break; + case MO_ALIGN_8: + /* Prefer MO_ALIGN+MO_64 to MO_ALIGN_8+MO_64. */ + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + mop_2 =3D mop_1; + break; + case MO_ALIGN: + /* Second has 8-byte alignment; first has 16-byte alignment. */ + mop_2 =3D mop_1; + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN_16; + break; + case MO_ALIGN_16: + case MO_ALIGN_32: + case MO_ALIGN_64: + /* Second has 8-byte alignment; first retains original. */ + mop_2 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + break; + default: + g_assert_not_reached(); + } + ret[0] =3D mop_1; + ret[1] =3D mop_2; +} + +void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + /* + * Since there are no global TCGv_i128, there is no visible state + * changed if the second load faults. Load directly into the two + * subwords. + */ + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(x, x); + } + + addr_p8 =3D tcg_temp_new(); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); + tcg_temp_free(addr_p8); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(y, y); + } + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_R); +} + +void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + addr_p8 =3D tcg_temp_new(); + if ((mop[0] ^ memop) & MO_BSWAP) { + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_bswap64_i64(t, x); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); + tcg_gen_bswap64_i64(t, y); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); + tcg_temp_free_i64(t); + } else { + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + } + tcg_temp_free(addr_p8); + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_W); +} + static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) { switch (opc & MO_SSIZE) { --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708103; cv=none; d=zohomail.com; s=zohoarc; b=ODDS6Ts2s2iVvAywanki1/BGC/NlWPqRygv4A3I6X2iheIYMd2RUHXzjX8MPKNI3cblbdekyyoNN//kWEO9Z5o08iFGAl1yKt0xPtzIfRHbRh8pUSnxuW5eTZblg4vPuvf1AuyI+o8aG2PjRexUOVEBO44H9LD53pj9EeB7YGSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Dm8T8fHNlXfpnwGMsMrqY/OLEO5E66bAajv8z5mkMcE=; b=CC9TI45DO0br9WY1YoSK70COax05MKOVmgCBD4GfsR10EmOWIengVYz38nTKUf0FKVRFBJQDnlC5ykxJQvllNPw33wjoYOeAwSYjJ2QedV/z1J6Hw9/l9cT9mcULgI6qmeIvKOGEpI/8eH4AUtyEZWAw1YbBBIUl3X1FG5lu62M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708103135225.83733951173406; Wed, 25 Jan 2023 20:41:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2L-0000EO-Ku; Wed, 25 Jan 2023 23:38:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2J-0000DK-PZ for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:55 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2H-0004Sp-Os for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:55 -0500 Received: by mail-pj1-x1033.google.com with SMTP id b10so543569pjo.1 for ; Wed, 25 Jan 2023 20:38:53 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dm8T8fHNlXfpnwGMsMrqY/OLEO5E66bAajv8z5mkMcE=; b=akdnSQfszMJCE55qtZEIAtZpZ264MV20ZzdHSg11KLe/KwBGSDoYeKgt67LjctVpRl nxUfmxYAWmUDe7pkTwYuOxN7mOb4eanvjd4WboVRQXi9g9tdm+XkXznSQ+BbCsus9paQ kMy3EmglZXQQ6tvIBO9XR3DgtYqPtquBYNzTHRJKPMwa0NEMPMVE5c0my54KiFmPgT9D OtmpapH09o0sbhvw/VQftOI38EEJKdrOdZ3Hxe//CQ+aW2IJ5y4bB2qed2ZTWhdazptV 3+GKbs86vif0016Rl0z1NIOFxB2w8UzxKIgDkDRoQTYNaFrMhH6NQAmuV/Hh3LyoOxCB feVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dm8T8fHNlXfpnwGMsMrqY/OLEO5E66bAajv8z5mkMcE=; b=SVoYJ7AQYBtJvEwoPQQa8vP50kSFuN3xqDipSL9FmOiXJRkD67WtMonau/MT5gZ4XE bYQPGh2aUdNpTuK84ATuBb9SkWPI02OAG6V2fTXH1eR6Ounv1xDlZ4JPoJUlrAaY2Ycl uI7dFO2Oa43nz/HYboeKWUfMxR553YcbNhVOBRbfZm9es7eldfoDyIqHIM6zEffUsHyu RRPytC9NvuY2YlYusTU5Yzi7VPn2Kzqi2Q80IgmQiPhDRWKyosuiC6iNGImR5jg+ziYF Ssf5hpPpGFedlF9acEGn4bGOIdgjIr3zSarJjeqkTVqWnlV2wVAe847xBnQyao6A0rIj iwdQ== X-Gm-Message-State: AO0yUKV5WDhbDd1MJ1njiumHY8NNAplXU1sSeEWUSc4SHB2WfuWHxK0Q TKkisjHFGvoZXfia9ZDF5BsKWJ6vD+HLqEer5SQ= X-Google-Smtp-Source: AK7set+/JqVv0f7pFt7koCFlO6WYso0zG4pLz9yuRyNxc9UyqwKy6GZXSvEEB0hxTgCIFVzA8ncv/g== X-Received: by 2002:a17:90b:4b4e:b0:22c:2f04:d23b with SMTP id mi14-20020a17090b4b4e00b0022c2f04d23bmr17829pjb.23.1674707932378; Wed, 25 Jan 2023 20:38:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Date: Wed, 25 Jan 2023 18:38:04 -1000 Message-Id: <20230126043824.54819-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708103597100013 Content-Type: text/plain; charset="utf-8" This will allow targets to avoid rolling their own. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-runtime.h | 11 +++++ include/tcg/tcg-op.h | 5 +++ tcg/tcg-op.c | 85 +++++++++++++++++++++++++++++++++++ accel/tcg/atomic_common.c.inc | 45 +++++++++++++++++++ 4 files changed, 146 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 37cbd722bf..e141a6ab24 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -55,6 +55,17 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64, i32) #endif +#ifdef CONFIG_CMPXCHG128 +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +#endif + +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) =20 #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e5f5b63c37..31bf3d287e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -907,6 +907,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i= 32, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); + +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); =20 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 33ef325f6e..5811ecd3e7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3295,6 +3295,8 @@ typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env,= TCGv, TCGv_i32, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv_i64, TCGv_i32); +typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, + TCGv_i128, TCGv_i128, TCGv_i32); typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, @@ -3305,6 +3307,11 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env= , TCGv, #else # define WITH_ATOMIC64(X) #endif +#ifdef CONFIG_CMPXCHG128 +# define WITH_ATOMIC128(X) X, +#else +# define WITH_ATOMIC128(X) +#endif =20 static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_8] =3D gen_helper_atomic_cmpxchgb, @@ -3314,6 +3321,8 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP= ) + 1] =3D { [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) + WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) + WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, @@ -3412,6 +3421,82 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv = addr, TCGv_i64 cmpv, } } =20 +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 c= mpv, + TCGv_i128 newv, TCGArg idx, MemOp memo= p) +{ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Inline expansion below is simply too large for 32-bit hosts. */ + gen_atomic_cx_i128 gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE + ? gen_helper_nonatomic_cmpxchgo_le=20 + : gen_helper_nonatomic_cmpxchgo_be); + MemOpIdx oi =3D make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + } else { + TCGv_i128 oldv =3D tcg_temp_new_i128(); + TCGv_i128 tmpv =3D tcg_temp_new_i128(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + + tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); + + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); + + /* tmpv =3D equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); + } +} + +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, + TCGv_i128 newv, TCGArg idx, MemOp memop) +{ + gen_atomic_cx_i128 gen; + + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); + return; + } + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } + + gen_helper_exit_atomic(cpu_env); + + /* + * Produce a result for a well-formed opcode stream. This satisfies + * liveness for set before used, which happens before this dead code + * is removed. + */ + tcg_gen_movi_i64(TCGV128_LOW(retv), 0); + tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); +} + static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6602d7689f..8f2ce43ee6 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -55,8 +55,53 @@ CMPXCHG_HELPER(cmpxchgq_be, uint64_t) CMPXCHG_HELPER(cmpxchgq_le, uint64_t) #endif =20 +#ifdef CONFIG_CMPXCHG128 +CMPXCHG_HELPER(cmpxchgo_be, Int128) +CMPXCHG_HELPER(cmpxchgo_le, Int128) +#endif + #undef CMPXCHG_HELPER =20 +Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS =3D=3D 32 + uintptr_t ra =3D GETPC(); + Int128 oldv; + + oldv =3D cpu_ld16_be_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_be_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + +Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS =3D=3D 32 + uintptr_t ra =3D GETPC(); + Int128 oldv; + + oldv =3D cpu_ld16_le_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_le_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + #define ATOMIC_HELPER(OP, TYPE) \ TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, target_ulong addr, \ TYPE val, uint32_t oi) \ --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708099; cv=none; d=zohomail.com; s=zohoarc; b=dtDp2Eaw4vNoW//csfp1l0fDuTbS7WXlD4TnPkL8eRRZvW79d7y8DxBzoQlkKSvt/QwM94sVr4c2hVg1sl+p0+k7wuOdKmM0lZrpHJFiF4Joa6U/F7d4LGLob1y5PvTCB3y5u2DuIxW6+iSico/jCASVTXtrBFYhdsOv8l7j6TI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708099; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a0WrnpFv1Nw89i7DTl3h+lKdWz/K7go9+e+qOQj+GaM=; b=cOpisz26q+G+FDHgEntekOvhsBKIlByRwb65xUMI+YLI+ADasj9y9J62LX4GaqxaW7VKNHqHF5BL8am5Rr/1RSXNL0em0vdYPcluyPIGMVmSjoUpTDTwqInyMJet3rdgH7Z58JIAggmooIeTK7bkREJKrjj2gdk75/Xjv6qUkNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708099147538.2724709018926; Wed, 25 Jan 2023 20:41:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2M-0000Ej-JA; Wed, 25 Jan 2023 23:38:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2L-0000EE-7g for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:57 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2J-0004TF-DA for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:56 -0500 Received: by mail-pj1-x1029.google.com with SMTP id nn18-20020a17090b38d200b0022bfb584987so723359pjb.2 for ; Wed, 25 Jan 2023 20:38:55 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a0WrnpFv1Nw89i7DTl3h+lKdWz/K7go9+e+qOQj+GaM=; b=Vq83fiap5kMVZzHxPq42p7tMVo7ccxiqdUJFitJgniK4lMZc/pGorIy/L+MIuUgrGq 12xgrFdhDk73h8aTnE0miDmLhC0Kv96/zD5dfli+vjrqd3AEiREB0fbj1HXfJVHhRUFM h3Lzs+zcLDezC/ZdU8mQBJBradCRPW1QdqAzBLBtkb1g+NJ8c511HJlhrb7/PHBSHg2z Oxe9wsJjdy+AgKvt3eu1oX1djYrooovFszQ8PtYgLUP3kChzWlOKgzhWCZdeiCSoFqp5 lX/b/IoRxfW4z7uYgaC1Jt4U7zGVzVpldGcdWqbA1YCWSFwTu8016V1nQu6E+Wk8FL3R Cg8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a0WrnpFv1Nw89i7DTl3h+lKdWz/K7go9+e+qOQj+GaM=; b=WdftEr4dqJyJwNNsMYjZ+RcKH9PTt+qs7hfs9coUrW8Q1ggsxHITV5qLyK1P9u5R5S KSeGmiO5Wj9jvGW80JPgu6LglNsK8a1yqzGh66b5J83lkF+i2M/lopNq0CnNSXHDwN40 MqD0KrNuZ4JZyuUCs8Yj8XWeHYhP6g9OiY4WYceqilRWnHAjNAIDD7iOHPT4k5zbJBQ3 hJfcTkHwYn7E2KEDmwQVpWn/4iVaWS9Bai0ggH/YzVxWt9iF6motm94okWkYUveO2Jxx xJ356lzTQy7JxHyFc23+q2f8iZ1yodTRvMRWE04TBg/sYMUVGzaybjt+Qg58vNk05zQH brWg== X-Gm-Message-State: AO0yUKVOXG9yDv1SECxSTp8k2+EzzEvbdnQBNWg+8Y3TLWcQ2b/8yBT7 ExYCwygg2Ihrai4jReKKqJI+brsnFY7q+a93JjE= X-Google-Smtp-Source: AK7set8pB8kCZmjYcpuyRAY8PZLv7P0Uq5/Vp5uu39NGzBB12yPByGTDqTC6tQ4fa6aE6PHVlPLPDg== X-Received: by 2002:a17:90a:4e:b0:22b:f6fa:dd98 with SMTP id 14-20020a17090a004e00b0022bf6fadd98mr7640609pjb.20.1674707933872; Wed, 25 Jan 2023 20:38:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org Subject: [PATCH v5 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} Date: Wed, 25 Jan 2023 18:38:05 -1000 Message-Id: <20230126043824.54819-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708099653100001 Content-Type: text/plain; charset="utf-8" Normally this is automatically handled by the CF_PARALLEL checks with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special case of !PREFIX_LOCK where it always wants the non-atomic version. Split these out so that x86 does not have to roll its own. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ++ tcg/tcg-op.c | 154 +++++++++++++++++++++++++++---------------- 2 files changed, 101 insertions(+), 57 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 31bf3d287e..839d91c0c7 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -910,6 +910,10 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i= 64, TCGv_i64, void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); =20 +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, + TCGArg, MemOp); +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, + TCGArg, MemOp); void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 5811ecd3e7..c581ae77c4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3325,82 +3325,122 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BS= WAP) + 1] =3D { WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, + TCGv_i32 newv, TCGArg idx, MemOp memop) +{ + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + + tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_temp_free_i32(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, t1, memop); + } else { + tcg_gen_mov_i32(retv, t1); + } + tcg_temp_free_i32(t1); +} + void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, TCGv_i32 newv, TCGArg idx, MemOp memop) { - memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen_atomic_cx_i32 gen; + MemOpIdx oi; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - TCGv_i32 t1 =3D tcg_temp_new_i32(); - TCGv_i32 t2 =3D tcg_temp_new_i32(); - - tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); - tcg_temp_free_i32(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, t1, memop); - } else { - tcg_gen_mov_i32(retv, t1); - } - tcg_temp_free_i32(t1); - } else { - gen_atomic_cx_i32 gen; - MemOpIdx oi; - - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, retv, memop); - } + tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); + return; } + + memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, retv, memop); + } +} + +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, + TCGv_i64 newv, TCGArg idx, MemOp memop) +{ + TCGv_i64 t1, t2; + + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } + return; + } + + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + + tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_temp_free_i64(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(retv, t1, memop); + } else { + tcg_gen_mov_i64(retv, t1); + } + tcg_temp_free_i64(t1); } =20 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, TCGv_i64 newv, TCGArg idx, MemOp memop) { - memop =3D tcg_canonicalize_memop(memop, 1, 0); - if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 t2 =3D tcg_temp_new_i64(); + tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); + return; + } =20 - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); - tcg_temp_free_i64(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, t1, memop); - } else { - tcg_gen_mov_i64(retv, t1); - } - tcg_temp_free_i64(t1); - } else if ((memop & MO_SIZE) =3D=3D MO_64) { -#ifdef CONFIG_ATOMIC64 + if ((memop & MO_SIZE) =3D=3D MO_64) { gen_atomic_cx_i64 gen; - MemOpIdx oi; =20 + memop =3D tcg_canonicalize_memop(memop, 1, 0); gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } =20 - oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); -#else gen_helper_exit_atomic(cpu_env); - /* Produce a result, so that we have a well-formed opcode stream - with respect to uses of the result in the (dead) code following= . */ + + /* + * Produce a result for a well-formed opcode stream. This satisfi= es + * liveness for set before used, which happens before this dead co= de + * is removed. + */ tcg_gen_movi_i64(retv, 0); -#endif /* CONFIG_ATOMIC64 */ + return; + } + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } } else { TCGv_i32 c32 =3D tcg_temp_new_i32(); TCGv_i32 n32 =3D tcg_temp_new_i32(); --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674707976; cv=none; d=zohomail.com; s=zohoarc; b=icFyU7TJgHGtw8rEDVWO+QClLKbZZ4PZ/ifzvIvSXshcspLqcFueNmMw2E4fCIeHEMU5yQ37TqFjIOxNUBKFYY8cOuFaPyz+JSMQKDyaJFl3CeVu1KgSFvTPgGCQ4iDsSyPFEZRKgd6xU5F5bHlIyfBXk7is4L/MysLYqlhTDnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674707976; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/YmjqRjimF5pBKzTT9PtXE7Qwz8sieC4JwIiThrHTeM=; b=doFctHvN8Kxo1lUQTJgjQdJK1e1nzg58CTQ/mZNgDN2UKeK/QbhWrvt5lrcL01iGQoPp2q/oyfNbNhbI+6suFvQB5VikgRZ2OyhlbvIo801/3fP1FkkWhd0y/MjMk0Awn93Zabn39rzwKAoocKFn7UeZzij9z+UQy3SSs3PeGBE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674707976284711.5875778728896; Wed, 25 Jan 2023 20:39:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2S-0000F1-RL; Wed, 25 Jan 2023 23:39:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2M-0000Ek-L0 for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:59 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2K-0004TZ-Jq for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:38:58 -0500 Received: by mail-pj1-x1035.google.com with SMTP id m11so563204pji.0 for ; Wed, 25 Jan 2023 20:38:56 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674707977150100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-2-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 6 --- target/arm/helper-a64.c | 104 ------------------------------------- target/arm/translate-a64.c | 60 ++++++++++++--------- 3 files changed, 35 insertions(+), 135 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b706571bb..94065d1917 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,12 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16= , ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 77a8502b6b..7dbdb2c233 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,110 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val= , uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); - Int128 newv =3D int128_make128(new_lo, new_hi); - Int128 oldv; - uintptr_t ra =3D GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi0 =3D make_memop_idx(MO_LEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 =3D make_memop_idx(MO_LEUQ, mem_idx); - - o0 =3D cpu_ldq_le_mmu(env, addr + 0, oi0, ra); - o1 =3D cpu_ldq_le_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - success =3D int128_eq(oldv, cmpv); - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - Int128 cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val= ); - Int128 newv =3D int128_make128(new_hi, new_lo); - Int128 oldv; - uintptr_t ra =3D GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi0 =3D make_memop_idx(MO_BEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 =3D make_memop_idx(MO_BEUQ, mem_idx); - - o1 =3D cpu_ldq_be_mmu(env, addr + 0, oi0, ra); - o0 =3D cpu_ldq_be_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); - - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); - newv =3D int128_make128(new_hi, new_lo); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - success =3D int128_eq(oldv, cmpv); - return !success; -} - /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 52b1b8a1f0..bd97666ddc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2586,32 +2586,42 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (!HAVE_CMPXCHG128) { - gen_helper_exit_atomic(cpu_env); - /* - * Produce a result so we have a well-formed opcode - * stream when the following (dead) code uses 'tmp'. - * TCG will remove the dead ops for us. - */ - tcg_gen_movi_i64(tmp, 0); - } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } - } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv_i128 c16 =3D tcg_temp_new_i128(); + TCGv_i64 a, b; + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt), cpu_reg(s, rt= 2)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_val, + cpu_exclusive_high); + } else { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt2), cpu_reg(s, r= t)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_high, + cpu_exclusive_val); + } + + tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, + get_mem_index(s), + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(c16); + + a =3D tcg_temp_new_i64(); + b =3D tcg_temp_new_i64(); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(a, b, t16); + } else { + tcg_gen_extr_i128_i64(b, a, t16); + } + + tcg_gen_xor_i64(a, a, cpu_exclusive_val); + tcg_gen_xor_i64(b, b, cpu_exclusive_high); + tcg_gen_or_i64(tmp, a, b); + tcg_temp_free_i64(a); + tcg_temp_free_i64(b); + tcg_temp_free_i128(t16); + + tcg_gen_setcondi_i64(TCG_COND_NE, tmp, tmp, 0); } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708088; cv=none; d=zohomail.com; s=zohoarc; b=E9rBGI5aGv/E6WQEs4DvWep8a1lKm3lwaZCf8obO+GTI5hvBig6L84bkEZfNj1gDMFo1+a/dHhCAxJlx4NUAUm+MjzKGL+qpD472YB0NXLHIGPZLCnHcPngLxl3A85bQ3/RBtc/4cJtzKJ7ApgHLLvCXALcv5cJBjZpHyF1hacc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708089485100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-3-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 2 -- target/arm/helper-a64.c | 43 --------------------------- target/arm/translate-a64.c | 61 +++++++++++--------------------------- 3 files changed, 18 insertions(+), 88 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 94065d1917..ff56807247 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,8 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16,= ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) -DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7dbdb2c233..0972a4bdd0 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,49 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Writes back the old data into Rs. */ -void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs] =3D int128_getlo(oldv); - env->xregs[rs + 1] =3D int128_gethi(oldv); -} - -void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_hi, uint64_t new_lo) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs + 1] =3D int128_getlo(oldv); - env->xregs[rs] =3D int128_gethi(oldv); -} - /* * AdvSIMD half-precision */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bd97666ddc..6678894ec7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2694,53 +2694,28 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, tcg_gen_extr32_i64(s2, s1, cmp); } tcg_temp_free_i64(cmp); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 tcg_rs =3D tcg_constant_i32(rs); - if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } - } else { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp =3D DISAS_NORETURN; - } } else { - TCGv_i64 d1 =3D tcg_temp_new_i64(); - TCGv_i64 d2 =3D tcg_temp_new_i64(); - TCGv_i64 a2 =3D tcg_temp_new_i64(); - TCGv_i64 c1 =3D tcg_temp_new_i64(); - TCGv_i64 c2 =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_constant_i64(0); + TCGv_i128 cmp =3D tcg_temp_new_i128(); + TCGv_i128 val =3D tcg_temp_new_i128(); =20 - /* Load the two words, in memory order. */ - tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, - MO_64 | MO_ALIGN_16 | s->be_data); - tcg_gen_addi_i64(a2, clean_addr, 8); - tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(val, t1, t2); + tcg_gen_concat_i64_i128(cmp, s1, s2); + } else { + tcg_gen_concat_i64_i128(val, t2, t1); + tcg_gen_concat_i64_i128(cmp, s2, s1); + } =20 - /* Compare the two words, also in memory order. */ - tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); - tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); - tcg_gen_and_i64(c2, c2, c1); + tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(val); =20 - /* If compare equal, write back new data, else write back old data= . */ - tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); - tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); - tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); - tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); - tcg_temp_free_i64(a2); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - - /* Write back the data from memory to Rs. */ - tcg_gen_mov_i64(s1, d1); - tcg_gen_mov_i64(s2, d2); - tcg_temp_free_i64(d1); - tcg_temp_free_i64(d2); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(s1, s2, cmp); + } else { + tcg_gen_extr_i128_i64(s2, s1, cmp); + } + tcg_temp_free_i128(cmp); } } =20 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=g37jcnbUdUFyC2lRNcU9y8u8XHVRs+SKjrcv8erdOH1EG0cTZQe73OrqrbvKW5A9it F54rNYhLNh9gtbryDwUmlJQC4XpUDfUiB5GzdiD3WwbfjMdmbZYqRd/kzOE60KPxGRYd f1wB1rRsvzTctQLawfRF1HW1AFE5ClbDrBI2PA9w75zX5NcIoQ19n4OnwHDUzxIzrc1P 9ncCNKf/R5FKzekTNnY5wWn5xG+dehDKk+vZjtyRIhkxkOhC/0VD1CQMmb0TTYRHV5bF hKBd7BgdwABelsxcqBbPDJ82w4hV63KTxrBfSAH7muePpmQvNjoGjqD4P2SzI6ZVerqn C+ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=m0BfqNMhjmVDeVEbyCVr11SKAi9xwn7RItbhgqsP9m7M35J1S4HNlQZkBqdR81EbA9 7uRrfBeK5u8woYpPm4jDv7FyutDNpnk+yDlNgjo4vh0QN3df0Q5Wv3nvqO/3k4Pj2niN bLlnEurtnlL9llIUvN6znBgqWXeNQ4A98okLftFWPQTD+vw+qrBo7Z2oSMtWMDaFkgsN 1JY0jQhaN0XNtvu1nU6vkAvBj+/2oeZZINavL6FnGwn5faLejhZFB1746EFUTQujXDGh XXeTeVQWhxo9a70ovqcRHMUNbGZSsM21l181RwKTxqFiSUcZM0ihTEf8YC6YSIhm+tye B0aQ== X-Gm-Message-State: AFqh2kpip9PL9padeFhF0qelp78WlOG3F4g/JzSLXIK3TQzXugnabefF 43gQ9F6OqOyhpoquCOzMmvZGhsfn3dFlrBcGdQ4= X-Google-Smtp-Source: AMrXdXuWwW1GYGGoeGPRhgvGhfvDRnwOh1xEdJDhQy+zjcd5p3f1tBmo9Jd/v9T2tFfe1fhai7Pnrg== X-Received: by 2002:a05:6a21:3996:b0:b8:610f:cd43 with SMTP id ad22-20020a056a21399600b000b8610fcd43mr36110683pzc.35.1674707938663; Wed, 25 Jan 2023 20:38:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Daniel Henrique Barboza Subject: [PATCH v5 20/36] target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX Date: Wed, 25 Jan 2023 18:38:08 -1000 Message-Id: <20230126043824.54819-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708101564100009 Content-Type: text/plain; charset="utf-8" Note that the previous direct reference to reserve_val, - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))); was incorrect because all references should have gone through cpu_reserve_val. Create a cpu_reserve_val2 tcg temp to fix this. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20221112061122.2720163-2-richard.henderson@linaro.org> --- target/ppc/helper.h | 2 - target/ppc/mem_helper.c | 44 ----------------- target/ppc/translate.c | 102 ++++++++++++++++++---------------------- 3 files changed, 47 insertions(+), 101 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 8dd22a35e4..0beaca5c7a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -818,6 +818,4 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index d1163f316c..1578887a8f 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -413,50 +413,6 @@ void helper_stq_be_parallel(CPUPPCState *env, target_u= long addr, val =3D int128_make128(lo, hi); cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } - -uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success =3D false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr =3D=3D env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success =3D int128_eq(oldv, cmpv); - } - env->reserve_addr =3D -1; - return env->so + success * CRF_EQ_BIT; -} - -uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success =3D false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr =3D=3D env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success =3D int128_eq(oldv, cmpv); - } - env->reserve_addr =3D -1; - return env->so + success * CRF_EQ_BIT; -} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index edb3daa9b5..1c17d5a558 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -72,6 +72,7 @@ static TCGv cpu_cfar; static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_reserve_val; +static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; =20 @@ -141,8 +142,11 @@ void ppc_translate_init(void) offsetof(CPUPPCState, reserve_addr), "reserve_addr"); cpu_reserve_val =3D tcg_global_mem_new(cpu_env, - offsetof(CPUPPCState, reserve_val), - "reserve_val"); + offsetof(CPUPPCState, reserve_val= ), + "reserve_val"); + cpu_reserve_val2 =3D tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, reserve_va= l2), + "reserve_val2"); =20 cpu_fpscr =3D tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, fpscr), "fpscr"); @@ -3998,78 +4002,66 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { + TCGLabel *lab_fail, *lab_over; int rs =3D rS(ctx->opcode); - TCGv EA, hi, lo; + TCGv EA, t0, t1; + TCGv_i128 cmp, val; =20 if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } =20 + lab_fail =3D gen_new_label(); + lab_over =3D gen_new_label(); + gen_set_access_type(ctx, ACCESS_RES); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); =20 + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_temp_free(EA); + + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + /* Note that the low part is always in RS+1, even in LE mode. */ - lo =3D cpu_gpr[rs + 1]; - hi =3D cpu_gpr[rs]; + tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); =20 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); - if (ctx->le_mode) { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } else { - gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } - tcg_temp_free_i32(oi); - } else { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } - tcg_temp_free(EA); - } else { - TCGLabel *lab_fail =3D gen_new_label(); - TCGLabel *lab_over =3D gen_new_label(); - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + tcg_temp_free_i128(cmp); =20 - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_temp_free(EA); + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + tcg_gen_extr_i128_i64(t1, t0, val); + tcg_temp_free_i128(val); =20 - gen_qemu_ld64_i64(ctx, t0, cpu_reserve); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))= ); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); =20 - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_ld64_i64(ctx, t0, t0); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val) - : offsetof(CPUPPCState, reserve_val2)= )); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(t0, t0, cpu_so); + tcg_gen_trunc_tl_i32(cpu_crf[0], t0); + tcg_temp_free(t0); =20 - /* Success */ - gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); + tcg_gen_br(lab_over); + gen_set_label(lab_fail); =20 - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); - tcg_gen_br(lab_over); + /* + * Address mismatch implies failure. But we still need to provide + * the memory barrier semantics of the instruction. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); =20 - gen_set_label(lab_fail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(lab_over); - tcg_gen_movi_tl(cpu_reserve, -1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } + gen_set_label(lab_over); + tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */ =20 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708134; cv=none; d=zohomail.com; s=zohoarc; b=WsGPfWjJHrkg5zLxEJdslzGxNx033MuWZxF5RZqE74qM7u0b8E9EI8fkTztcRWYW5U3Ff5uCzhsUDqCx9RBSFuzYss9ggFpNJWj0zRbC0mHlcVYd4L4AFs4l+FSGthEkPtrOynkW3A/xJ08lZKiCxkRXKRo9s1/R23Zo4dvPO1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708134; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=RyCHfUo51EE29BLepaFkXlWuCxk+ZMWp7p11mr4zG1yF02zWcXp2G8IQnJ5SHdETGmp9VlmotafTC6DKjTq/hRm+97YCCLjZQk/KxSyD4+7H7HCX0ujMlOoo9DAeO2xJ2/yhzWKz/yf2EFz2Vg8HkqtmREZNS+VMW3vW11Yo12Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708134015766.3445231409373; Wed, 25 Jan 2023 20:42:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2o-0000OV-UF; Wed, 25 Jan 2023 23:39:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2Y-0000HM-DY for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:10 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2V-0004OJ-Fp for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:10 -0500 Received: by mail-pl1-x636.google.com with SMTP id a18so930571plm.2 for ; Wed, 25 Jan 2023 20:39:00 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:38:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=fsRAkMGQUW4N2QcnZSnYvzBT+7ZxQPSjiow+8PyLsf3RATiIIALz3vPrW5nkLperBz nb3+2HbOl0A+tGsgpJ/ZxSxPAune0SV7AKADZvcxIB79qdKDphVuBV1cXyFCCzq2DzTS P3oiNMomSBG/VkR0MDlG+/5sDMD5uGZYuv3aIeYtQPyttzw8veJtxiF1sajb4T8zhtI5 LjXQbFWN59ZBMKFzbt4WYjv4u/Itr06e8V5pS/oMl8gttHupgkYlKKqrmC7UdPc/SUdO RlXezqto6EhqisCe6Go7Iu4LjdVY0mIEHh6VLbUvN+tiMFp1uz2RsaOzmyoW+bb4cbF3 7nrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=lAQ54efGtbaVoCHGOWSBaxgaHMS3eZIY/H8BMXyYOy0r7TLGh9cUS5X+9zq5b94KNw XFfqMn5vKoLdFV7kpmd8ibqWhP6bf9Po4zFBLtTesNq1SsuYSPOMQR4myt7YzIH5yF1i 0mpMb8lIAMdxe6FWBgyZCzQIuRSXJaYydIoLSjRDOPtbwE49TrQdz1rGBQ43y8P7lZSM ZoaOCpmF/GgpnnKskXZJhDFbOqrdlrZ88k6A+G1AXrlXjHdgF59oYlEPsnvHyMrkloXh Ed2YTKewlh5TNJVZ1yx6PfAY4L4q6RmyEXFzI+gGPBOnVHbIpefnxL7dsLhg0nEvDaGt yt8g== X-Gm-Message-State: AFqh2krGzW2JuSYJrlEse+uMGGfTEjyxejuTjBH21478gx5jQec1LXYf 4s1n18vh+yxUMjqNVKr6jif2IidCDHk/nGUQaXo= X-Google-Smtp-Source: AMrXdXtk+Es3anERhHoLIt/u9NuAh8vydInx4W5cd4LosJ5ra3IOrRLp4CMr0Zv+fry9uNyrbDvb9w== X-Received: by 2002:a17:90b:1d0c:b0:22b:b46d:ebed with SMTP id on12-20020a17090b1d0c00b0022bb46debedmr22299279pjb.47.1674707940250; Wed, 25 Jan 2023 20:39:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Ilya Leoshkevich Subject: [PATCH v5 21/36] tests/tcg/s390x: Add div.c Date: Wed, 25 Jan 2023 18:38:09 -1000 Message-Id: <20230126043824.54819-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708135743100003 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/div.c | 40 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 41 insertions(+) create mode 100644 tests/tcg/s390x/div.c diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c new file mode 100644 index 0000000000..5807295614 --- /dev/null +++ b/tests/tcg/s390x/div.c @@ -0,0 +1,40 @@ +#include +#include + +static void test_dr(void) +{ + register int32_t r0 asm("r0") =3D -1; + register int32_t r1 asm("r1") =3D -4241; + int32_t b =3D 101, q, r; + + asm("dr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D -41); + assert(r =3D=3D -100); +} + +static void test_dlr(void) +{ + register uint32_t r0 asm("r0") =3D 0; + register uint32_t r1 asm("r1") =3D 4243; + uint32_t b =3D 101, q, r; + + asm("dlr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D 42); + assert(r =3D=3D 1); +} + +int main(void) +{ + test_dr(); + test_dlr(); +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 07fcc6d0ce..ab7a3bcfb2 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -24,6 +24,7 @@ TESTS+=3Dtrap TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec +TESTS+=3Ddiv =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708010; cv=none; d=zohomail.com; s=zohoarc; b=mOAakJCbvXvhDU2xF6uafCcKJdUM2SMIgXwE3JPl2aGPUv2t06/rCWwOeO7RU8zGZ35MwHpVzQGZb/CnPWGlCkLltaHxoXyYrkBcK1vIIGQ/X6AVb4x+CfMatW9wIdmFf1Wi3t49PpYJMkDz3E7lMIuxFDQriqgVSweF3gxafJk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708010; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=j9EwSuqpkLOLyomPq/WGx5+BiHFTfnNsZkK6UxF+/TY7N5HloVv/VYohrb66AieBMNmsWRQX1xXWOfaEory38/gC9FqqgbPJ4+kQ9wkqGUaIR7JoAdlPtrlrVbty1KpgR5qNlhMdrg2D+AajSP8YJBEouTFx3EDhQphsG9f0+T8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708010322920.9939806548172; Wed, 25 Jan 2023 20:40:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2g-0000Ii-Lt; Wed, 25 Jan 2023 23:39:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2Y-0000Hi-JE for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:10 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2V-0004U8-FV for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:10 -0500 Received: by mail-pj1-x102e.google.com with SMTP id j5so518356pjn.5 for ; Wed, 25 Jan 2023 20:39:02 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=rOVlxI8YqoKxFk72U9ZAs/52C4kwvRR+c4od1L3IHzN+ut5OXGPc5pKM9KaLHAlOdG v4hcGbtqFY4Z1gS5NyltnJHAuR4366QTNOMp5lQT6P+v+aow2Pa5Cz2mOyLtlGid7RLO eF9DhtbM/s9FGlYQM+sPiSCN7s2K10yqhLpOcb7sCw/+dMpGRg8mrO5mJmpb+y6EArLc zqzGh8D/H1m49ip46R1Tdo5R1XhlKaqWaONCjcn6U4xJNHpBb8mMxyItBLunZucmlt8P NihkrGLBDgFx/lL2azz3MLCTUwC9BrOMLaST7kfZ19uQkJlKj9/G/QOD7zoE/OChHpF6 Lg4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=pRs+wimGcy11pGBARquPUfNAVJ4gHpq/U0VkMKpy8bsrcUnjfcb13KYwZ37w21a7JJ +RQz+2vTIwr3A2Uz1CIOtEzmOY6y3MB7m5LV2+tZBVLb6pKcLT1//Qvf0qNca0Wiqopc 6E3E7PNi0mhJIllHJhGqnTvWpRE0vnmaBnmyMb5qxURli9jvAIy1RBo1+MiBrRYO2fDp lQfPjuq40ntqKTxv1F+k6iH5iLgAuGcBXazCkfJcTBSy9vOj//k59A75ttv8tHHeA/I0 i93XPgDpPxZX1dZ61QkqCjYyNCkSV0mhW3azc8+tmXLyTWBISTdl8SdaAPEKgQBPezfe MdUA== X-Gm-Message-State: AO0yUKUAVYYZ+czoRTCladcQvy+H1yh5LDesdxIgBWA1l7TZBlGmUhW6 ZlbnfxcGcqElfDtM8DMBK8CBy500nXYFb725HY8= X-Google-Smtp-Source: AK7set/G8xvW2tUdOpeC6juLeK4Pk6AVi3Xx4DGw7W2SGHj9cn+RVsW+xJGF5L5pxnzEiTAxjRFL8g== X-Received: by 2002:a17:90b:4c8e:b0:22c:1749:7ea5 with SMTP id my14-20020a17090b4c8e00b0022c17497ea5mr856234pjb.12.1674707941785; Wed, 25 Jan 2023 20:39:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Ilya Leoshkevich Subject: [PATCH v5 22/36] tests/tcg/s390x: Add clst.c Date: Wed, 25 Jan 2023 18:38:10 -1000 Message-Id: <20230126043824.54819-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708011256100007 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/clst.c | 82 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 83 insertions(+) create mode 100644 tests/tcg/s390x/clst.c diff --git a/tests/tcg/s390x/clst.c b/tests/tcg/s390x/clst.c new file mode 100644 index 0000000000..ed2fe7326c --- /dev/null +++ b/tests/tcg/s390x/clst.c @@ -0,0 +1,82 @@ +#define _GNU_SOURCE +#include +#include + +static int clst(char sep, const char **s1, const char **s2) +{ + const char *r1 =3D *s1; + const char *r2 =3D *s2; + int cc; + + do { + register int r0 asm("r0") =3D sep; + + asm("clst %[r1],%[r2]\n" + "ipm %[cc]\n" + "srl %[cc],28" + : [r1] "+r" (r1), [r2] "+r" (r2), "+r" (r0), [cc] "=3Dr" (cc) + : + : "cc"); + *s1 =3D r1; + *s2 =3D r2; + } while (cc =3D=3D 3); + + return cc; +} + +static const struct test { + const char *name; + char sep; + const char *s1; + const char *s2; + int exp_cc; + int exp_off; +} tests[] =3D { + { + .name =3D "cc0", + .sep =3D 0, + .s1 =3D "aa", + .s2 =3D "aa", + .exp_cc =3D 0, + .exp_off =3D 0, + }, + { + .name =3D "cc1", + .sep =3D 1, + .s1 =3D "a\x01", + .s2 =3D "aa\x01", + .exp_cc =3D 1, + .exp_off =3D 1, + }, + { + .name =3D "cc2", + .sep =3D 2, + .s1 =3D "abc\x02", + .s2 =3D "abb\x02", + .exp_cc =3D 2, + .exp_off =3D 2, + }, +}; + +int main(void) +{ + const struct test *t; + const char *s1, *s2; + size_t i; + int cc; + + for (i =3D 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + t =3D &tests[i]; + s1 =3D t->s1; + s2 =3D t->s2; + cc =3D clst(t->sep, &s1, &s2); + if (cc !=3D t->exp_cc || + s1 !=3D t->s1 + t->exp_off || + s2 !=3D t->s2 + t->exp_off) { + fprintf(stderr, "%s\n", t->name); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index ab7a3bcfb2..79250f31dd 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -25,6 +25,7 @@ TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec TESTS+=3Ddiv +TESTS+=3Dclst =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708002; cv=none; d=zohomail.com; s=zohoarc; b=Jre2MH8oiUaLFKFHz2GmrHwnP/71GkzSp8FEYugG7/nQVB3VwJRFjq2eP+GYP4SakZ/hBl1mdTaRl9Da/pYHstm/7dnGC8glk+GEPU3U54+dB2AYUxckBWa7bfR+zNI+D0UyI2nFXV5YRi+4XzurkTyn59H1wyJS2gHLkbJN5rg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708002; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wHZLFNNm0ZFp31ulDF75QeL44+XwFwYbg39T7b6YDuI=; b=LerTE3JDBupQ389sVLQzPw6lZU8kLM2BEbFm7PUOoip3ncw1iuGCIxZL38hx2N+2A7gP4cCqUAUv5NaM6O2aXIbC3Ut0GjJTR1fklcoGH4IKDGZM0aRAUho92txQM0U2Vd6ZEkJkPV94Ws709kyp7Nc1p0jYFTvUx7sHxj53II8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708002293769.8822197024601; Wed, 25 Jan 2023 20:40:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2Y-0000HP-IT; Wed, 25 Jan 2023 23:39:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2X-0000H3-18 for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:09 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2V-0004Rg-Fw for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:08 -0500 Received: by mail-pj1-x1035.google.com with SMTP id z1-20020a17090a66c100b00226f05b9595so756996pjl.0 for ; Wed, 25 Jan 2023 20:39:03 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708003149100001 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tests/tcg/s390x/long-double.c | 24 ++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/long-double.c diff --git a/tests/tcg/s390x/long-double.c b/tests/tcg/s390x/long-double.c new file mode 100644 index 0000000000..757a6262fd --- /dev/null +++ b/tests/tcg/s390x/long-double.c @@ -0,0 +1,24 @@ +/* + * Perform some basic arithmetic with long double, as a sanity check. + * With small integral numbers, we can cross-check with integers. + */ + +#include + +int main() +{ + int i, j; + + for (i =3D 1; i < 5; i++) { + for (j =3D 1; j < 5; j++) { + long double la =3D (long double)i + j; + long double lm =3D (long double)i * j; + long double ls =3D (long double)i - j; + + assert(la =3D=3D i + j); + assert(lm =3D=3D i * j); + assert(ls =3D=3D i - j); + } + } + return 0; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 79250f31dd..1d454270c0 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -26,6 +26,7 @@ TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec TESTS+=3Ddiv TESTS+=3Dclst +TESTS+=3Dlong-double =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BaPNUV0c7247g5NnraFY0tZEOzKo666SsANsAFMshsk=; b=XfpXMwT1eKZ8klyN5pMeD6yVXvJfnP515CrIgKG+MOnMx8REEynWgzXSQCagSzOCZY B8yqAZ6B+96U5d5iHSGaVRhSTEHNv/hO+eCh9i8QZOa1rdcQu3f+T5ft759pwh/VfU5w MOBdN/tyJ0PXvJ0G1trx0mkvYFwqqiyDHllCBQ8bllkED8wKdfd6I+qGqb1d7G+Zx8M8 G8sOTnc3pEyluB1S1Km2hx9VPJtsK0WZa28SAxwawczzyGoUOf4sHC9ZvHO1Bz8bjUOC XHW9IMgKM0gKhB4CtDU8gQ12jYs/kqrP/JiQTWLKKh5YEIqdwdF2Rh8RwDNqmiMwJReh p77w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BaPNUV0c7247g5NnraFY0tZEOzKo666SsANsAFMshsk=; b=gyKNsOOqd2P5phl+Plk5VrLw+DLU2S9PB5onmBgcBXZTMgkR2rQSYDG+iR4ZNZcvBt DWHXvSt/ID9vQY2ZesbnE1czl3yFVHH+76JtXALhHWkg71cB/MqcprppHN2lNUsYI6ju 5Io6DZ4baitvrwFHNCqb12Urec8oREllbLAL8swJSlKpx84hlrkw7xMzA19GS0F0IDoE s8Nu3tcd8mPg1TcgWc8gr8b+7QGsgsCluPj2MTRn7kW5GhV9Co2I2J4Zq2CnN8KEviGS IKA0II/O5KzfI9HYDBvxmD2wJc1NKA8/ZEE5YnWhItdUW6+P2saSFzw0YkXdxJWYQOJp aA3Q== X-Gm-Message-State: AFqh2kpAr4x3/Kxbcum7DlmaDfkmlEmZHePPCFazf2a3Z0vE/Vp8RE3C rzo3Xl+pZhgOXmXQggBnrj+ZqJflwEX9Jp4iEEw= X-Google-Smtp-Source: AMrXdXvX0rYU94hRT+4Mk1KGbu4qR10Kta11LEpN7OTfScF41gu4w3/RJsdVgto2Tfq7gqs5yonBhg== X-Received: by 2002:a17:90b:3eca:b0:22b:b89b:b9d0 with SMTP id rm10-20020a17090b3eca00b0022bb89bb9d0mr21215869pjb.22.1674707945250; Wed, 25 Jan 2023 20:39:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, David Hildenbrand , Ilya Leoshkevich Subject: [PATCH v5 24/36] target/s390x: Use a single return for helper_divs32/u32 Date: Wed, 25 Jan 2023 18:38:12 -1000 Message-Id: <20230126043824.54819-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708151755100001 Content-Type: text/plain; charset="utf-8" Pack the quotient and remainder into a single uint64_t. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v2: Fix operand ordering; use tcg_extr32_i64. Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/helper.h | 2 +- target/s390x/tcg/int_helper.c | 26 +++++++++++++------------- target/s390x/tcg/translate.c | 8 ++++---- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 93923ca153..bc828d976b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -10,7 +10,7 @@ DEF_HELPER_FLAGS_4(clc, TCG_CALL_NO_WG, i32, env, i32, i6= 4, i64) DEF_HELPER_3(mvcl, i32, env, i32, i32) DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) -DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64) +DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 954542388a..7260583cf2 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -34,45 +34,45 @@ #endif =20 /* 64/32 -> 32 signed division */ -int64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) +uint64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) { - int32_t ret, b =3D b64; - int64_t q; + int32_t b =3D b64; + int64_t q, r; =20 if (b =3D=3D 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - ret =3D q =3D a / b; - env->retxl =3D a % b; + q =3D a / b; + r =3D a % b; =20 /* Catch non-representable quotient. */ - if (ret !=3D q) { + if (q !=3D (int32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - return ret; + return deposit64(q, 32, 32, r); } =20 /* 64/32 -> 32 unsigned division */ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a, uint64_t b64) { - uint32_t ret, b =3D b64; - uint64_t q; + uint32_t b =3D b64; + uint64_t q, r; =20 if (b =3D=3D 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - ret =3D q =3D a / b; - env->retxl =3D a % b; + q =3D a / b; + r =3D a % b; =20 /* Catch non-representable quotient. */ - if (ret !=3D q) { + if (q !=3D (uint32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - return ret; + return deposit64(q, 32, 32, r); } =20 /* 64/64 -> 64 signed division */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a339b277e9..169f7ee1b2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2395,15 +2395,15 @@ static DisasJumpType op_diag(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_divs32(DisasContext *s, DisasOps *o) { - gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divs32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 static DisasJumpType op_divu32(DisasContext *s, DisasOps *o) { - gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divu32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708007; cv=none; d=zohomail.com; s=zohoarc; b=KhT441cnYcBJb/C98RRNAWP/P0XHaXDuxXmefJlM6p4E9WzsLIBQYA1BGNQxh4mVmAKtlVHfkJv7LnWVYWcykzV4xwZcgfxgG56dTUtjFn9GHjB2XGkZZuN4UsuVoq3ChPFp63vCNv4OeVtXnVPNC9PwVUiRlIxUoC6v3VE533Q= ARC-Message-Signature: i=1; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zggxelJn7xEGVyzBGDuJjR27fAkYzw0xoPZGZDzp+DI=; b=u18Ci3Dg+MPW2Ol3pYCUCicusd+tHqhXDotc60fPmFT5O7ORYUslzBmZ96oY8sPvOa 24ykFOMVrpFEDzrAB+nTi05bJQts6xOY+drJ0uFKQw9lmY6qtjYEstQZQ9xXa01TVyXH s+NNksGPqq2ilHIk7le2H+vXRGqbk09PUYycqd+4m5vCd37xBCHi8Og33gWOGNuNhGrn Y6EdHV4d+h77g42+gKZTnXDYAV9iWyhNRNznz4+CQzz0eYZfoLRnpEuBV2CdU/Bs83xY wTtUVOtRY3W1fEk3ElkNXhCzlTf+1D/xAYKlXTAH8clSCcWiKjO3LjXSoDBbfHdiDdde K58w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zggxelJn7xEGVyzBGDuJjR27fAkYzw0xoPZGZDzp+DI=; b=BokbyGokGb2UM28UXxgxMokv+FxjclzdCM+oxh4W5ProWkV0719Ci4TQncr1EhzixJ kq/VA4WBVAqEuIW6lWuuVZ6nK2lRUYhsRM/yUJj84imURBoP81jlIeYxngQAqmskk/b+ w1hYcIaBTVCRgJhl1xisSv3l4uDMiUXAHgVChfgGtZjHRBEyUsYEZNYjUjNCTi5SDf24 rnpswBQC5+4gzLzzyPyUnyW81Je08A8ANbnUI243thnjl2OO2XXFSqwgjzY44JU4hN5r AiIgjm+xN23lXtGz4Paki/5QnOa2khJSYFnlUp2qH+9m1TSZFu8lj1L9d716JXPvV30M FOSw== X-Gm-Message-State: AO0yUKWpLXif9fNTuJLOQAMln9yVSxQwVydJwSAmUX5jhkcGHI6MG11A y6kLK66h4sEulaq1WxRTy/Incv0mvNP0JATvYVo= X-Google-Smtp-Source: AK7set+lB/+09tDuJQWew3+lU2xyONBuKOBx61hJ3I29+L5m/Zgv48Yy3BRBqO5Gs2X0WtnQEbtyyg== X-Received: by 2002:a17:90b:33c6:b0:22c:665:6ee with SMTP id lk6-20020a17090b33c600b0022c066506eemr5323749pjb.31.1674707946964; Wed, 25 Jan 2023 20:39:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v5 25/36] target/s390x: Use a single return for helper_divs64/u64 Date: Wed, 25 Jan 2023 18:38:13 -1000 Message-Id: <20230126043824.54819-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708009224100001 Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- v2: Extended div test case to cover these insns. --- target/s390x/helper.h | 4 ++-- target/s390x/tcg/int_helper.c | 38 +++++++++-------------------------- target/s390x/tcg/translate.c | 14 +++++++++---- tests/tcg/s390x/div.c | 35 ++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 35 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bc828d976b..593f3c8bee 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -12,8 +12,8 @@ DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) -DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64, s64) +DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) DEF_HELPER_4(clst, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 7260583cf2..eb8e6dd1b5 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -76,46 +76,26 @@ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a,= uint64_t b64) } =20 /* 64/64 -> 64 signed division */ -int64_t HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) +Int128 HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) { /* Catch divide by zero, and non-representable quotient (MIN / -1). */ if (b =3D=3D 0 || (b =3D=3D -1 && a =3D=3D (1ll << 63))) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - env->retxl =3D a % b; - return a / b; + return int128_make128(a / b, a % b); } =20 /* 128 -> 64/64 unsigned division */ -uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t b) +Int128 HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64= _t b) { - uint64_t ret; - /* Signal divide by zero. */ - if (b =3D=3D 0) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); - } - if (ah =3D=3D 0) { - /* 64 -> 64/64 case */ - env->retxl =3D al % b; - ret =3D al / b; - } else { - /* ??? Move i386 idivq helper to host-utils. */ -#ifdef CONFIG_INT128 - __uint128_t a =3D ((__uint128_t)ah << 64) | al; - __uint128_t q =3D a / b; - env->retxl =3D a % b; - ret =3D q; - if (ret !=3D q) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); + if (b !=3D 0) { + uint64_t r =3D divu128(&al, &ah, b); + if (ah =3D=3D 0) { + return int128_make128(al, r); } -#else - /* 32-bit hosts would need special wrapper functionality - just ab= ort if - we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); -#endif } - return ret; + /* divide by zero or overflow */ + tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 uint64_t HELPER(cvd)(int32_t reg) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 169f7ee1b2..6953b81de7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2409,15 +2409,21 @@ static DisasJumpType op_divu32(DisasContext *s, Dis= asOps *o) =20 static DisasJumpType op_divs64(DisasContext *s, DisasOps *o) { - gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + TCGv_i128 t =3D tcg_temp_new_i128(); + + gen_helper_divs64(t, cpu_env, o->in1, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } =20 static DisasJumpType op_divu64(DisasContext *s, DisasOps *o) { - gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out); + TCGv_i128 t =3D tcg_temp_new_i128(); + + gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } =20 diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c index 5807295614..6ad9900e08 100644 --- a/tests/tcg/s390x/div.c +++ b/tests/tcg/s390x/div.c @@ -33,8 +33,43 @@ static void test_dlr(void) assert(r =3D=3D 1); } =20 +static void test_dsgr(void) +{ + register int64_t r0 asm("r0") =3D -1; + register int64_t r1 asm("r1") =3D -4241; + int64_t b =3D 101, q, r; + + asm("dsgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D -41); + assert(r =3D=3D -100); +} + +static void test_dlgr(void) +{ + register uint64_t r0 asm("r0") =3D 0; + register uint64_t r1 asm("r1") =3D 4243; + uint64_t b =3D 101, q, r; + + asm("dlgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D 42); + assert(r =3D=3D 1); +} + int main(void) { test_dr(); test_dlr(); + test_dsgr(); + test_dlgr(); + return 0; } --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708198; cv=none; d=zohomail.com; s=zohoarc; b=QEXjsDdnLAgOAi3Xt8L0bMJweIqY7VNvXYMxxN/raY6r949FwnwfV14NlsEgkGX80DdPSdKjlniziDIhST7i6hpDBQdMshp5rYD2A0H9zr0MmbtQWihnPc9e7CtthM+eN6Z+EhWt+vi4tGXTzaX/7Eac9rQgONGGS5yjHqASzGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708198; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SzDpq4p4TZ0OiGc3bd/AjIVDg1qF6XupmGP3awuLITw=; b=cUzsckyU0kqJCsONceqSH4w4SDzOgnBqN4rGzys++4zYsUz6eFQUTIo/bVmWLJKN95kOBHzr4c4KpFlerStve9L+6nD+t5tlaCArdMtEj3zx3SKGMfHggiJ20mmvZTi0RfPvCYi4aRFxKW8yyVgmCfP5mXhUXYfzx3XC9W8bi2o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708198820639.451950431534; Wed, 25 Jan 2023 20:43:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2q-0000Sx-3S; Wed, 25 Jan 2023 23:39:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2Z-0000I3-Qu for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:15 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2X-0004Qk-JS for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:11 -0500 Received: by mail-pj1-x102b.google.com with SMTP id v6-20020a17090ad58600b00229eec90a7fso5407949pju.0 for ; Wed, 25 Jan 2023 20:39:09 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708199943100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 11 ++++------- target/s390x/tcg/translate.c | 8 ++++++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 593f3c8bee..25c2dd0b3c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -16,7 +16,7 @@ DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64= , s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) -DEF_HELPER_4(clst, i64, env, i64, i64, i64) +DEF_HELPER_4(clst, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index cb82cd1c1d..9be42851d8 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -886,7 +886,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) } =20 /* unsigned string compare (c is string terminator) */ -uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_= t s2) +Int128 HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t = s2) { uintptr_t ra =3D GETPC(); uint32_t len; @@ -904,23 +904,20 @@ uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c,= uint64_t s1, uint64_t s2) if (v1 =3D=3D c) { /* Equal. CC=3D0, and don't advance the registers. */ env->cc_op =3D 0; - env->retxl =3D s2; - return s1; + return int128_make128(s2, s1); } } else { /* Unequal. CC=3D{1,2}, and advance the registers. Note that the terminator need not be zero, but the string that contai= ns the terminator is by definition "low". */ env->cc_op =3D (v1 =3D=3D c ? 1 : v2 =3D=3D c ? 2 : v1 < v2 ? = 1 : 2); - env->retxl =3D s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } } =20 /* CPU-determined bytes equal; advance the registers. */ env->cc_op =3D 3; - env->retxl =3D s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } =20 /* move page */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 6953b81de7..8397fe2bd8 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2164,9 +2164,13 @@ static DisasJumpType op_clm(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_clst(DisasContext *s, DisasOps *o) { - gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2); + TCGv_i128 pair =3D tcg_temp_new_i128(); + + gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); + tcg_gen_extr_i128_i64(o->in2, o->in1, pair); + tcg_temp_free_i128(pair); + set_cc_static(s); - return_low128(o->in2); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708209; cv=none; d=zohomail.com; s=zohoarc; b=LSmSUWVQlYHyz4TmYw2W4Q7e2KTWv0uExP05zlK2Cx7rxHvxAhcuT9hC0kz4fnR1pVaPY1IZCHp0nzcmwcox4EZKI3WnPM/nIudbVpseoST1rWO4DjOQ58FLM0bi4BBcBO4+di1sGFC+f5U1gPn/5RrienaIrbIFruxhIX4NrV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708209; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=XAbvm/XmhphpxhDI7g29vkn8daNY2Rehyp9+xNhD8BweCNPU5QcSFVQ7wvp6XIy8oJg6drWuThxFlh6upmNOGB01FvwRj6pHSCcX2tBklznkR1Jm5vVMi5rayF1JWGMgbJfLeGRkNxyc5C2VHQbYQgM40Ztu/9/dXZyXm9UQcIo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708209652678.9273705615459; Wed, 25 Jan 2023 20:43:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2r-0000Tk-ET; Wed, 25 Jan 2023 23:39:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2e-0000Ia-9B for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:16 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2Z-0004VR-IB for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:13 -0500 Received: by mail-pj1-x102b.google.com with SMTP id lp10so524659pjb.4 for ; Wed, 25 Jan 2023 20:39:10 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708209952100001 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 6 ++++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 25c2dd0b3c..03b29efa3e 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -103,7 +103,7 @@ DEF_HELPER_4(tre, i64, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) -DEF_HELPER_4(cksm, i64, env, i64, i64, i64) +DEF_HELPER_4(cksm, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i= 64) DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 9be42851d8..b0b403e23a 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1350,8 +1350,8 @@ uint32_t HELPER(clclu)(CPUS390XState *env, uint32_t r= 1, uint64_t a2, } =20 /* checksum */ -uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, - uint64_t src, uint64_t src_len) +Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, + uint64_t src, uint64_t src_len) { uintptr_t ra =3D GETPC(); uint64_t max_len, len; @@ -1392,8 +1392,7 @@ uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, env->cc_op =3D (len =3D=3D src_len ? 0 : 3); =20 /* Return both cksm and processed length. */ - env->retxl =3D cksm; - return len; + return int128_make128(cksm, len); } =20 void HELPER(pack)(CPUS390XState *env, uint32_t len, uint64_t dest, uint64_= t src) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8397fe2bd8..1a7aa9e4ae 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2041,11 +2041,13 @@ static DisasJumpType op_cxlgb(DisasContext *s, Disa= sOps *o) static DisasJumpType op_cksm(DisasContext *s, DisasOps *o) { int r2 =3D get_field(s, r2); + TCGv_i128 pair =3D tcg_temp_new_i128(); TCGv_i64 len =3D tcg_temp_new_i64(); =20 - gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]); + gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); - return_low128(o->out); + tcg_gen_extr_i128_i64(o->out, len, pair); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708147733100005 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 7 +++++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 03b29efa3e..b4170a4256 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_4(unpka, TCG_CALL_NO_WG, i32, env, i64, = i32, i64) DEF_HELPER_FLAGS_4(unpku, TCG_CALL_NO_WG, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32) DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64) -DEF_HELPER_4(tre, i64, env, i64, i64, i64) +DEF_HELPER_4(tre, i128, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b0b403e23a..49969abda7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1632,8 +1632,8 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uin= t64_t array, do_helper_tr(env, len, array, trans, GETPC()); } =20 -uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, - uint64_t len, uint64_t trans) +Int128 HELPER(tre)(CPUS390XState *env, uint64_t array, + uint64_t len, uint64_t trans) { uintptr_t ra =3D GETPC(); uint8_t end =3D env->regs[0] & 0xff; @@ -1668,8 +1668,7 @@ uint64_t HELPER(tre)(CPUS390XState *env, uint64_t arr= ay, } =20 env->cc_op =3D cc; - env->retxl =3D len - i; - return array + i; + return int128_make128(len - i, array + i); } =20 static inline uint32_t do_helper_trt(CPUS390XState *env, int len, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1a7aa9e4ae..f3e4b70ed9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -4905,8 +4905,11 @@ static DisasJumpType op_tr(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_tre(DisasContext *s, DisasOps *o) { - gen_helper_tre(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + TCGv_i128 pair =3D tcg_temp_new_i128(); + + gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, pair); + tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; } --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708099; cv=none; d=zohomail.com; s=zohoarc; b=Fkoga9V8q7xqug43Ptb3E4YQcemYcVSDyAy9AulK94JaE1p8WTQeP8twTSIZzj/By9wk2xVjQsJP1xXUl+hbrHnft1F4LODUMqA//JXcMW6HPHfFO7kcex5qthFh5xaBXX2qCpsXYEm2ULWkungjsuwqlvvzZhdd5ljMFlzgQNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708099; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; b=rPKyx/y193LPwqefZ2OllQ5y4bYyQEomrA6/AV/ML6bLOFSQ56zLKps6Rm+qsPfFm3 i33kwwr5lbh1EmHReRNE8Zos1nNPvUYYhrIvkuZdwy3e+ALAWg1SzTL9fWE+nelJQSTM 255CQGgJIEAE6ZbuMd6VjpYr/ooT0Eh1bx/eMEPU4DVhwj2hq4Fo9IG4Ov9w5YrCcNJm B8EllEr8rfbNswnoE9yy8qkR4nWxC1kjP8vxdAUWMGsOtXE+xmuvvDpo1vom0f+fpKsH bgjILCe44cHrBmVJR742dvh9fqJ2RMDHT/dGZ0Lx6WrfUZTCPPySJhMMOIDeV+5GqK/s VJ+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; b=R+DGlPjDv9bPvPp/xtOhBn2R4PFvuoy0/I+kmcFL06AXvsRYipPjdgGItsgBB7Dhsj PIs0j9ICICGyDhKtXd8IgK3bD1T/vVFSmw3Mw/yOsrWLTDedn7U8KYxxke3l4T1brgzn zZ8EgdCZ9iOgObKS+E6qXUnq1IoSoMKq4BCuuU7MksLC9dcfbVaM7P4kdlaHRxsxMnS5 VATdXCvjCwahzG5fnPy1Ddc7jFuBSkb6zkvdhKN66bDmKjAzrXFziwzbWXTbYGyprYFZ ib18eS5ilT5tlj4aL0CcmCzTXEc+uS3eDBZplMLtFgT6o+A2m3454lCHbFznu5OTBrzS auGw== X-Gm-Message-State: AO0yUKW7Nwq7LGAY0YxMfZ5zd+deksHUcJh0J9lf/GZF1dLgQlqIbtrl b9qtlvUx+yjDwANpbF1DjTOwFi9/XtHNSJs6Co0= X-Google-Smtp-Source: AK7set83dTR/2eUF1KCmySVTv6Yqf8JJQZieiw0p2IlR2nfB1njFJKcNbDqgpZT4/zpueKXRbbBVUw== X-Received: by 2002:a17:90a:31a:b0:22b:b681:2bb3 with SMTP id 26-20020a17090a031a00b0022bb6812bb3mr762459pje.38.1674707953703; Wed, 25 Jan 2023 20:39:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Ilya Leoshkevich Subject: [PATCH v5 29/36] target/s390x: Copy wout_x1 to wout_x1_P Date: Wed, 25 Jan 2023 18:38:17 -1000 Message-Id: <20230126043824.54819-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708101533100007 Content-Type: text/plain; charset="utf-8" Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 12 ++++++------ target/s390x/tcg/translate.c | 8 ++++++++ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 79c6ab509a..d0814cb218 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -422,7 +422,7 @@ F(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0, IF_AFP1 |= IF_AFP2) F(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) F(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) - F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1, movx, 0, IF_AFP1) + F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1_P, movx, 0, IF_AFP1) /* LOAD IMMEDIATE */ C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0) /* LOAD RELATIVE LONG */ @@ -461,7 +461,7 @@ C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64) F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP) F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP) - F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1, movx, f128, IF_BFP) + F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP) /* LOAD AND TRAP */ C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0) C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0) @@ -483,7 +483,7 @@ C(0xb913, LCGFR, RRE, Z, 0, r2_32s, r1, 0, neg, neg64) F(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32, IF_BFP) F(0xb313, LCDBR, RRE, Z, 0, f2, new, f1, negf64, f64, IF_BFP) - F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1, negf128, f128, IF_= BFP) + F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1_P, negf128, f128, I= F_BFP) F(0xb373, LCDFR, RRE, FPSSH, 0, f2, new, f1, negf64, 0, IF_AFP1 | = IF_AFP2) /* LOAD COUNT TO BLOCK BOUNDARY */ C(0xe727, LCBB, RXE, V, la2, 0, r1, 0, lcbb, 0) @@ -552,7 +552,7 @@ C(0xb911, LNGFR, RRE, Z, 0, r2_32s, r1, 0, nabs, nabs64) F(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32, IF_BFP) F(0xb311, LNDBR, RRE, Z, 0, f2, new, f1, nabsf64, f64, IF_BFP) - F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1, nabsf128, f128, IF= _BFP) + F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1_P, nabsf128, f128, = IF_BFP) F(0xb371, LNDFR, RRE, FPSSH, 0, f2, new, f1, nabsf64, 0, IF_AFP1 |= IF_AFP2) /* LOAD ON CONDITION */ C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0) @@ -577,7 +577,7 @@ C(0xb910, LPGFR, RRE, Z, 0, r2_32s, r1, 0, abs, abs64) F(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32, IF_BFP) F(0xb310, LPDBR, RRE, Z, 0, f2, new, f1, absf64, f64, IF_BFP) - F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1, absf128, f128, IF_= BFP) + F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1_P, absf128, f128, I= F_BFP) F(0xb370, LPDFR, RRE, FPSSH, 0, f2, new, f1, absf64, 0, IF_AFP1 | = IF_AFP2) /* LOAD REVERSED */ C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0) @@ -588,7 +588,7 @@ /* LOAD ZERO */ F(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0, IF_AFP1) F(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0, IF_AFP1) - F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0, IF_AFP1) + F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1_P, zero2, 0, IF_AFP1) =20 /* LOAD FPC */ F(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0, IF_BFP) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f3e4b70ed9..d25b6f3c03 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5518,6 +5518,14 @@ static void wout_x1(DisasContext *s, DisasOps *o) } #define SPEC_wout_x1 SPEC_r1_f128 =20 +static void wout_x1_P(DisasContext *s, DisasOps *o) +{ + int f1 =3D get_field(s, r1); + store_freg(f1, o->out); + store_freg(f1 + 2, o->out2); +} +#define SPEC_wout_x1_P SPEC_r1_f128 + static void wout_cond_r1r2_32(DisasContext *s, DisasOps *o) { if (get_field(s, r1) !=3D get_field(s, r2)) { --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708178; cv=none; d=zohomail.com; s=zohoarc; b=CkOL1Oim4UUZLxUjo6kUmoFgA0qpjwmqRcPodWFBGw0YQviz4EnhxmxcWezFXTiXXe/A4KtUGDRED7TIh0Mg57AdmNWw9Kj/6fwDGFHJKWLqUGPhC4gmnVXs3F3nyq5xeTokNnAU+nImL4AiXV+jcZHRqxWX8Gv9hLRtFbBWxX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708178; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mnJae2XWTp6f4pv/OJfYN9Mm46ElpE4QE5RfX1Hhsh4=; b=T9jvk25eICILkOlhVCGcpPMr1fqEhzWGbFEinlpUPsUWK5/gjp/FhJA5AruZN9da6f L55nHHl8+Y4Lrg1IVEd8Od0q/Cukyb648/5WOFj3rlCmSAgDiYdR/ZPZP0u3QYIdlqAS uPrLsA5JlFytqEyAqXFhcZh0/LKg9AMBx+3q1XkjLfipVfb83oWMx3v6cUzDu8Uy1V62 bBVdutScixTa8dgBICVyXUeYE/ZWW4a+hBmEGQyGbclWukQgECFswAXW7v4/scuYT8pb 6H+Q3HgkW/m6oBfx9Ib1JBlCaLop/DFCNZPRU4qTQHmgN6EMiMA2YaGJIT/PTYc3x5cz FQpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mnJae2XWTp6f4pv/OJfYN9Mm46ElpE4QE5RfX1Hhsh4=; b=UkI9jj5beQGjyAHvwOyA7tWa4ArUYecZOM+7ySuk2sEowiBaIni8C1LsQLL2e2+MdS gsTx6YlfZMs0FpiVtIcxJoAx8lNZMUX+LEKHYNmKVUXacqo0ireH4R44NJu6anTk1whl 0WcUGmPaXycbc9YzqkF7ZANBPBN0nPP3pqttrhdf9yt6H8jtiEgwJGXq0Buu69+xT+iC JKxwrwYqIrTCJMNTwkRsZ414mA85ljG7sNqyYggOCZbFsUm3zT7RLuMmh9BukBPTXwaY bkLhGJI0zyT0bWLCNNIvS2dvdqQQFy9go0ukah2ASCnxrQxac6UVekOlai3U3ftzu8gW S77Q== X-Gm-Message-State: AFqh2kpv5rNhEQWRwgdyVjkcb14JkMjl7jyMYSCKG7QC/JD8cQ2JOiXa +EeV2Ri4/1VSLFyYC/bj8reBx4eTl/WzoPpQeQk= X-Google-Smtp-Source: AMrXdXuH9y8Uzaz7g02uGZ+GABTxY4mUCxm/yS+VlFADnlX+kslxcKKoSPuI0sblU+1XgwxP/NcF6A== X-Received: by 2002:a17:90a:5913:b0:229:c282:77c0 with SMTP id k19-20020a17090a591300b00229c28277c0mr32324551pji.45.1674707955456; Wed, 25 Jan 2023 20:39:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Hildenbrand , Ilya Leoshkevich Subject: [PATCH v5 30/36] target/s390x: Use Int128 for returning float128 Date: Wed, 25 Jan 2023 18:38:18 -1000 Message-Id: <20230126043824.54819-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708179852100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Acked-by: David Hildenbrand --- v2: Remove extraneous return_low128. Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/helper.h | 22 +++++++------- target/s390x/tcg/insn-data.h.inc | 20 ++++++------- target/s390x/tcg/fpu_helper.c | 29 +++++++++--------- target/s390x/tcg/translate.c | 51 +++++++++++++++++--------------- 4 files changed, 63 insertions(+), 59 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b4170a4256..d40aeb471f 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -31,32 +31,32 @@ DEF_HELPER_4(clcle, i32, env, i32, i64, i32) DEF_HELPER_4(clclu, i32, env, i32, i64, i32) DEF_HELPER_3(cegb, i64, env, s64, i32) DEF_HELPER_3(cdgb, i64, env, s64, i32) -DEF_HELPER_3(cxgb, i64, env, s64, i32) +DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) -DEF_HELPER_3(cxlgb, i64, env, i64, i32) +DEF_HELPER_3(cxlgb, i128, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) -DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) +DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) @@ -79,7 +79,7 @@ DEF_HELPER_3(clfdb, i64, env, i64, i32) DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) @@ -89,7 +89,7 @@ DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i6= 4, i64) DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index d0814cb218..517a4500ae 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -306,10 +306,10 @@ /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) - F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_P, x1, cxgb, 0, IF_BFP) + F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_x, x1, cxgb, 0, IF_BFP) F(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0, IF_BFP) F(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, new, f1, cdgb, 0, IF_BFP) - F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_P, x1, cxgb, 0, IF_BFP) + F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_x, x1, cxgb, 0, IF_BFP) /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) @@ -320,10 +320,10 @@ /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) - F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_x, x1, cxlgb, 0, IF_BFP) F(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0, IF_BFP) F(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, new, f1, cdlgb, 0, IF_BFP) - F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_x, x1, cxlgb, 0, IF_BFP) =20 /* CONVERT UTF-8 TO UTF-16 */ D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12) @@ -597,15 +597,15 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_P, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) =20 /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) - F(0xb305, LXDBR, RRE, Z, 0, f2, new_P, x1, lxdb, 0, IF_BFP) - F(0xb306, LXEBR, RRE, Z, 0, e2, new_P, x1, lxeb, 0, IF_BFP) + F(0xb305, LXDBR, RRE, Z, 0, f2, new_x, x1, lxdb, 0, IF_BFP) + F(0xb306, LXEBR, RRE, Z, 0, e2, new_x, x1, lxeb, 0, IF_BFP) F(0xed04, LDEB, RXE, Z, 0, m2_32u, new, f1, ldeb, 0, IF_BFP) - F(0xed05, LXDB, RXE, Z, 0, m2_64, new_P, x1, lxdb, 0, IF_BFP) - F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_P, x1, lxeb, 0, IF_BFP) + F(0xed05, LXDB, RXE, Z, 0, m2_64, new_x, x1, lxdb, 0, IF_BFP) + F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_x, x1, lxeb, 0, IF_BFP) F(0xb324, LDER, RXE, Z, 0, e2, new, f1, lde, 0, IF_AFP1) F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_P, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) =20 diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index be80b2373c..13be44499b 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -34,7 +34,10 @@ #define HELPER_LOG(x...) #endif =20 -#define RET128(F) (env->retxl =3D F.low, F.high) +static inline Int128 RET128(float128 f) +{ + return int128_make128(f.low, f.high); +} =20 uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { @@ -224,7 +227,7 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP addition */ -uint64_t HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_add(make_float128(ah, al), @@ -251,7 +254,7 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP subtraction */ -uint64_t HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_sub(make_float128(ah, al), @@ -278,7 +281,7 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP division */ -uint64_t HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_div(make_float128(ah, al), @@ -314,7 +317,7 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP multiplication */ -uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_mul(make_float128(ah, al), @@ -325,8 +328,7 @@ uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, u= int64_t al, } =20 /* 128/64-bit FP multiplication */ -uint64_t HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t f2) +Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t= f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); ret =3D float128_mul(make_float128(ah, al), ret, &env->fpu_status); @@ -355,7 +357,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, = uint64_t al, } =20 /* convert 64-bit float to 128-bit float */ -uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -363,7 +365,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) } =20 /* convert 32-bit float to 128-bit float */ -uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -486,7 +488,7 @@ uint64_t HELPER(cdgb)(CPUS390XState *env, int64_t v2, u= int32_t m34) } =20 /* convert 64-bit int to 128-bit float */ -uint64_t HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) +Int128 HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D int64_to_float128(v2, &env->fpu_status); @@ -519,7 +521,7 @@ uint64_t HELPER(cdlgb)(CPUS390XState *env, uint64_t v2,= uint32_t m34) } =20 /* convert 64-bit uint to 128-bit float */ -uint64_t HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) +Int128 HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D uint64_to_float128(v2, &env->fpu_status); @@ -748,8 +750,7 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2, = uint32_t m34) } =20 /* round to integer 128-bit */ -uint64_t HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t= m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D float128_round_to_int(make_float128(ah, al), @@ -890,7 +891,7 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } =20 /* square root 128-bit */ -uint64_t HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float128 ret =3D float128_sqrt(make_float128(ah, al), &env->fpu_status= ); handle_exceptions(env, false, GETPC()); diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d25b6f3c03..0a750a5467 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1103,6 +1103,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; + TCGv_i128 out_128; } DisasOps; =20 /* Instructions can place constraints on their operands, raising specifica= tion @@ -1461,8 +1462,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -1995,9 +1995,8 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } =20 @@ -2032,9 +2031,8 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxlgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } =20 @@ -2447,8 +2445,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -2553,8 +2550,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34); - return_low128(o->out2); + gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2866,15 +2862,13 @@ static DisasJumpType op_lexb(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o) { - gen_helper_lxdb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxdb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o) { - gen_helper_lxeb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxeb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } =20 @@ -3590,15 +3584,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); return DISAS_NEXT; } =20 @@ -4063,8 +4055,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -4082,8 +4073,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -5395,6 +5385,14 @@ static void prep_new_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_new_P 0 =20 +static void prep_new_x(DisasContext *s, DisasOps *o) +{ + o->out =3D tcg_temp_new_i64(); + o->out2 =3D tcg_temp_new_i64(); + o->out_128 =3D tcg_temp_new_i128(); +} +#define SPEC_prep_new_x 0 + static void prep_r1(DisasContext *s, DisasOps *o) { o->out =3D regs[get_field(s, r1)]; @@ -5411,11 +5409,12 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even =20 -/* Whenever we need x1 in addition to other inputs, we'll load it to out/o= ut2 */ static void prep_x1(DisasContext *s, DisasOps *o) { o->out =3D load_freg(get_field(s, r1)); o->out2 =3D load_freg(get_field(s, r1) + 2); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); } #define SPEC_prep_x1 SPEC_r1_f128 =20 @@ -5513,6 +5512,8 @@ static void wout_f1(DisasContext *s, DisasOps *o) static void wout_x1(DisasContext *s, DisasOps *o) { int f1 =3D get_field(s, r1); + + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); } @@ -6588,7 +6589,9 @@ static DisasJumpType translate_one(CPUS390XState *env= , DisasContext *s) if (o.addr1) { tcg_temp_free_i64(o.addr1); } - + if (o.out_128) { + tcg_temp_free_i128(o.out_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708051; cv=none; d=zohomail.com; s=zohoarc; b=YA3ibzN9EA9rQ/Y7t+TSJZJ7kgh2EBipO0Ss1o0+YuxruvrupZQCZgyZKXRb69k3BV996vbmafDBlcnzxDFLhgsNM8CZGVgjFSH1sNg7DXxNZ6P5SLEoUB0h4CYNHvV2GnE94NmpR8fofSuDP/ydWLxp6bPAEMKGVPwB2F7ad/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708051; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g4lktU2LOvDtpiDVqeA4HMqijIEjkekItfgcLpT3plU=; b=axEWbyJXKSpVyuXPNk9ye1wro5Gb7x77655ZcIlMNJFqYfSRLZoroiVB8tloO0UZLZk0DLlb0S6TXyyTcTCsZcBT42YrjIX9mNwyO/jn3br7+YrVsDtthOILHbuy2zKLUU5KOA/ejDO9P6fZTtP5rghtyg6NCUGR1tLcwWoq07Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167470805185365.55060433594622; Wed, 25 Jan 2023 20:40:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2u-0000VP-Oo; Wed, 25 Jan 2023 23:39:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2j-0000OF-Te for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:22 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2g-0004Vr-MV for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:21 -0500 Received: by mail-pj1-x1035.google.com with SMTP id t12-20020a17090aae0c00b00229f4cff534so5122982pjq.1 for ; Wed, 25 Jan 2023 20:39:17 -0800 (PST) Received: from stoup.. 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Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/helper.h | 32 ++++++------ target/s390x/tcg/insn-data.h.inc | 30 +++++------ target/s390x/tcg/fpu_helper.c | 88 ++++++++++++++------------------ target/s390x/tcg/translate.c | 76 ++++++++++++++++++--------- 4 files changed, 121 insertions(+), 105 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index d40aeb471f..bccd3bfca6 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -41,55 +41,55 @@ DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(axb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(sxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(dxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(mxb, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(mxdb, TCG_CALL_NO_WG, i128, env, i128, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(ldxb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(lexb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(cdb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(cxb, TCG_CALL_NO_WG_SE, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(cxb, TCG_CALL_NO_WG_SE, i32, env, i128, i128) DEF_HELPER_FLAGS_3(keb, TCG_CALL_NO_WG, i32, env, i64, i64) DEF_HELPER_FLAGS_3(kdb, TCG_CALL_NO_WG, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(kxb, TCG_CALL_NO_WG, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(kxb, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_3(cgeb, i64, env, i64, i32) DEF_HELPER_3(cgdb, i64, env, i64, i32) -DEF_HELPER_4(cgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cgxb, i64, env, i128, i32) DEF_HELPER_3(cfeb, i64, env, i64, i32) DEF_HELPER_3(cfdb, i64, env, i64, i32) -DEF_HELPER_4(cfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cfxb, i64, env, i128, i32) DEF_HELPER_3(clgeb, i64, env, i64, i32) DEF_HELPER_3(clgdb, i64, env, i64, i32) -DEF_HELPER_4(clgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clgxb, i64, env, i128, i32) DEF_HELPER_3(clfeb, i64, env, i64, i32) DEF_HELPER_3(clfdb, i64, env, i64, i32) -DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clfxb, i64, env, i128, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(fixb, TCG_CALL_NO_WG, i128, env, i128, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i128, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) +DEF_HELPER_FLAGS_2(sqxb, TCG_CALL_NO_WG, i128, env, i128) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 517a4500ae..893f4b48db 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -34,7 +34,7 @@ C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64) F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP) F(0xb31a, ADBR, RRE, Z, f1, f2, new, f1, adb, f64, IF_BFP) - F(0xb34a, AXBR, RRE, Z, x2h, x2l, x1, x1, axb, f128, IF_BFP) + F(0xb34a, AXBR, RRE, Z, x1, x2, new_x, x1, axb, f128, IF_BFP) F(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32, IF_BFP) F(0xed1a, ADB, RXE, Z, f1, m2_64, new, f1, adb, f64, IF_BFP) /* ADD HIGH */ @@ -172,13 +172,13 @@ C(0xe330, CGF, RXY_a, Z, r1_o, m2_32s, 0, 0, 0, cmps64) F(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0, IF_BFP) F(0xb319, CDBR, RRE, Z, f1, f2, 0, 0, cdb, 0, IF_BFP) - F(0xb349, CXBR, RRE, Z, x2h, x2l, x1, 0, cxb, 0, IF_BFP) + F(0xb349, CXBR, RRE, Z, x1, x2, 0, 0, cxb, 0, IF_BFP) F(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0, IF_BFP) F(0xed19, CDB, RXE, Z, f1, m2_64, 0, 0, cdb, 0, IF_BFP) /* COMPARE AND SIGNAL */ F(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0, IF_BFP) F(0xb318, KDBR, RRE, Z, f1, f2, 0, 0, kdb, 0, IF_BFP) - F(0xb348, KXBR, RRE, Z, x2h, x2l, x1, 0, kxb, 0, IF_BFP) + F(0xb348, KXBR, RRE, Z, x1, x2, 0, 0, kxb, 0, IF_BFP) F(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0, IF_BFP) F(0xed18, KDB, RXE, Z, f1, m2_64, 0, 0, kdb, 0, IF_BFP) /* COMPARE IMMEDIATE */ @@ -299,10 +299,10 @@ /* CONVERT TO FIXED */ F(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0, IF_BFP) F(0xb399, CFDBR, RRF_e, Z, 0, f2, new, r1_32, cfdb, 0, IF_BFP) - F(0xb39a, CFXBR, RRF_e, Z, x2h, x2l, new, r1_32, cfxb, 0, IF_BFP) + F(0xb39a, CFXBR, RRF_e, Z, 0, x2, new, r1_32, cfxb, 0, IF_BFP) F(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0, IF_BFP) F(0xb3a9, CGDBR, RRF_e, Z, 0, f2, r1, 0, cgdb, 0, IF_BFP) - F(0xb3aa, CGXBR, RRF_e, Z, x2h, x2l, r1, 0, cgxb, 0, IF_BFP) + F(0xb3aa, CGXBR, RRF_e, Z, 0, x2, r1, 0, cgxb, 0, IF_BFP) /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) @@ -313,10 +313,10 @@ /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) - F(0xb39e, CLFXBR, RRF_e, FPE, x2h, x2l, new, r1_32, clfxb, 0, IF_BFP) + F(0xb39e, CLFXBR, RRF_e, FPE, 0, x2, new, r1_32, clfxb, 0, IF_BFP) F(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0, IF_BFP) F(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2, r1, 0, clgdb, 0, IF_BFP) - F(0xb3ae, CLGXBR, RRF_e, FPE, x2h, x2l, r1, 0, clgxb, 0, IF_BFP) + F(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2, r1, 0, clgxb, 0, IF_BFP) /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) @@ -343,7 +343,7 @@ C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, = 0) F(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0, IF_BFP) F(0xb31d, DDBR, RRE, Z, f1, f2, new, f1, ddb, 0, IF_BFP) - F(0xb34d, DXBR, RRE, Z, x2h, x2l, x1, x1, dxb, 0, IF_BFP) + F(0xb34d, DXBR, RRE, Z, x1, x2, new_x, x1, dxb, 0, IF_BFP) F(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0, IF_BFP) F(0xed1d, DDB, RXE, Z, f1, m2_64, new, f1, ddb, 0, IF_BFP) /* DIVIDE LOGICAL */ @@ -597,7 +597,7 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, 0, x2, new_x, x1, fixb, 0, IF_BFP) =20 /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) @@ -610,8 +610,8 @@ F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ F(0xb344, LEDBR, RRF_e, Z, 0, f2, new, e1, ledb, 0, IF_BFP) - F(0xb345, LDXBR, RRF_e, Z, x2h, x2l, new, f1, ldxb, 0, IF_BFP) - F(0xb346, LEXBR, RRF_e, Z, x2h, x2l, new, e1, lexb, 0, IF_BFP) + F(0xb345, LDXBR, RRF_e, Z, 0, x2, new, f1, ldxb, 0, IF_BFP) + F(0xb346, LEXBR, RRF_e, Z, 0, x2, new, e1, lexb, 0, IF_BFP) =20 /* LOAD MULTIPLE */ C(0x9800, LM, RS_a, Z, 0, a2, 0, 0, lm32, 0) @@ -666,7 +666,7 @@ C(0xe384, MG, RXY_a, MIE2,r1p1_o, m2_64, r1_P, 0, muls128, 0) F(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0, IF_BFP) F(0xb31c, MDBR, RRE, Z, f1, f2, new, f1, mdb, 0, IF_BFP) - F(0xb34c, MXBR, RRE, Z, x2h, x2l, x1, x1, mxb, 0, IF_BFP) + F(0xb34c, MXBR, RRE, Z, x1, x2, new_x, x1, mxb, 0, IF_BFP) F(0xb30c, MDEBR, RRE, Z, f1, e2, new, f1, mdeb, 0, IF_BFP) F(0xb307, MXDBR, RRE, Z, 0, f2, x1, x1, mxdb, 0, IF_BFP) F(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0, IF_BFP) @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, 0, x2, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) =20 @@ -913,7 +913,7 @@ C(0xe319, SGF, RXY_a, Z, r1, m2_32s, r1, 0, sub, subs64) F(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32, IF_BFP) F(0xb31b, SDBR, RRE, Z, f1, f2, new, f1, sdb, f64, IF_BFP) - F(0xb34b, SXBR, RRE, Z, x2h, x2l, x1, x1, sxb, f128, IF_BFP) + F(0xb34b, SXBR, RRE, Z, x1, x2, new_x, x1, sxb, f128, IF_BFP) F(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32, IF_BFP) F(0xed1b, SDB, RXE, Z, f1, m2_64, new, f1, sdb, f64, IF_BFP) /* SUBTRACT HALFWORD */ @@ -957,7 +957,7 @@ /* TEST DATA CLASS */ F(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0, IF_BFP) F(0xed11, TCDB, RXE, Z, f1, a2, 0, 0, tcdb, 0, IF_BFP) - F(0xed12, TCXB, RXE, Z, 0, a2, x1, 0, tcxb, 0, IF_BFP) + F(0xed12, TCXB, RXE, Z, x1, a2, 0, 0, tcxb, 0, IF_BFP) =20 /* TEST DECIMAL */ C(0xebc0, TP, RSL, E2, la1, 0, 0, 0, tp, 0) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 13be44499b..0bdab5bcf7 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -39,6 +39,11 @@ static inline Int128 RET128(float128 f) return int128_make128(f.low, f.high); } =20 +static inline float128 ARG128(Int128 i) +{ + return make_float128(int128_gethi(i), int128_getlo(i)); +} + uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { uint8_t s390_exc =3D 0; @@ -227,12 +232,9 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP addition */ -Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(axb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_add(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_add(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -254,12 +256,9 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP subtraction */ -Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(sxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_sub(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_sub(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -281,12 +280,9 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP division */ -Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_div(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_div(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -317,21 +313,18 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1= , uint64_t f2) } =20 /* 128-bit FP multiplication */ -Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(mxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_mul(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_mul(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } =20 /* 128/64-bit FP multiplication */ -Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t= f2) +Int128 HELPER(mxdb)(CPUS390XState *env, Int128 a, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); - ret =3D float128_mul(make_float128(ah, al), ret, &env->fpu_status); + ret =3D float128_mul(ARG128(a), ret, &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -345,11 +338,10 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) } =20 /* convert 128-bit float to 64-bit float */ -uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(ldxb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float64 ret =3D float128_to_float64(make_float128(ah, al), &env->fpu_s= tatus); + float64 ret =3D float128_to_float64(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -384,11 +376,10 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2= , uint32_t m34) } =20 /* convert 128-bit float to 32-bit float */ -uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(lexb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float32 ret =3D float128_to_float32(make_float128(ah, al), &env->fpu_s= tatus); + float32 ret =3D float128_to_float32(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -412,11 +403,9 @@ uint32_t HELPER(cdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP compare */ -uint32_t HELPER(cxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(cxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp =3D float128_compare_quiet(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp =3D float128_compare_quiet(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -564,10 +553,10 @@ uint64_t HELPER(cgdb)(CPUS390XState *env, uint64_t v2= , uint32_t m34) } =20 /* convert 128-bit float to 64-bit int */ -uint64_t HELPER(cgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t= m34) +uint64_t HELPER(cgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); int64_t ret =3D float128_to_int64(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -613,10 +602,10 @@ uint64_t HELPER(cfdb)(CPUS390XState *env, uint64_t v2= , uint32_t m34) } =20 /* convert 128-bit float to 32-bit int */ -uint64_t HELPER(cfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t= m34) +uint64_t HELPER(cfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); int32_t ret =3D float128_to_int32(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -662,10 +651,10 @@ uint64_t HELPER(clgdb)(CPUS390XState *env, uint64_t v= 2, uint32_t m34) } =20 /* convert 128-bit float to 64-bit uint */ -uint64_t HELPER(clgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_= t m34) +uint64_t HELPER(clgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); uint64_t ret =3D float128_to_uint64(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -711,10 +700,10 @@ uint64_t HELPER(clfdb)(CPUS390XState *env, uint64_t v= 2, uint32_t m34) } =20 /* convert 128-bit float to 32-bit uint */ -uint64_t HELPER(clfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_= t m34) +uint64_t HELPER(clfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); uint32_t ret =3D float128_to_uint32(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -750,11 +739,10 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2= , uint32_t m34) } =20 /* round to integer 128-bit */ -Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t= m34) +Int128 HELPER(fixb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 ret =3D float128_round_to_int(make_float128(ah, al), - &env->fpu_status); + float128 ret =3D float128_round_to_int(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -778,11 +766,9 @@ uint32_t HELPER(kdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP compare and signal */ -uint32_t HELPER(kxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(kxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp =3D float128_compare(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp =3D float128_compare(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -869,9 +855,9 @@ uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, = uint64_t m2) } =20 /* test data class 128-bit */ -uint32_t HELPER(tcxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64= _t m2) +uint32_t HELPER(tcxb)(CPUS390XState *env, Int128 a, uint64_t m2) { - return (m2 & float128_dcmask(env, make_float128(ah, al))) !=3D 0; + return (m2 & float128_dcmask(env, ARG128(a))) !=3D 0; } =20 /* square root 32-bit */ @@ -891,9 +877,9 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } =20 /* square root 128-bit */ -Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, Int128 a) { - float128 ret =3D float128_sqrt(make_float128(ah, al), &env->fpu_status= ); + float128 ret =3D float128_sqrt(ARG128(a), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0a750a5467..d422a1e62b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -305,6 +305,18 @@ static TCGv_i64 load_freg32_i64(int reg) return r; } =20 +static TCGv_i128 load_freg_128(int reg) +{ + TCGv_i64 h =3D load_freg(reg); + TCGv_i64 l =3D load_freg(reg + 2); + TCGv_i128 r =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(r, l, h); + tcg_temp_free_i64(h); + tcg_temp_free_i64(l); + return r; +} + static void store_reg(int reg, TCGv_i64 v) { tcg_gen_mov_i64(regs[reg], v); @@ -1103,7 +1115,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; - TCGv_i128 out_128; + TCGv_i128 out_128, in1_128, in2_128; } DisasOps; =20 /* Instructions can place constraints on their operands, raising specifica= tion @@ -1462,7 +1474,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_axb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -1778,7 +1790,7 @@ static DisasJumpType op_cdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_cxb(DisasContext *s, DisasOps *o) { - gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_cxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -1841,7 +1853,7 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1880,7 +1892,7 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1919,7 +1931,7 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1958,7 +1970,7 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -2445,7 +2457,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_dxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -2550,7 +2562,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); + gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2769,7 +2781,7 @@ static DisasJumpType op_kdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_kxb(DisasContext *s, DisasOps *o) { - gen_helper_kxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_kxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -2843,7 +2855,7 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2855,7 +2867,7 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -3584,13 +3596,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_mxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); + gen_helper_mxdb(o->out_128, cpu_env, o->in1_128, o->in2); return DISAS_NEXT; } =20 @@ -4055,7 +4067,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_sxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -4073,7 +4085,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); + gen_helper_sqxb(o->out_128, cpu_env, o->in2_128); return DISAS_NEXT; } =20 @@ -4852,7 +4864,7 @@ static DisasJumpType op_tcdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o) { - gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2); + gen_helper_tcxb(cc_op, cpu_env, o->in1_128, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -5387,8 +5399,6 @@ static void prep_new_P(DisasContext *s, DisasOps *o) =20 static void prep_new_x(DisasContext *s, DisasOps *o) { - o->out =3D tcg_temp_new_i64(); - o->out2 =3D tcg_temp_new_i64(); o->out_128 =3D tcg_temp_new_i128(); } #define SPEC_prep_new_x 0 @@ -5411,10 +5421,7 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) =20 static void prep_x1(DisasContext *s, DisasOps *o) { - o->out =3D load_freg(get_field(s, r1)); - o->out2 =3D load_freg(get_field(s, r1) + 2); - o->out_128 =3D tcg_temp_new_i128(); - tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); + o->out_128 =3D load_freg_128(get_field(s, r1)); } #define SPEC_prep_x1 SPEC_r1_f128 =20 @@ -5513,6 +5520,11 @@ static void wout_x1(DisasContext *s, DisasOps *o) { int f1 =3D get_field(s, r1); =20 + /* Split out_128 into out+out2 for cout_f128. */ + tcg_debug_assert(o->out =3D=3D NULL); + o->out =3D tcg_temp_new_i64(); + o->out2 =3D tcg_temp_new_i64(); + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); @@ -5755,6 +5767,12 @@ static void in1_f1(DisasContext *s, DisasOps *o) } #define SPEC_in1_f1 0 =20 +static void in1_x1(DisasContext *s, DisasOps *o) +{ + o->in1_128 =3D load_freg_128(get_field(s, r1)); +} +#define SPEC_in1_x1 SPEC_r1_f128 + /* Load the high double word of an extended (128-bit) format FP number */ static void in1_x2h(DisasContext *s, DisasOps *o) { @@ -5964,6 +5982,12 @@ static void in2_f2(DisasContext *s, DisasOps *o) } #define SPEC_in2_f2 0 =20 +static void in2_x2(DisasContext *s, DisasOps *o) +{ + o->in2_128 =3D load_freg_128(get_field(s, r2)); +} +#define SPEC_in2_x2 SPEC_r2_f128 + /* Load the low double word of an extended (128-bit) format FP number */ static void in2_x2l(DisasContext *s, DisasOps *o) { @@ -6592,6 +6616,12 @@ static DisasJumpType translate_one(CPUS390XState *en= v, DisasContext *s) if (o.out_128) { tcg_temp_free_i128(o.out_128); } + if (o.in1_128) { + tcg_temp_free_i128(o.in1_128); + } + if (o.in2_128) { + tcg_temp_free_i128(o.in2_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708188; cv=none; d=zohomail.com; s=zohoarc; b=BX24xyN1ZRQwP0WoUvkpSESiNEzuXapskeLqUN51tSt0pr5vO+uo0VICwerJ2B2sppv6+u8VM+V8MpMMz2B/bCM/qYmH/E7EWRu9aUFfyDbPFWIGiiI9IWpsiG0Kj8CwI61kpDyh1qSh1zfi4QVuTO5Bud5vTzQMdKH+gxeSrMU= ARC-Message-Signature: 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708189953100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/helper.h | 2 -- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/mem_helper.c | 52 --------------------------- target/s390x/tcg/translate.c | 60 ++++++++++++++++++++------------ 4 files changed, 38 insertions(+), 78 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bccd3bfca6..341bc51ec2 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -35,8 +35,6 @@ DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i128, env, i64, i32) -DEF_HELPER_4(cdsg, void, env, i64, i32, i32) -DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 893f4b48db..ea34b4a277 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -276,7 +276,7 @@ /* COMPARE DOUBLE AND SWAP */ D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) - C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) + C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, r1_D64, r1_D64, cdsg, 0) /* COMPARE AND SWAP AND STORE */ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) =20 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 49969abda7..d6725fd18c 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1771,58 +1771,6 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r= 1, uint32_t r2, return cc; } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra =3D GETPC(); - Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); - Int128 oldv; - uint64_t oldh, oldl; - bool fail; - - check_alignment(env, addr, 16, ra); - - oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); - oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); - - oldv =3D int128_make128(oldl, oldh); - fail =3D !int128_eq(oldv, cmpv); - if (fail) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); - - env->cc_op =3D fail; - env->regs[r1] =3D int128_gethi(oldv); - env->regs[r1 + 1] =3D int128_getlo(oldv); -} - -void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra =3D GETPC(); - Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); - int mem_idx; - MemOpIdx oi; - Int128 oldv; - bool fail; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - fail =3D !int128_eq(oldv, cmpv); - - env->cc_op =3D fail; - env->regs[r1] =3D int128_gethi(oldv); - env->regs[r1 + 1] =3D int128_getlo(oldv); -} - static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d422a1e62b..0dafa27dab 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2224,31 +2224,22 @@ static DisasJumpType op_cs(DisasContext *s, DisasOp= s *o) static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) { int r1 =3D get_field(s, r1); - int r3 =3D get_field(s, r3); - int d2 =3D get_field(s, d2); - int b2 =3D get_field(s, b2); - DisasJumpType ret =3D DISAS_NEXT; - TCGv_i64 addr; - TCGv_i32 t_r1, t_r3; =20 - /* Note that R1:R1+1 =3D expected value and R3:R3+1 =3D new value. */ - addr =3D get_address(s, 0, b2, d2); - t_r1 =3D tcg_const_i32(r1); - t_r3 =3D tcg_const_i32(r3); - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); - } else if (HAVE_CMPXCHG128) { - gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); - } else { - gen_helper_exit_atomic(cpu_env); - ret =3D DISAS_NORETURN; - } - tcg_temp_free_i64(addr); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r3); + /* Note out (R1:R1+1) =3D expected value and in2 (R3:R3+1) =3D new val= ue. */ + tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_1= 28, + get_mem_index(s), MO_BE | MO_128 | MO_ALIG= N); =20 - set_cc_static(s); - return ret; + /* + * Extract result into cc_dst:cc_src, compare vs the expected value + * in the as yet unmodified input registers, then update CC_OP. + */ + tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128); + tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]); + tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]); + tcg_gen_or_i64(cc_dst, cc_dst, cc_src); + set_cc_nz_u64(s, cc_dst); + + return DISAS_NEXT; } =20 static DisasJumpType op_csst(DisasContext *s, DisasOps *o) @@ -5419,6 +5410,14 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even =20 +static void prep_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 =3D get_field(s, r1); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]); +} +#define SPEC_prep_r1_D64 SPEC_r1_even + static void prep_x1(DisasContext *s, DisasOps *o) { o->out_128 =3D load_freg_128(get_field(s, r1)); @@ -5488,6 +5487,13 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) } #define SPEC_wout_r1_D32 SPEC_r1_even =20 +static void wout_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 =3D get_field(s, r1); + tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128); +} +#define SPEC_wout_r1_D64 SPEC_r1_even + static void wout_r3_P32(DisasContext *s, DisasOps *o) { int r3 =3D get_field(s, r3); @@ -5935,6 +5941,14 @@ static void in2_r3(DisasContext *s, DisasOps *o) } #define SPEC_in2_r3 0 =20 +static void in2_r3_D64(DisasContext *s, DisasOps *o) +{ + int r3 =3D get_field(s, r3); + o->in2_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]); +} +#define SPEC_in2_r3_D64 SPEC_r3_even + static void in2_r3_sr32(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674707993; cv=none; d=zohomail.com; s=zohoarc; b=mL5eoqOm1xq7OPsv4Dh8ZDThMr6q92iXBLjzpqI8nKO7wCrp/mKKjWVHOqT7PxzBXGv+rnOmqXIGxo2Wt9/ZzPWtk5FL/VxMh2Jh/6eNty0lMXkF8YcA9CFG75gHo3p9wWaBayOj+UpdKd0O8lmOyql13TGnbFZmpnd3uZofUW0= ARC-Message-Signature: i=1; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ukwtjg9oIq7luK67vm6BnI743dBnzE6yf3C88tqi0lc=; b=O6uTIMBrP1eBuoMbTiV34z9pWKwJS8WeyOvvJCj8HO6jvxj8aPKrLeoieCr+aWfNUC kX1eU/PAlR6Y5S0NJaEufFEvwTpTSl/Lhnl2WmsQT9iDY7srxOc4GIxihwaGuGTXgkAt 7FG0kxjgocS9rifg1Q+wHvOpYWv1QEDYB4Rk+J2W8aL5kx73CxzSWH6Y8XWSC14gR/MD me0SfDlsKi09vgQuQhmr3KJQvTMwqKwzo3GQe2YXvTW+LXSnPDDEu9s0k9kR9MoqfzVK xSW5s1huqBDQaqnVaItlYe7rPb0Tjjz6XmzeJ8ebFlO3nwI74c3QrOwVdXMiHnKvBT52 8RAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ukwtjg9oIq7luK67vm6BnI743dBnzE6yf3C88tqi0lc=; b=grGg7B8tbeGm16d/BFGFO8STOrp+ya3831Pt2h4tE6HJ/xJfwU/82iIUSPvumrAZYa i9bgpC+Xy99DBg+iLAnCdwbo3mt1cdWxTL/DstHOVUKmc3ReXEp5GHAEuLquUpKCQedC l9NulSy5YafMt9bXLVfb53qR7MMRQtZJ8WeKZ9z54ymx5Nx7l3K+rxE1sr1Pc1uxZSTM M/d1ouVqWP38glae+ylI0sm2uoRPBAibeEhiiZ+Yx3leM3C68h0UfPIGyBzj5sXeqHnI EfJ6oKSnkYTShUq5WUa79Js7RMgo5hW93+gpzVs2dWR0nTygZLZuGxzaPQkhgjzUcPhC YEyg== X-Gm-Message-State: AO0yUKXrcVSP32gT4k0Ske8qnGINzpCi/njFkuw/y9fGMmNtwg1fRn7E KOfuLf9Y0IQtxMtS2UrwjnUV8l38JQIFI1gWm68= X-Google-Smtp-Source: AK7set+hMY2KbTRJGjNyUc7yo5UJFA/UTbFjvZXZjvzHwDg02UCV5mU6HdzDTw6vnXsZNpoVuYH3Uw== X-Received: by 2002:a17:90b:3b51:b0:22b:f24d:e83a with SMTP id ot17-20020a17090b3b5100b0022bf24de83amr825217pjb.12.1674707960634; Wed, 25 Jan 2023 20:39:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, David Hildenbrand , Ilya Leoshkevich Subject: [PATCH v5 33/36] target/s390x: Implement CC_OP_NZ in gen_op_calc_cc Date: Wed, 25 Jan 2023 18:38:21 -1000 Message-Id: <20230126043824.54819-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674707995153100002 Content-Type: text/plain; charset="utf-8" This case is trivial to implement inline. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- Cc: David Hildenbrand Cc: Ilya Leoshkevich --- target/s390x/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0dafa27dab..b8cb21c395 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -625,6 +625,9 @@ static void gen_op_calc_cc(DisasContext *s) /* env->cc_op already is the cc value */ break; case CC_OP_NZ: + tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0); + tcg_gen_extrl_i64_i32(cc_op, cc_dst); + break; case CC_OP_ABS_64: case CC_OP_NABS_64: case CC_OP_ABS_32: --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674707981; cv=none; d=zohomail.com; s=zohoarc; b=M8Nkk9NuOo7UB6fsUOFO22v3/ZcNE2fHkowY53Dx1E5Mx8E0tK0U2kcC0zewE8OrO5twbnwpLWYgOmbwDTFYOB1WJaEBh5EhCEtkBK1zlINkTRRh0/T1NEvb+2Rjkt1g+JMWG2u2HrCkx0GOp9LkF6czZ5bsWAJBdyfYnNeiKgk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674707981; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZnBSw+DizwOZo4UW4Jj6dd8GS0IvC1zlFir1RDsd6zE=; b=cgrhq6E6S1WiGziN3LcQCCehYg5lM6j9Fd3O762CuSUaCSB/3wuuKbxVAYIDOwQHhrFilp1/oog5ON3kMsJLQAsdmd5PJNWLxFco0VWdIm/fudeFeEmg0de60/rub/r1TZWlajLC06yFLfmwPSIPNOfrcgULWMJoDSEw4APUQMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167470798178295.1033271398893; Wed, 25 Jan 2023 20:39:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2u-0000VR-Oa; Wed, 25 Jan 2023 23:39:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2q-0000Sz-Do for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:28 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2o-0004XT-P6 for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:28 -0500 Received: by mail-pj1-x1030.google.com with SMTP id k10-20020a17090a590a00b0022ba875a1a4so4225116pji.3 for ; Wed, 25 Jan 2023 20:39:23 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZnBSw+DizwOZo4UW4Jj6dd8GS0IvC1zlFir1RDsd6zE=; b=qGESYRYhTD1fIaahtXNNzjF/OwKy2algwf1JQdYPLMoq4KCGNHxlLaIWCjUOEIaoif m4bLZASdzz7M77ynToDq46QKgActY3596RhT1+GeHtLoAFIL5YpAhhme6uiCXfsp5pBe VJWoXxOCTnlYh01/tO29NtuvgqFqgpvrBgzjrNMuC5CNkv1QVCCUw136jglLvpUFwdT8 3JWBINauzVurMbGmaO4maaVy5cniet7qlhMIfL4jhE7b7v8j6z8EYMZZAwuJOqv8Bsgq qLEjs/ZdJoYplJP8CTiUyi4GlFjrsukbn5Va6U4vGlEzGCbgAsJpMK7S+itR6Ril2R44 OSQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZnBSw+DizwOZo4UW4Jj6dd8GS0IvC1zlFir1RDsd6zE=; b=4JpyKE1W06NpWIuqhhIwZtmJfHca/t33bN8vgo9M8pF6WXDU2mba9WLiA0G5cMfg/5 Cpvs/N4RFhHNYPEMqbOvv4tPP7B7NjQm9oQLmSyZh/AiO5FX+ymuGHVmc1j98J6pcS0u ZL+uDy5pyrzYIC7RakI5auB657la04diAHwN15NsrCv69PwV9TM12d5prIePeRken5sV YdQiUeC0RUwAS5vVAKvtlic+siNOyyQhql0jbtZmQB08Zz2ooHsAKVjHKLLmCuuRZPHP Az2rm0yjOe0d0JfPuI2AtH5sZJINTa6fbXHzlVw6hsr2fNzY7Its0V9N3t3T334Mp265 SUMg== X-Gm-Message-State: AFqh2ko7b7GNdsAk3QIKCr4pDXPbmJXLqIrM2Pcu2HJwZmaLlM/aTmI/ 8LHKzdQQx+njZGdVwZ/rlnZfPGMppo4q8JHwDL0= X-Google-Smtp-Source: AMrXdXumbwGchRpC7VI4aOkCUNkyx6jMlvFyR/KAE21XIuGDjT/2AVg4AVw8i0s0r8tqtQKZIaQHlw== X-Received: by 2002:a17:90a:5793:b0:229:1f6d:47fc with SMTP id g19-20020a17090a579300b002291f6d47fcmr36238162pji.41.1674707962455; Wed, 25 Jan 2023 20:39:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Eduardo Habkost Subject: [PATCH v5 34/36] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Date: Wed, 25 Jan 2023 18:38:22 -1000 Message-Id: <20230126043824.54819-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674707983189100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/tcg/translate.c | 48 ++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e0b2a709a..a82131d635 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2993,6 +2993,34 @@ static void gen_sty_env_A0(DisasContext *s, int offs= et, bool align) #include "emit.c.inc" #include "decode-new.c.inc" =20 +static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg8b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} + +#ifdef TARGET_X86_64 +static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg16b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} +#endif + /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static bool disas_insn(DisasContext *s, CPUState *cpu) @@ -3844,28 +3872,14 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg16b(s, env, modrm); break; } -#endif =20 +#endif if (!(s->cpuid_features & CPUID_CX8)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg8b(s, env, modrm); break; =20 case 7: /* RDSEED */ --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708168; cv=none; d=zohomail.com; s=zohoarc; b=ifSZC7+K5wQ3G4cfAkfTOxwforqSup5S3EJC3DE9O/Ki7z5CiKzLu3wCo4JZgqfLVn1hG0s3ywF4ctubmToKXOlECxYiiSJb5TtX9jRVRxlypXv/FRyA1OB8FRPfD0I7+vWhSIOXAsa5uNzDQidHx00xUtZlVeYeqed4hGK2Vyo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708168; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ziBn/5+saVd4auHCBHIgshaqj52WwpIAD7oymg6iFS8=; b=g4n+pTKGHVCDx7SjM4ly13fePavJ77c7irUjOvjXIL99Z/iLMWGB4p0QOERuddxlB8Fo85/6LFYN+utGWpC0ZUM2ooZoX6y5aAU2rLloJtmzJN4I7nyDGMPB+HyVgcd42oVz7u6XTRnkVHxZgNc7S6kNcQgrpERgSd0RoYRJMrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708168521531.0302271617704; Wed, 25 Jan 2023 20:42:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2s-0000Ui-To; Wed, 25 Jan 2023 23:39:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2q-0000T6-Lh for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:28 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2o-0004Xc-Pq for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:28 -0500 Received: by mail-pj1-x1031.google.com with SMTP id k10-20020a17090a590a00b0022ba875a1a4so4225163pji.3 for ; Wed, 25 Jan 2023 20:39:24 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ziBn/5+saVd4auHCBHIgshaqj52WwpIAD7oymg6iFS8=; b=oiCibha8asbWTul49wn7BRlLamxTBA5+XtqZRILjOkb9H6+pdsmmWbv1qQJ5otCPkp RstmucFAs2NOz5eNXNedaEXL4eUuD7bcFvnHXzr23+olDRut4xtItLROQW38lANtLB3O RWrTKZPDXP5xD8DacIX6lNG9EL7iVmVMvuHIQao9CWBG7lYFfXmeLnf7l3LyJR1HdA3P NJKODvvyeO+jpfeQkAd7Ym8tWLyHBMUlWM0tKdeuVkoGWaJr1ow4S/U5t0xncRUjTRgb SziCXKIW6BviWOZxRZrE9+1OEg0zEDbVQ7XiwgGBtzVS8FSJNy/cii0Tat0gtzt0d7GL OEWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ziBn/5+saVd4auHCBHIgshaqj52WwpIAD7oymg6iFS8=; b=CclA30yWWAKLm6zoOt9isq8xdIZ5R8DRG6CjRycagWq9C/80XFgU+pnmsJXbelFnHZ 0ozIvT+ir6/rROfkl+icsq39eBog9DTkgoqGQtQZjiCgsjBU85KjX8TdFUm8Szl4gjwm pGtl2z3xMo6W5Kc+xjR/9JKjhFa7/2aBa0FuSH+fiwLDP6SIOsPBRAnz0PBOYhg90PSp nyCwhQw+X+PomGMg77U61b3wYCeo1/m8BRprJBdkX1Xgo/+cAa5J0U33JqRrmSqmvXNO Sswb4rrVGmsCXeh8MugwBa0wQYpIepRR4SwHzk+KiF6emtMcCWoY7h2OAIU58eqPCiJB U+ug== X-Gm-Message-State: AO0yUKX/mE1DbUUXxz3eT1jD6X+ySDu5fbbMmbOiwtvweZePioLAegMT eUl0CLlrr6Sgs1elyhvOlXDNJgV0znJHVa9n1T4= X-Google-Smtp-Source: AK7set8rlck0RpGYHeN8bYT6+PKqlj1K+DxmM1VBzpW35jfS/AoOatPNlGWmyDxAVRhjI7n7swjAmg== X-Received: by 2002:a17:90b:4c8d:b0:22c:43:714f with SMTP id my13-20020a17090b4c8d00b0022c0043714fmr6402115pjb.7.1674707964102; Wed, 25 Jan 2023 20:39:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Paolo Bonzini , Eduardo Habkost Subject: [PATCH v5 35/36] target/i386: Inline cmpxchg8b Date: Wed, 25 Jan 2023 18:38:23 -1000 Message-Id: <20230126043824.54819-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708169891100005 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Signed-off-by: Richard Henderson --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57 ------------------------------------ target/i386/tcg/translate.c | 54 ++++++++++++++++++++++++++++++---- 3 files changed, 49 insertions(+), 64 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index b7de5429ef..2df8049f91 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,8 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -DEF_HELPER_2(cmpxchg8b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg8b, void, env, tl) #ifdef TARGET_X86_64 DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e3cdafd2d4..814786bb87 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,63 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - oldv =3D cpu_ldq_data_ra(env, a0, ra); - newv =3D (cmpv =3D=3D oldv ? newv : oldv); - /* always do the store */ - cpu_stq_data_ra(env, a0, newv, ra); - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) -{ -#ifdef CONFIG_ATOMIC64 - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - { - uintptr_t ra =3D GETPC(); - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mem_idx); - oldv =3D cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); - } - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -#else - cpu_loop_exit_atomic(env_cpu(env), GETPC()); -#endif /* CONFIG_ATOMIC64 */ -} - #ifdef TARGET_X86_64 void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a82131d635..b542b084a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2995,15 +2995,59 @@ static void gen_sty_env_A0(DisasContext *s, int off= set, bool align) =20 static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) { + TCGv_i64 cmp, val, old; + TCGv Z; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i64(); + val =3D tcg_temp_new_i64(); + old =3D tcg_temp_new_i64(); + + /* Construct the comparison values from the register pair. */ + tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_= TEUQ); } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, + s->mem_index, MO_TEUQ); } - set_cc_op(s, CC_OP_EFLAGS); + tcg_temp_free_i64(val); + + /* Set tmp0 to match the required value of Z. */ + tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); + Z =3D tcg_temp_new(); + tcg_gen_trunc_i64_tl(Z, cmp); + tcg_temp_free_i64(cmp); + + /* + * Extract the result values for the register pair. + * For 32-bit, we may do this unconditionally, because on success (Z= =3D1), + * the old value matches the previous value in EDX:EAX. For x86_64, + * the store must be conditional, because we must leave the source + * registers unchanged on success, and zero-extend the writeback + * on failure (Z=3D0). + */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); + } else { + TCGv zero =3D tcg_constant_tl(0); + + tcg_gen_extr_i64_tl(s->T0, s->T1, old); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, + s->T0, cpu_regs[R_EAX]); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, + s->T1, cpu_regs[R_EDX]); + } + tcg_temp_free_i64(old); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); + tcg_temp_free(Z); } =20 #ifdef TARGET_X86_64 --=20 2.34.1 From nobody Tue May 14 11:28:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674708231; cv=none; d=zohomail.com; s=zohoarc; b=dNRTpLvEUKEW4VhNk5P5J4MgdvMV9Fe9gwbavxOzO02kc1xrXsVNv1KzPhmdR69gGPB+xsg35odED3N4H58jkEeJQyy9IgIq0e4NaW3BxUdiXGfJC+9LJtTZ/jyUaSxtWeD9cVT2rjJlQ+ZVir78fOyGMgaxQWxQ6V9n3p/bb2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674708231; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/wjq7xXevU0mmvHUtmHWv2FofdJ4SksIwuVkJSWY5CU=; b=DHN6eO6yRASuC53ZCFjl7P9Ceb6UQOUvrfss1iJWTK+nRDFetcDDP5Jc2wWhi0e735qlP+dQRvZPwHq+fo0I5TKAl4udDz7p+20xzC8mEuG5U8xrr/qh+jJOYQ8zm8XWAbCXJCnrsYFKAyn748/vnp/RyJlHJl0AbqzO8x/FlTA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674708231420674.504491081679; Wed, 25 Jan 2023 20:43:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pKu2v-0000W7-G1; Wed, 25 Jan 2023 23:39:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKu2s-0000U1-0u for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:30 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKu2p-0004Xg-36 for qemu-devel@nongnu.org; Wed, 25 Jan 2023 23:39:29 -0500 Received: by mail-pj1-x102e.google.com with SMTP id m7-20020a17090a71c700b0022c0c070f2eso3548220pjs.4 for ; Wed, 25 Jan 2023 20:39:26 -0800 (PST) Received: from stoup.. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id s62-20020a17090a69c400b00228e56d375asm233376pjj.33.2023.01.25.20.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 20:39:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/wjq7xXevU0mmvHUtmHWv2FofdJ4SksIwuVkJSWY5CU=; b=DXLBHfKVoFtECPDLg8hnNmvXIIatwduJN9Kr0uybHJ+LbRP3XhVUiJpyUDLz9CS23x yjgEfU6FPQR+ohVj1ozXrHpTdU7ot6MSwA3enbGqUH7p80a8I65QVgcwkbQFN/qoe7mi THDRIwWnmQ0+xMEfUnGDhYweXL2TA/KNEuL03lS0AK9LUD9qQXhWhUhJePwxb230n6J6 oexB2KWYEmxAVH3bEaHLu3Ikov6dmC/7kHCJAWEazVcQhCx7qW6gJkRw5mj3SkpFJIB9 T2HfwkpCiIf73brb2UC9Fsy0TBjLyMLttjYb/09w1QS4RyEB+hE1Wv3ZhJImOzpDozua 86VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/wjq7xXevU0mmvHUtmHWv2FofdJ4SksIwuVkJSWY5CU=; b=oKK/6KOLdcaTNI+i7PdMiut0sLwAZN3aMaxtlYpIk7Zp+dCsOYGuOKxEx4iCPKiR5B N4L1iivmSkkXLryhByfAeQFwxoSh5DUr9Wk8cPF/iyeRaGj+Btm9LJjvLEOZT1kRGdCW /7hWtNBiiHiruGIhTjkrqHxg1OaPA2FVA4wi2I3pw7h5o6xl2NyOCK0CB1USGP0B/lYq El2dScCmiGydER4kVS+S52AEsBMTtnjfFPMGaFyUrIupAt6no5QS+yERokr+mT8fsuGx wd/RFsNjFJ+37ZFY4qS5DXObzdwI1PA9CGuWnmln491mt45WP5fVKvF0goxeKTd+anuq EBIQ== X-Gm-Message-State: AFqh2kqpgCs9GiBo9vH/iDdGwcq7GBKHajTaIgxPF2IzQI+SefnvQIcN ACHBEnPyyYMeom1qAab6XJxNmPbNfVJe7u5bZ3E= X-Google-Smtp-Source: AMrXdXuGD73y22UhzEOx3kJLKOn06jZXzIn6wEx0h8dOtkXBxWNKLTuwkLp51ggLQhQLD3Wy8Ldl6Q== X-Received: by 2002:a17:90a:6545:b0:229:9b0a:360e with SMTP id f5-20020a17090a654500b002299b0a360emr37043993pjs.12.1674707965833; Wed, 25 Jan 2023 20:39:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, Paolo Bonzini , Eduardo Habkost Subject: [PATCH v5 36/36] target/i386: Inline cmpxchg16b Date: Wed, 25 Jan 2023 18:38:24 -1000 Message-Id: <20230126043824.54819-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126043824.54819-1-richard.henderson@linaro.org> References: <20230126043824.54819-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674708232106100001 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Signed-off-by: Richard Henderson --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69 ------------------------------------ target/i386/tcg/translate.c | 44 ++++++++++++++++++++--- 3 files changed, 39 insertions(+), 78 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 2df8049f91..e627a93107 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,10 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -#ifdef TARGET_X86_64 -DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg16b, void, env, tl) -#endif DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 814786bb87..3ef84e90d9 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,75 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -#ifdef TARGET_X86_64 -void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - Int128 oldv, cmpv, newv; - uint64_t o0, o1; - int eflags; - bool success; - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - o0 =3D cpu_ldq_data_ra(env, a0 + 0, ra); - o1 =3D cpu_ldq_data_ra(env, a0 + 8, ra); - - oldv =3D int128_make128(o0, o1); - success =3D int128_eq(oldv, cmpv); - if (!success) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra); - cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra); - - if (success) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, ra); - } else if (HAVE_CMPXCHG128) { - int eflags =3D cpu_cc_compute_all(env, CC_OP); - - Int128 cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); - - if (int128_eq(oldv, cmpv)) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; - } else { - cpu_loop_exit_atomic(env_cpu(env), ra); - } -} -#endif - void helper_boundw(CPUX86State *env, target_ulong a0, int v) { int low, high; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b542b084a6..9d9392b009 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3053,15 +3053,49 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) #ifdef TARGET_X86_64 static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) { + MemOp mop =3D MO_TE | MO_128 | MO_ALIGN; + TCGv_i64 t0, t1; + TCGv_i128 cmp, val; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mo= p); } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index,= mop); } - set_cc_op(s, CC_OP_EFLAGS); + + tcg_gen_extr_i128_i64(s->T0, s->T1, val); + tcg_temp_free_i128(cmp); + tcg_temp_free_i128(val); + + /* Determine success after the fact. */ + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); + tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); + tcg_gen_or_i64(t0, t0, t1); + tcg_temp_free_i64(t1); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); + tcg_temp_free_i64(t0); + + /* + * Extract the result values for the register pair. We may do this + * unconditionally, because on success (Z=3D1), the old value matches + * the previous value in RDX:RAX. + */ + tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); + tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); } #endif =20 --=20 2.34.1