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bh=xKXtZsO8lnptTaaBCHlOkSzR3qu9Uu3BLJo2fZPDBlk=; b=bLl8GCm6ED2zb52lxfKta47FAXt3IgLNe+khf8A0UsuQKaLUQ083yP+lf0vIkAjhSeh7DX 8p1AV6iEO8t8My4o3DIEIbe7dOrhfGc83t8NmPYelBQoRfpGv0BCqxguzOchaN/1PAwwsH 5kbmzKoB2FPp61DWq6DAYuskKW1etow= X-MC-Unique: F8V4-s62Oki-vjQXyp2L_Q-1 From: Markus Armbruster To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Daniel Henrique Barboza Subject: [PULL 12/12] include/hw/ppc include/hw/pci-host: Drop extra typedefs Date: Fri, 20 Jan 2023 08:01:22 +0100 Message-Id: <20230120070122.3982588-13-armbru@redhat.com> In-Reply-To: <20230120070122.3982588-1-armbru@redhat.com> References: <20230120070122.3982588-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1674198157011100003 PnvChip is typedef'ed in five places, and PnvPhb4PecState in two. Keep one, drop the others. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20221222104628.659681-5-armbru@redhat.com> --- hw/pci-host/pnv_phb.h | 2 +- include/hw/pci-host/pnv_phb3.h | 1 - include/hw/pci-host/pnv_phb4.h | 2 -- include/hw/ppc/pnv_core.h | 3 +-- include/hw/ppc/pnv_homer.h | 2 +- include/hw/ppc/pnv_lpc.h | 8 ++------ include/hw/ppc/pnv_xive.h | 7 +++---- 7 files changed, 8 insertions(+), 17 deletions(-) diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h index 58ebd6dd0f..eb429d529f 100644 --- a/hw/pci-host/pnv_phb.h +++ b/hw/pci-host/pnv_phb.h @@ -12,9 +12,9 @@ =20 #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" +#include "hw/ppc/pnv.h" #include "qom/object.h" =20 -typedef struct PnvChip PnvChip; typedef struct PnvPhb4PecState PnvPhb4PecState; =20 struct PnvPHB { diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index f791ebda9b..d62b3091ac 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -15,7 +15,6 @@ #include "hw/pci-host/pnv_phb.h" =20 typedef struct PnvPHB3 PnvPHB3; -typedef struct PnvChip PnvChip; =20 /* * PHB3 XICS Source for MSIs diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index b4f2b29fb5..1f3237c9d5 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -16,10 +16,8 @@ #include "hw/ppc/xive.h" #include "qom/object.h" =20 -typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; typedef struct PnvPHB4 PnvPHB4; -typedef struct PnvChip PnvChip; =20 /* * We have one such address space wrapper per possible device under diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c22eab2e1f..3d75706e95 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -22,14 +22,13 @@ =20 #include "hw/cpu/core.h" #include "target/ppc/cpu.h" +#include "hw/ppc/pnv.h" #include "qom/object.h" =20 #define TYPE_PNV_CORE "powernv-cpu-core" OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass, PNV_CORE) =20 -typedef struct PnvChip PnvChip; - struct PnvCore { /*< private >*/ CPUCore parent_obj; diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h index 07e8b19311..b1c5d498dc 100644 --- a/include/hw/ppc/pnv_homer.h +++ b/include/hw/ppc/pnv_homer.h @@ -39,7 +39,7 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER, struct PnvHomer { DeviceState parent; =20 - struct PnvChip *chip; + PnvChip *chip; MemoryRegion pba_regs; MemoryRegion regs; }; diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 001eee27d7..5d22c45570 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -21,6 +21,7 @@ #define PPC_PNV_LPC_H =20 #include "exec/memory.h" +#include "hw/ppc/pnv.h" #include "hw/qdev-core.h" =20 #define TYPE_PNV_LPC "pnv-lpc" @@ -93,13 +94,8 @@ struct PnvLpcClass { DeviceRealize parent_realize; }; =20 -/* - * Old compilers error on typdef forward declarations. Keep them happy. - */ -struct PnvChip; - ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); -int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset, +int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, uint64_t lpcm_size); =20 #endif /* PPC_PNV_LPC_H */ diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index b5d91505e5..9c48430ee4 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -10,12 +10,11 @@ #ifndef PPC_PNV_XIVE_H #define PPC_PNV_XIVE_H =20 +#include "hw/ppc/pnv.h" #include "hw/ppc/xive.h" #include "qom/object.h" #include "hw/ppc/xive2.h" =20 -struct PnvChip; - #define TYPE_PNV_XIVE "pnv-xive" OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass, PNV_XIVE) @@ -31,7 +30,7 @@ struct PnvXive { XiveRouter parent_obj; =20 /* Owning chip */ - struct PnvChip *chip; + PnvChip *chip; =20 /* XSCOM addresses giving access to the controller registers */ MemoryRegion xscom_regs; @@ -106,7 +105,7 @@ typedef struct PnvXive2 { Xive2Router parent_obj; =20 /* Owning chip */ - struct PnvChip *chip; + PnvChip *chip; =20 /* XSCOM addresses giving access to the controller registers */ MemoryRegion xscom_regs; --=20 2.39.0