From nobody Tue Feb 10 10:04:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1674157478; cv=none; d=zohomail.com; s=zohoarc; b=Fx7BGFwDKwuLLrJU5XXAqsCv/z8vQ0c02aH0H8RHBDKXDJbnM+sw3i2T0wSOZykfQLyoaVU7B1oAw8mPVpvskVqpNbic1dEglYtq6yz3IhhLipspiduwtS/3RiUDPHqi+rqbq+rukt8aN3gVTSH5dJTPoPpRC3T8nEBNT8/JPjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674157478; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X1RLMon7j9YAFv1oETJXMYMXKuoq8ZJkPa5qfG+nY+g=; b=AtjdAcKgDePnYYCRIWMGyPtH1Cd/GctH/UTTqvtAVQ9Y5HbFMz2ZUM7Bk+/geUtPi8a9ocRCihDsm/grcZ0Bl+m1Ci46RQIAvpe3Ctmk9LgqvKrlG+LlUNzWb5ITkHuMK4cOXOwC/UDG2NWUoGuV4PcECe88WSAISVScjdrpO6Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674157477790504.4634824119588; Thu, 19 Jan 2023 11:44:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIaSz-0002Tv-H7; Thu, 19 Jan 2023 14:20:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIaSp-0002NK-Eb for qemu-devel@nongnu.org; Thu, 19 Jan 2023 14:20:49 -0500 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIaSn-0007co-7X for qemu-devel@nongnu.org; Thu, 19 Jan 2023 14:20:43 -0500 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-15eec491b40so3664805fac.12 for ; Thu, 19 Jan 2023 11:20:40 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id t9-20020a056870f20900b0015f193c86d2sm9001128oao.6.2023.01.19.11.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 11:20:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X1RLMon7j9YAFv1oETJXMYMXKuoq8ZJkPa5qfG+nY+g=; b=R+rHbwMn+Ydj1T/R0lpdKX9M5pWyv2GC+FKyKHH4U6ME2foJR9aJ7TD/wyhNi9Md87 yaYTFvImlQURso7mObspNkWck+4bxWx+Y7vmDt/lihSFf4T7qU0aPrpQtnsw2yFFe2Nt FD6Ix9jB5JvBWkq2clrCV/yBwR98HX1SIAvX5gSwAQFQDDPx0HOmRFIyJNIrs0PSbvUK n33/+oSC6vDAbly2RdD5iDYtcnS0rAqiOHBjeFrDEsnk9M3O/mbthd7scEHcRksdHR8W pe24oo19fGd9Y5cDyrqWE3Pi+r5CfgNWn/ud80hbD7fDJt5mewR/qxlzdquTwBG2x8K2 Pabg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X1RLMon7j9YAFv1oETJXMYMXKuoq8ZJkPa5qfG+nY+g=; b=3n86Iyg6k6SWkwg2krspiBWmkKTHLRDMj2vahCm14nGDXZVGE4YtuSPZP0LfA1hr3g QETqh3HSKTBXcD/MH5my7j0WErRyl1xTf8mxleB7yrbr2aWRxew84jdDX4E1D0QcBdUb 7qthpipgRQVCqqcfMzvkVq0iVPc2roSXUQwEzQafTg23NjANHAq0lqKuW1+LhhgcShAR MoRccxY4O0zV63b8jletMktEt4kfVI2XIPi80vvBM5c3O78f+7C0LCalqsYCBZHa7VbN 5TLOQfqB3ddSNmmu3Qdj6z+LNjNxTpAbduegZr6bfGv20tippdlOe/Daz7gqOnC3wVWl G2DQ== X-Gm-Message-State: AFqh2kpz6MhEwS0z90eERN0vKQSgWMoALNUiOPUyOEt6+unubz5t/Si5 h0h/HwvBwmU9jLAGQZrSi+Z9xvotyeahQp3HltA= X-Google-Smtp-Source: AMrXdXvRF/sK2E92uEc/5EvYZUas9uLbx6TwTCw/0BI89ENj4tWsPHzUJU1DEWkeUE5cgR+JO+eO5g== X-Received: by 2002:a05:6870:c43:b0:151:fd0f:1b59 with SMTP id lf3-20020a0568700c4300b00151fd0f1b59mr17185444oab.5.1674156039722; Thu, 19 Jan 2023 11:20:39 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 5/7] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Date: Thu, 19 Jan 2023 16:17:26 -0300 Message-Id: <20230119191728.622081-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1674157480863100001 riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2688410fc5..1119f4ba22 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc =3D MACHINE(s); + int socket_count =3D riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; =20 *msi_m_phandle =3D (*phandle)++; *msi_s_phandle =3D (*phandle)++; imsic_cells =3D g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs =3D g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs =3D g_new0(uint32_t, socket_count * 4); =20 /* M-level IMSIC node */ for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const M= emMapEntry *memmap, imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + for (socket =3D 0; socket < socket_count; socket++) { imsic_addr =3D memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const M= emMapEntry *memmap, } imsic_guest_bits =3D imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + for (socket =3D 0; socket < socket_count; socket++) { imsic_addr =3D memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits= ", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, MachineState *mc =3D MACHINE(s); uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count =3D riscv_socket_count(mc); =20 qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, intc_phandles =3D g_new0(uint32_t, mc->smp.cpus); =20 phandle_pos =3D mc->smp.cpus; - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { phandle_pos -=3D s->soc[socket].num_harts; =20 clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, } =20 phandle_pos =3D mc->smp.cpus; - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { phandle_pos -=3D s->soc[socket].num_harts; =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, =20 g_free(intc_phandles); =20 - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + for (socket =3D 0; socket < socket_count; socket++) { if (socket =3D=3D 0) { *irq_mmio_phandle =3D xplic_phandles[socket]; *irq_virtio_phandle =3D xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap) =20 /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_= seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } =20 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1328,9 +1331,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count =3D riscv_socket_count(machine); =20 /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1338,7 +1342,7 @@ static void virt_machine_init(MachineState *machine) =20 /* Initialize sockets */ mmio_irqchip =3D virtio_irqchip =3D pcie_irqchip =3D NULL; - for (i =3D 0; i < riscv_socket_count(machine); i++) { + for (i =3D 0; i < socket_count; i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); exit(1); --=20 2.39.0