From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145626; cv=none; d=zohomail.com; s=zohoarc; b=TkiSkqdgvjXqmZTdW0Vdp0huwkJvsUDl5VanKTM2J2J+qrj6+WyJ/2vLai+idQWsMDomPNh59Cn0e57anaAnTcD29o+ZEpBi15qTWhdekb+srHhKJWRo1PU1mJwDBiX5O5JNhqfp4ssb8cUOrr2jcvRGn1YeNJVf7tnz1DLmpR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145626; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AYWDMTmY+SCzbBTfhDbUxfPgw9Xf88DejLV4GZrSQBc=; b=Ol8IHrgZfIHTRhvcOpf+9xaEse7me9oIqPFJrGRLSzd8VCNYfcXOY7SOhUc33z9Zj/f2jc4U/sXq1LGX6VibjTNwB6d7vdEcUbwpBURPuXm2YN3vkJ+AH9xtJE6M6q7MNBolR8qy9W0YKhVSNF1XHlPwQtNvpxojlUQmAf0Uk/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145626918175.48209504532701; Sat, 7 Jan 2023 18:40:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELYy-0004bg-GP; Sat, 07 Jan 2023 21:37:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELYw-0004ab-RL for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:30 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYq-0004Ur-VE for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:30 -0500 Received: by mail-pj1-x1030.google.com with SMTP id z9-20020a17090a468900b00226b6e7aeeaso5836961pjf.1 for ; Sat, 07 Jan 2023 18:37:24 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AYWDMTmY+SCzbBTfhDbUxfPgw9Xf88DejLV4GZrSQBc=; b=pLPuT5WYnfYC0HZG4mjD8WIko7UQ+srtvnZ/EiccQdvk17ChX1JQy1w72AdEHmv5QX gV1V3W7e4CV/xqypyVex8Faxl64GJNgPwdA5Ac3fpFDz/MN6434G5HmD+GVmNsikKyln r+5NZgYD7Nr90c8vN24QisRcP3Ky+7M2XR3e3mv50xX6VvivWiXauoVAPssseDpbXmuD /ktI4UsIWqvz2uErK1oOczcMImYGMOkKkGZe7yUJJgBupI6s/jstMRklaRLW1kwxQKMT 9rTdTHHwZ5qiPFHMH+FT3W8/2DiL6OZiIfMNWFOIV6BLawi7NzbN7S3fCZVmSqZWUHx2 0aNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AYWDMTmY+SCzbBTfhDbUxfPgw9Xf88DejLV4GZrSQBc=; b=m5whsSmcnvmFmfSMgaOIMNypaXQahNehWIO+1XVsiH2yBleJIbIxFfhWlFNhz9sE8I cYI3TNJZqXG+b5/3PjlEn3Em8ZMA8lBuCf9MkRqRwxMqCIWCZi3xwgmTlK/JRjEFbl44 kXHgtOqmHRvZAptEqtUIivaPzJTTRdudv+3nO2YVhyTV1Y87CudrCBeepz8sMTolwBBe bu67J8uTp8yev3vmqAs4kgQrVVJ378RmLUbkoF88b/vzR+K1JuzUF1X7sEsmGC3ziN6i bTk/sRAOJXyNLhDqIaIS0tlrdm33JRnJMydoGjZZEcMfp9vfEj6dy4g/lmLb9tAaTds5 Wv+Q== X-Gm-Message-State: AFqh2kosC9flmRzms8LPFHfPvPpWAnYoPR8lBIVaP5NtA+bqD4DaFZRa y8rj+61+xBBTaA0N8t+yiPyV+EGJgQrS0t/X X-Google-Smtp-Source: AMrXdXtcU2/5ET2pswa2iwJIb30/Jp+plIb9YuhEGBEJELjmTS74pvcgI+fKIRE1vAIrvjmPUpUhig== X-Received: by 2002:a17:903:186:b0:188:d2b3:26c1 with SMTP id z6-20020a170903018600b00188d2b326c1mr81236833plg.10.1673145442678; Sat, 07 Jan 2023 18:37:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 01/36] tcg: Define TCG_TYPE_I128 and related helper macros Date: Sat, 7 Jan 2023 18:36:44 -0800 Message-Id: <20230108023719.2466341-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145628391100007 Content-Type: text/plain; charset="utf-8" Begin staging in support for TCGv_i128 with Int128. Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/helper-head.h | 7 +++++++ include/tcg/tcg.h | 17 ++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index bc6698b19f..b8d1140dc7 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_i128 i128 #define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 @@ -40,6 +41,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_i128 Int128 #define dh_ctype_f16 uint32_t #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 @@ -71,6 +73,7 @@ #define dh_retvar_decl0_noreturn void #define dh_retvar_decl0_i32 TCGv_i32 retval #define dh_retvar_decl0_i64 TCGv_i64 retval +#define dh_retval_decl0_i128 TCGv_i128 retval #define dh_retvar_decl0_ptr TCGv_ptr retval #define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) =20 @@ -78,6 +81,7 @@ #define dh_retvar_decl_noreturn #define dh_retvar_decl_i32 TCGv_i32 retval, #define dh_retvar_decl_i64 TCGv_i64 retval, +#define dh_retvar_decl_i128 TCGv_i128 retval, #define dh_retvar_decl_ptr TCGv_ptr retval, #define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) =20 @@ -85,6 +89,7 @@ #define dh_retvar_noreturn NULL #define dh_retvar_i32 tcgv_i32_temp(retval) #define dh_retvar_i64 tcgv_i64_temp(retval) +#define dh_retvar_i128 tcgv_i128_temp(retval) #define dh_retvar_ptr tcgv_ptr_temp(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) =20 @@ -95,6 +100,7 @@ #define dh_typecode_i64 4 #define dh_typecode_s64 5 #define dh_typecode_ptr 6 +#define dh_typecode_i128 7 #define dh_typecode_int dh_typecode_s32 #define dh_typecode_f16 dh_typecode_i32 #define dh_typecode_f32 dh_typecode_i32 @@ -104,6 +110,7 @@ =20 #define dh_callflag_i32 0 #define dh_callflag_i64 0 +#define dh_callflag_i128 0 #define dh_callflag_ptr 0 #define dh_callflag_void 0 #define dh_callflag_noreturn TCG_CALL_NO_RETURN diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b949d75fdd..7d346192ca 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -277,6 +277,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_I128, =20 TCG_TYPE_V64, TCG_TYPE_V128, @@ -358,13 +359,14 @@ typedef tcg_target_ulong TCGArg; in tcg/README. Target CPU front-end code uses these types to deal with TCG variables as it emits TCG code via the tcg_gen_* functions. They come in several flavours: - * TCGv_i32 : 32 bit integer type - * TCGv_i64 : 64 bit integer type - * TCGv_ptr : a host pointer type - * TCGv_vec : a host vector type; the exact size is not exposed - to the CPU front-end code. - * TCGv : an integer type the same size as target_ulong - (an alias for either TCGv_i32 or TCGv_i64) + * TCGv_i32 : 32 bit integer type + * TCGv_i64 : 64 bit integer type + * TCGv_i128 : 128 bit integer type + * TCGv_ptr : a host pointer type + * TCGv_vec : a host vector type; the exact size is not exposed + to the CPU front-end code. + * TCGv : an integer type the same size as target_ulong + (an alias for either TCGv_i32 or TCGv_i64) The compiler's type checking will complain if you mix them up and pass the wrong sized TCGv to a function. =20 @@ -384,6 +386,7 @@ typedef tcg_target_ulong TCGArg; =20 typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; +typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145903631517.6675016820922; Sat, 7 Jan 2023 18:45:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZ1-0004e7-5Q; Sat, 07 Jan 2023 21:37:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELYz-0004cu-Pq for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:33 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYr-0004VI-5g for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:33 -0500 Received: by mail-pj1-x1032.google.com with SMTP id z9-20020a17090a468900b00226b6e7aeeaso5836979pjf.1 for ; Sat, 07 Jan 2023 18:37:24 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uy+1LYtKetQWFHYH8PaN7/XbqnFh4isIp+PwWLyalNo=; b=gTpYFrptaAB6DVGm8liAVvYlvcGaeThZF2mSsuwEqS4MEeWIVtzmrjxAPkfyqo81wt Wf/8VzoDmI7kIwUgNmIojeIsEiDh0lPa9YTDX4ihp52j2MYtu8zzNnn/+ypAM4+6pCuP s1KGmVCKigKUA7/mWjpExzTJvNbyFQZ7yjF+kd/xYJtvOjZyvG8e0RxwLSKuGd40GEzm wOF6s3JhjJt0rkH3ZTkzyvvrZ/tUWmpfOK+Hxm4CAEyEH3lV6A+jD3hZyJARCsxC1owi eq8kyYx4F6v2rnsMHgRxqROpU85Tx+xa9ES1PhMKKRdhGHJyxaXqMAVMI1ImrlanDKrp xOew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uy+1LYtKetQWFHYH8PaN7/XbqnFh4isIp+PwWLyalNo=; b=QhhK3j2ACNGTHo8h9k2F5jvpikDuLkdQxcdcYtcnqFa2XZsOp1zT0aUnbxVlxuzZVM /3JrThrwhr1KFv47dd1dUEl5b8PRr9murHxEDquXT1gvDfL4pFwouk6arCWEETYQ7eoQ YusxT7/E2j7iHFv+Wae3Td5q01t0XNAXW0cKqN3Jd4DK65jJjTJB37tDnpXJBO2FDr4W 5CttpQPqQ1BTMu20iwJLBV2s6easQgAHujIG0BKCE/ZrK6Rnzzm/fj9zLszg4u4D1boo DujeNoBZcyMUb15P/FynMv9hv9TZ1ooFAs8QXOhsk8OaPFrAeokrS5XFs0d3X+o3IAt9 ABSg== X-Gm-Message-State: AFqh2koTBBEsIjna6I6MVzICnQShKQSN2j9pDzGVcvGNQJuCd/RwsN8E A5FnkjnGhs+gzHbn71MO8iHtgVcgRo8Tk7mQ X-Google-Smtp-Source: AMrXdXuXQ9EW1XNokSvls9hPBC8/jQRcqSDMFCWua55675KWLzN/6yZkEbH8hlUYpYsRQ9NSl90IfQ== X-Received: by 2002:a17:902:aa8e:b0:189:abdd:400a with SMTP id d14-20020a170902aa8e00b00189abdd400amr62371783plr.15.1673145443887; Sat, 07 Jan 2023 18:37:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 02/36] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL Date: Sat, 7 Jan 2023 18:36:45 -0800 Message-Id: <20230108023719.2466341-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1673145905331100003 Content-Type: text/plain; charset="utf-8" Many hosts pass and return 128-bit quantities like sequential 64-bit quantities. Treat this just like we currently break down 64-bit quantities for a 32-bit host. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index da91779890..99e6e4e1a8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -686,11 +686,22 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out =3D 64 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; + assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); + break; + case dh_typecode_i128: + info->nr_out =3D 128 / TCG_TARGET_REG_BITS; + info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ + switch (/* TODO */ TCG_CALL_RET_NORMAL) { + case TCG_CALL_RET_NORMAL: + assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); + break; + default: + qemu_build_not_reached(); + } break; default: g_assert_not_reached(); } - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); =20 /* * Parse and place function arguments. @@ -712,6 +723,9 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_ptr: type =3D TCG_TYPE_PTR; break; + case dh_typecode_i128: + type =3D TCG_TYPE_I128; + break; default: g_assert_not_reached(); } @@ -751,6 +765,19 @@ static void init_call_layout(TCGHelperInfo *info) } break; =20 + case TCG_TYPE_I128: + switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + case TCG_CALL_ARG_EVEN: + layout_arg_even(&cum); + /* fall through */ + case TCG_CALL_ARG_NORMAL: + layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); + break; + default: + qemu_build_not_reached(); + } + break; + default: g_assert_not_reached(); } @@ -1668,11 +1695,13 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) op->args[pi++] =3D temp_arg(ret); break; case 2: + case 4: tcg_debug_assert(ret !=3D NULL); - tcg_debug_assert(ret->base_type =3D=3D ret->type + 1); + tcg_debug_assert(ret->base_type =3D=3D ret->type + ctz32(n)); tcg_debug_assert(ret->temp_subindex =3D=3D 0); - op->args[pi++] =3D temp_arg(ret); - op->args[pi++] =3D temp_arg(ret + 1); + for (i =3D 0; i < n; ++i) { + op->args[pi++] =3D temp_arg(ret + i); + } break; default: g_assert_not_reached(); --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145625; cv=none; d=zohomail.com; s=zohoarc; b=h5OX/CwGPF94ido76Ix852bb2Kuzkhqjdy6bNo93E/zbYlRB4h1H6mZaBrIwWLVWfLjSkJfvNLQKWNiiWHBhtEtwgSWp7RF8dkwMkWtbOeOnUsyrq9V8TlDt0C2BVrlPTOw4dVmRG3YP+FaHyTppE90AFerK2VkT672KQvNMXio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145625; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ie3FlFBACJeq4X/M6VQiwe1m8Ml1Kbx+Yprz1q0XbrA=; b=htuE08ICA1XnKrGM9Vhj3RwTaUDpHd82MDNhN4ARs3yKS/wg6akgs13LZWCGnTi5GobLPv6hSosld/KmfFVz5/9SQzylmYue/oUZVQnYNOw2JKEZcz/6Wf7zlQB2kUAR7iOeuvKHo6bGB5ictKz1ke4F+PWYzcP9uiYhqBVjavY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145625525384.1922091034089; Sat, 7 Jan 2023 18:40:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZ4-0004ga-Tn; Sat, 07 Jan 2023 21:37:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZ2-0004eb-Ho for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:36 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYs-0004Vf-37 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:36 -0500 Received: by mail-pj1-x102d.google.com with SMTP id fz16-20020a17090b025000b002269d6c2d83so8701099pjb.0 for ; Sat, 07 Jan 2023 18:37:25 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ie3FlFBACJeq4X/M6VQiwe1m8Ml1Kbx+Yprz1q0XbrA=; b=Z15r7KZxo6FKWk9NQI5CRhE+8/7Y/WGTW39Y29D4hKJUkIKkC6fUGY6fDsLJ8Uj1OJ 4mkSehnvjsUrwpkvvSOFrB4ULe04PPEt3eE3rSS805ppw6s3/6g8JHQ+31MHlEQx5kBb dRB/QdEIL49sKWQYZNzMtgInpZdQdeeeq7pkejuZNfbUS8YNAZCEswSTW4IuCvt6DEsl nOpvnNbv1DWAwEycMigmUBmJmYJNKN1eJiL6K8HHZfAYtBWVmnJRduLAIEegXGE1qY+U Sh9HdkSX4qeIbwI34dmRNaKjKuBbGOQn9t7zVOAxGpOtYz/oj5b5pSXEsvyJl07ruErH HaRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ie3FlFBACJeq4X/M6VQiwe1m8Ml1Kbx+Yprz1q0XbrA=; b=Q/tkWuuVasRT/B43OZKYnlmw65/at53hnkiMcxAziANges688VIY7wjdU8D87WMZvU QSJC79DPcsj/JxCaa40JW+0T14xtnztYFeCfkGdTeY6Hlvhek1/SPB3ibXFM04sL/UVC ja7Op7OJPu7RJoUy53ve5o1+m6NRR2CWVYvfsBv5GktZA3dM6wXetgEItq/GlZE/tGkz uH49BB0hDWgYTfDb36BOWRBSEFArRyFdCaeHgfpT3uPvf+vaD+PoEj3RMB8VGJS4rrf8 gphzsLfrv0woZJk6+yKNYLHxX9mlNs6s8vsXHd9hRd19/4qZJ6DjojVeFTWQn7XYVQz6 GG5A== X-Gm-Message-State: AFqh2koJLhN9OO1grfZgHeNP2kIbrqLtWlgFcSjJTNmlBNYxVIjcIVuO CJ4U5GtdQJPQHlhdgSjLfj9I7XKRe+rnXMj0 X-Google-Smtp-Source: AMrXdXsW2CjhvWbAVrh8ulwzsWWWefeDvIT9tKykiaRfAk2sc1JVK/ybfqkQeHdkKP5VPKJQ2TrvKw== X-Received: by 2002:a05:6a20:a584:b0:ad:a5fd:b664 with SMTP id bc4-20020a056a20a58400b000ada5fdb664mr68551943pzb.37.1673145444802; Sat, 07 Jan 2023 18:37:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Date: Sat, 7 Jan 2023 18:36:46 -0800 Message-Id: <20230108023719.2466341-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145626371100001 Content-Type: text/plain; charset="utf-8" When allocating a temp to the stack frame, consider the base type and allocate all parts at once. Signed-off-by: Richard Henderson --- tcg/tcg.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 99e6e4e1a8..7e69e2c9fd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3242,11 +3242,12 @@ static bool liveness_pass_2(TCGContext *s) =20 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - int size =3D tcg_type_size(ts->type); - int align; intptr_t off; + int size, align; =20 - switch (ts->type) { + /* When allocating an object, look at the full type. */ + size =3D tcg_type_size(ts->base_type); + switch (ts->base_type) { case TCG_TYPE_I32: align =3D 4; break; @@ -3277,13 +3278,26 @@ static void temp_allocate_frame(TCGContext *s, TCGT= emp *ts) tcg_raise_tb_overflow(s); } s->current_frame_offset =3D off + size; - - ts->mem_offset =3D off; #if defined(__sparc__) - ts->mem_offset +=3D TCG_TARGET_STACK_BIAS; + off +=3D TCG_TARGET_STACK_BIAS; #endif - ts->mem_base =3D s->frame_temp; - ts->mem_allocated =3D 1; + + /* If the object was subdivided, assign memory to all the parts. */ + if (ts->base_type !=3D ts->type) { + int part_size =3D tcg_type_size(ts->type); + int part_count =3D size / part_size; + + ts -=3D ts->temp_subindex; + for (int i =3D 0; i < part_count; ++i) { + ts[i].mem_offset =3D off + i * part_size; + ts[i].mem_base =3D s->frame_temp; + ts[i].mem_allocated =3D 1; + } + } else { + ts->mem_offset =3D off; + ts->mem_base =3D s->frame_temp; + ts->mem_allocated =3D 1; + } } =20 /* Assign @reg to @ts, and update reg_to_temp[]. */ --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145852; cv=none; d=zohomail.com; s=zohoarc; b=SvijjD8AaXxrSyjH6JB326K3d76XtaMfAN5d2rt0uJlvAhaJwvbqjcC+XG0MpOm4rCZiOj0kxtDN9q4+75Qlj16aUqMy9FecIDvBfwgjyLJxY6eiWrfcm1QdqrBiCst3CvlBtpuZBmnyM8uklz30hxlxR3FEO+i/yROTAhWxUTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9Rv856N+OWstGUl7U1vP59WucQCWPrxG6fVCW7RDz4k=; b=R14NeCGAtqFqQNo837Ore5YrnRYAo/u+Nwjj8Htqc8FQg0khfW6tdlhUSGEIvBAAsbothGE0gqqsnCg308bG0UkjrCazulKTGBnjpeSPAlyWAxT/b9UjJa2eF1SX99XgjFkP+Yxg7FWQTPV37T5Jg2zQhfjskp4fbNh/zCMQ3K0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167314585206576.52121212335453; Sat, 7 Jan 2023 18:44:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZ7-0004ic-Bi; Sat, 07 Jan 2023 21:37:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZ5-0004gn-AP for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:39 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYt-0004WI-Cw for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:39 -0500 Received: by mail-pl1-x635.google.com with SMTP id w3so5884987ply.3 for ; Sat, 07 Jan 2023 18:37:26 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Rv856N+OWstGUl7U1vP59WucQCWPrxG6fVCW7RDz4k=; b=fwnqtv2jC1ESO6lC5Y/IX69fD2uiohbh2dlaBhqIJbRImITXE5f0gRRB53LvD4+qGu eb2v1+Y6NM8MKVEFWYxwb+tUCD7RhgA2Iy/qxjlqNUxMTgIX4tPkOnz0BnrDLNMKgx1z YucwxKi04pkBHZaeCjtaFjgw6NOZO0m1GUijODP5btf5r5+H/+0sPcqhY4pBy6TUSZ5Z rW3lYxxsxu97umMu+3Jm+LxaGkpgeFtsK4+z/R5MeDfKuWaN9bZE+uXnm+iH141I3+kJ dcg17m1mguxXmpTaBR6I0gzQJ0WCZW2LsTzGfAhWFR8TGe/tUunOpdah7qQBCfyDTuej 3wCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Rv856N+OWstGUl7U1vP59WucQCWPrxG6fVCW7RDz4k=; b=YtsWswbjDOtuiJyhSHnt3/ih88mePBHMBkBQN/FRp+sewoknYJVHCJjWO7e35E0H9s G8tL0VqxDb2K9kCpbybRZC7azE1cC1OyQ9vHWF8ZbgawWLvPenZFSOy/8X4kg5WBmEB7 +omYTNCOjSVb54o9hbLLEj8k4kvzGgl/mxXHhNuHuOpmnobO3A146971V9vo6H0pyjdC 3dYL6T2RT7tylaN1K4fS+J5njJyzTmswTZg94MpdbJR8+cI4NosH5HE+ArqS2YA6XPBD 5YRFZDuRg9cVeB5nGypplLD/8lbPZ+OnhzA3qbVnSQOGMum8KnJIEJgRqBSQ5IXCAn0+ vhJw== X-Gm-Message-State: AFqh2kqqYZzmg4hCM4Q+dZMIuCtHTeO3VolEsafspoMG5NHGYrwvznrQ YVHRJbj+pUD2FGmFfLajUTbAqutHA88NnRe7 X-Google-Smtp-Source: AMrXdXuz9rPfuEcj89rl2AbxoiX8/IJTVUDvrXji45IGqXFo8r5ub0hZzb9mYsQ2kUJQVzuAzgBDMw== X-Received: by 2002:a17:902:ccc4:b0:186:e434:6265 with SMTP id z4-20020a170902ccc400b00186e4346265mr73347806ple.2.1673145445962; Sat, 07 Jan 2023 18:37:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 04/36] tcg: Introduce tcg_out_addi_ptr Date: Sat, 7 Jan 2023 18:36:47 -0800 Message-Id: <20230108023719.2466341-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145853166100001 Content-Type: text/plain; charset="utf-8" Implement the function for arm, i386, and s390x, which will use it. Add stubs for all other backends. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++++++ tcg/arm/tcg-target.c.inc | 20 ++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 8 ++++++++ tcg/loongarch64/tcg-target.c.inc | 7 +++++++ tcg/mips/tcg-target.c.inc | 7 +++++++ tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 7 +++++++ tcg/s390x/tcg-target.c.inc | 7 +++++++ tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 7 +++++++ 11 files changed, 86 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 7e69e2c9fd..a6c2783285 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,6 +103,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g) + __attribute__((unused)); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ad1816e32d..2279a14c11 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1102,6 +1102,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg rd, tcg_out_insn(s, 3305, LDR, 0, rd); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + /* Define something more legible for general use. */ #define tcg_out_ldst_r tcg_out_insn_3310 =20 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9245ea86d0..8b24481d8c 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2540,6 +2540,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + int enc, opc =3D ARITH_ADD; + + /* All of the easiest immediates to encode are positive. */ + if (imm < 0) { + imm =3D -imm; + opc =3D ARITH_SUB; + } + enc =3D encode_imm(imm); + if (enc >=3D 0) { + tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); + tcg_out_dat_reg(s, COND_AL, opc, rd, rs, + TCG_REG_TMP, SHIFT_IMM_LSL(0)); + } +} + /* Type is always V128, with I64 elements. */ static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg r= h) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 58bd5873f5..6a021dda8b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1069,6 +1069,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val =3D=3D (int8_t)val) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index c9e99e8ec3..54b1dcd911 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -389,6 +389,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_andi(s, ret, arg, 0xff); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 292e490b5c..22b5463f0f 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -550,6 +550,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int fla= gs) { /* ret and arg can't be register tmp0 */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0621463f6..bf3812eb8d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1125,6 +1125,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg ret, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static bool mask_operand(uint32_t c, int *mb, int *me) { uint32_t lsb, test; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f741e0582d..b961972b9f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -558,6 +558,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b9ba7b605e..d65cd79899 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1020,6 +1020,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTyp= e type, TCGArg val, return false; } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); +} + /* load data from an absolute host address */ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, const void *abs) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index eb913f33c8..f6a8a8e605 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -497,6 +497,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d36a7ebdd1..633345d74b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -557,6 +557,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, const TCGHelperInfo *info) { --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1lsxB0Q3bC5RA9mVuczL9+THSacM775KBH8YOyPIxoI=; b=ENvIh9xN742A5aZ45VE/p5kFr/9irKWtvvspMUP5BRbgcNPHSnxkAXSyRqtP3PQZWs N0KZscRbZRr73VpRkTaps2vo2tCxMeuNh1a0ScOMG9WA6KzlgR7WcWRAQy6LlGXEKoaG flFWdtvQUqheArBdgTaQwMn9jgvdgdqmSLrlFfeFdYW//yLtcA1O6jJcZiBLEhW+eG08 rjmr5dx3aVyMSJHF87Z3hY9oKvQ+MWjtf+g/BrTNScgMRe03zHx/HkZiDZNduq1IS34Q +guz8XFXGkIK2FOKPWwNw2u1ntvn1fxuF1pE0cNyErf+HM94cC3c8c1MoatQ8JvhgncM zLOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1lsxB0Q3bC5RA9mVuczL9+THSacM775KBH8YOyPIxoI=; b=Ud599SRXLMucpLTSZ/cr8pSzbfnZt0P4ls8zFjF8Yo7rB7ONk6rvMHp9M0reKDuUsi 0RmxPWTGRD6SJlhiZfwhpLHThGdfvrgzzAkgp5ZUeYrDkgsACjtT1tOzAkHpw84wzmVS RHi1uE93OBDb2dqjfD5rwp2yvDwoIn3twbqyaJQ80q+5K7sE2pedE601+lnCLip/5ePw iWRnSje3/E9oxkbKKUqRqUrCZFFrgTdGIImZbkRuyxYvFgf5HP10bgVF7E8T6rxy3QcA S1uq0pVBuGqXpCJOlujvVcFehC3xPe00O0kURa2Ak0Rkoyz763NbglMvDHhatWSvUF8B futg== X-Gm-Message-State: AFqh2kou1WtzTRpCIoalVvPvOSGZh4R4LIODfqkLDtTkUJoUzixC67Uq In3qpMA7VLl8oWvaf7RIhUws5vAclk+APXVV X-Google-Smtp-Source: AMrXdXsGgYTqXe6+VEt7fnQDeU5cG9TOVBEpCAYKbHgZmvTCWUva02CX1eeOCwjWxCgUWwuEU9SlZw== X-Received: by 2002:a17:902:a98a:b0:189:cef2:88e3 with SMTP id bh10-20020a170902a98a00b00189cef288e3mr62240851plb.57.1673145446963; Sat, 07 Jan 2023 18:37:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Date: Sat, 7 Jan 2023 18:36:48 -0800 Message-Id: <20230108023719.2466341-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145492178100006 Content-Type: text/plain; charset="utf-8" These will be used by some hosts, both 32 and 64-bit, to pass and return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 3 + tcg/tcg.c | 135 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 135 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 6e50aeba3a..2ec1ea01df 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -36,6 +36,7 @@ */ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference */ } TCGCallReturnKind; =20 typedef enum { @@ -44,6 +45,8 @@ typedef enum { TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ + TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ } TCGCallArgumentKind; =20 typedef struct TCGCallArgumentLoc { diff --git a/tcg/tcg.c b/tcg/tcg.c index a6c2783285..93d1331f93 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,8 +103,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g) - __attribute__((unused)); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); @@ -662,6 +661,38 @@ static void layout_arg_normal_n(TCGCumulativeArgs *cum, cum->arg_slot +=3D n; } =20 +static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc =3D &info->in[cum->info_in_idx]; + int n =3D 128 / TCG_TARGET_REG_BITS; + + /* The first subindex carries the pointer. */ + layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); + + /* + * The callee is allowed to clobber memory associated with + * structure pass by-reference. Therefore we must make copies. + * Allocate space from "ref_slot", which will be adjusted to + * follow the parameters on the stack. + */ + loc[0].ref_slot =3D cum->ref_slot; + + /* + * Subsequent words also go into the reference slot, but + * do not accumulate into the regular arguments. + */ + for (int i =3D 1; i < n; ++i) { + loc[i] =3D (TCGCallArgumentLoc){ + .kind =3D TCG_CALL_ARG_BY_REF_N, + .arg_idx =3D cum->arg_idx, + .tmp_subindex =3D i, + .ref_slot =3D cum->ref_slot + i, + }; + } + cum->info_in_idx +=3D n; + cum->ref_slot +=3D n; +} + static void init_call_layout(TCGHelperInfo *info) { int max_reg_slots =3D ARRAY_SIZE(tcg_target_call_iarg_regs); @@ -697,6 +728,14 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_RET_NORMAL: assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); break; + case TCG_CALL_RET_BY_REF: + /* + * Allocate the first argument to the output. + * We don't need to store this anywhere, just make it + * unavailable for use in the input loop below. + */ + cum.arg_slot =3D 1; + break; default: qemu_build_not_reached(); } @@ -775,6 +814,9 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_ARG_NORMAL: layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); break; + case TCG_CALL_ARG_BY_REF: + layout_arg_by_ref(&cum, info); + break; default: qemu_build_not_reached(); } @@ -790,7 +832,39 @@ static void init_call_layout(TCGHelperInfo *info) assert(cum.info_in_idx <=3D ARRAY_SIZE(info->in)); /* Validate the backend has enough argument space. */ assert(cum.arg_slot <=3D max_reg_slots + max_stk_slots); - assert(cum.ref_slot <=3D max_stk_slots); + + /* + * Relocate the "ref_slot" area to the end of the parameters. + * Minimizing this stack offset helps code size for x86, + * which has a signed 8-bit offset encoding. + */ + if (cum.ref_slot !=3D 0) { + int ref_base =3D 0; + + if (cum.arg_slot > max_reg_slots) { + int align =3D __alignof(Int128) / sizeof(tcg_target_long); + + ref_base =3D cum.arg_slot - max_reg_slots; + if (align > 1) { + ref_base =3D ROUND_UP(ref_base, align); + } + } + assert(ref_base + cum.ref_slot <=3D max_stk_slots); + + if (ref_base !=3D 0) { + for (int i =3D cum.info_in_idx - 1; i >=3D 0; --i) { + TCGCallArgumentLoc *loc =3D &info->in[i]; + switch (loc->kind) { + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: + loc->ref_slot +=3D ref_base; + break; + default: + break; + } + } + } + } } =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; @@ -1716,6 +1790,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) =20 switch (loc->kind) { case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: op->args[pi++] =3D temp_arg(ts); break; =20 @@ -4382,6 +4458,27 @@ static void load_arg_normal(TCGContext *s, const TCG= CallArgumentLoc *l, } } =20 +static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, + intptr_t ref_off, TCGRegSet *allocated_regs) +{ + TCGReg reg; + int stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); + + if (stk_slot < 0) { + reg =3D tcg_target_call_iarg_regs[arg_slot]; + tcg_reg_free(s, reg, *allocated_regs); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_regset_set_reg(*allocated_regs, reg); + } else { + reg =3D tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], + *allocated_regs, 0, false); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + stk_slot * sizeof(tcg_target_long)); + } +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs =3D TCGOP_CALLO(op); @@ -4405,6 +4502,16 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) case TCG_CALL_ARG_EXTEND_S: load_arg_normal(s, loc, ts, &allocated_regs); break; + case TCG_CALL_ARG_BY_REF: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + loc->ref_slot * sizeof(tcg_target_long), + &allocated_regs); + break; + case TCG_CALL_ARG_BY_REF_N: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + break; default: g_assert_not_reached(); } @@ -4436,6 +4543,19 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) save_globals(s, allocated_regs); } =20 + /* + * If the ABI passes a pointer to the returned struct as the first + * argument, load that now. Pass a pointer to the output home slot. + */ + if (info->out_kind =3D=3D TCG_CALL_RET_BY_REF) { + TCGTemp *ts =3D arg_temp(op->args[0]); + + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_r= egs); + } + tcg_out_call(s, tcg_call_func(op), info); =20 /* Assign output registers and emit moves if needed. */ @@ -4452,6 +4572,15 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) ts->mem_coherent =3D 0; } break; + + case TCG_CALL_RET_BY_REF: + /* The callee has performed a write through the reference. */ + for (i =3D 0; i < nb_oargs; i++) { + TCGTemp *ts =3D arg_temp(op->args[i]); + ts->val_type =3D TEMP_VAL_MEM; + } + break; + default: g_assert_not_reached(); } --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145581; cv=none; d=zohomail.com; s=zohoarc; b=F7Q7fX++Pr0E2/btYbL0X0efthpgVQ5+Hgz6pghIkpybPkLqpnRg1lugOWAGNoV9AZPWw/hzeUVkSqNh526/8OIddiNMwEigEu5yHv/b0vHm1NbHabSMx+YzvK7BV028RskQj5rhO38cJnPpJ4fvIeLk18aiXAk/hPYDWV+xuPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145581; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+2kpzoSN5frXUNS/YnvoqX3GwlgAgZ4V3+f4wTeNprg=; b=C39XRTn6HZlxMhkvitzBBeZa//WX4MQk1iXA2Algw6IuP790cZIKmglurQl+I8XVbzRcyO2qVKLPAUwb2P/WcvqR741V29kERyoBdtIsEzyzEjCRpYqeCMwDuaItPyB6Mxln1YnaKYTS5A0LjXkIxB3ybpOuVtyfMHVqA1FSCoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145581162457.45809274625776; Sat, 7 Jan 2023 18:39:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZB-0004ml-P3; Sat, 07 Jan 2023 21:37:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZ9-0004lL-UA for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:43 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYv-0004XK-8L for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:43 -0500 Received: by mail-pj1-x1034.google.com with SMTP id c8-20020a17090a4d0800b00225c3614161so9249124pjg.5 for ; Sat, 07 Jan 2023 18:37:28 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+2kpzoSN5frXUNS/YnvoqX3GwlgAgZ4V3+f4wTeNprg=; b=PbOSEtJiVN9CjNCJC7ZSsxT3qdWW+Lab9/Ol1RfgH/I8JrQi+YjKAY6hso1RnGOt+Y 0YcT4+rXZ1lYRAx7l256panNwVBbgHww1BcYkfkZrv1hdOYpXqAVfjNMW0773bDlsThz t3LGY0+F1fWcrcdP8GEcB0G7gvFRwcy9DpvmDXnalpv80IXFvlIy3315k62+VL63Evsk smYf5iN6gZM3ZNQH2ltu2gqlH9/8101fhfkfEgu1qKVoBWBVVGs211Lm9ZMAa34To9Ui MCV26XKnFznysxHdUdsQMo0Vw8fcaGAWeoCl2Udtqbm5qN6eTCWlBkIu4jdZ1z1JSTLV wgKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+2kpzoSN5frXUNS/YnvoqX3GwlgAgZ4V3+f4wTeNprg=; b=AXKMRi0IJh1BBpwUgNb2RWn33xESGqt9q0thLMnWOznFx8HzQw0pR5f54CEDMqzCvF Z+j5m5MPO+RkEasj83J0ZkVZXv2tQAuIFmMyjc+80uyS2J5t37lDgiNWZfT+M1r0oCER 9FvcvEqo914MrM1U/2ta8xTxjAp8Xeenqf11J3gqBChm0XKzcNJ2J/KfD01kB+dpZP5D RR3zIC93HiqjEFlor+DRiN4M0e8Pr1MRF6O3YDP4zHGPtaSYQ+2ubeoOv7VYC253caVy mA4CgQ71UrHmbUrl8ls88AZ/vKSAsuxjs6aJ811Ni6sEdokF5qFEMpxtBlxA8hanfR31 45Ew== X-Gm-Message-State: AFqh2kqrgWNuZPgKK1PQYivGZlmFWebmZQUNDsRgwHBK1q4A8Ov0Jr23 kwuONNw/kbR79DiTNUD9mAct/nKgZ1L6wDcg X-Google-Smtp-Source: AMrXdXtnXkhIZquwJZf1edTcxpn8Eid7e+zQ2EKGi4DGzVpvnPe2KBbQpWlzcPf9p/h/CBiNyBhDGg== X-Received: by 2002:a17:903:3287:b0:192:e0ab:a4a2 with SMTP id jh7-20020a170903328700b00192e0aba4a2mr15422001plb.51.1673145447968; Sat, 07 Jan 2023 18:37:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg Date: Sat, 7 Jan 2023 18:36:49 -0800 Message-Id: <20230108023719.2466341-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145582199100003 Content-Type: text/plain; charset="utf-8" Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 9 ++++++--- tcg/aarch64/tcg-target.c.inc | 10 +++++++--- tcg/arm/tcg-target.c.inc | 10 +++++++--- tcg/i386/tcg-target.c.inc | 16 ++++++++++------ tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 10 ++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ tcg/tci/tcg-target.c.inc | 12 ++++++------ 11 files changed, 72 insertions(+), 46 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 93d1331f93..092cdaf422 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -148,6 +148,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, const TCGHelperInfo *info); +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -719,14 +720,16 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out =3D 64 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ switch (/* TODO */ TCG_CALL_RET_NORMAL) { case TCG_CALL_RET_NORMAL: - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)= ); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case TCG_CALL_RET_BY_REF: /* @@ -4563,7 +4566,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) case TCG_CALL_RET_NORMAL: for (i =3D 0; i < nb_oargs; i++) { TCGTemp *ts =3D arg_temp(op->args[i]); - TCGReg reg =3D tcg_target_call_oarg_regs[i]; + TCGReg reg =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i= ); =20 /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 2279a14c11..dfe569dd8c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] =3D { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 }; -static const int tcg_target_call_oarg_regs[1] =3D { - TCG_REG_X0 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_X0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8b24481d8c..4e1d06dcd8 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -79,9 +79,13 @@ static const int tcg_target_reg_alloc_order[] =3D { static const int tcg_target_call_iarg_regs[4] =3D { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 }; -static const int tcg_target_call_oarg_regs[2] =3D { - TCG_REG_R0, TCG_REG_R1 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_R0 + slot; +} =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6a021dda8b..ab6881a4f3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -109,12 +109,16 @@ static const int tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_EDX -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + switch (kind) { + case TCG_CALL_RET_NORMAL: + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return slot ? TCG_REG_EDX : TCG_REG_EAX; + default: + g_assert_not_reached(); + } +} =20 /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 54b1dcd911..f6b0ed00bb 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #ifndef CONFIG_SOFTMMU #define USE_GUEST_BASE (guest_base !=3D 0) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 22b5463f0f..92883176c6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] =3D { #endif }; =20 -static const TCGReg tcg_target_call_oarg_regs[2] =3D { - TCG_REG_V0, - TCG_REG_V1 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_V0 + slot; +} =20 static const tcg_insn_unit *tb_ret_addr; static const tcg_insn_unit *bswap32_addr; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index bf3812eb8d..d31e6c3de4 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R10 }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R3, - TCG_REG_R4 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_R3 + slot; +} =20 static const int tcg_target_callee_save_regs[] =3D { #ifdef _CALL_DARWIN diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index b961972b9f..7cfd35e753 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); + return TCG_REG_A0 + slot; +} =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d65cd79899..cebf180777 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -390,9 +390,12 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_R6, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R2, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_R2; +} =20 #define S390_CC_EQ 8 #define S390_CC_LT 4 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index f6a8a8e605..9b5afb8248 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -133,12 +133,12 @@ static const int tcg_target_call_iarg_regs[6] =3D { TCG_REG_O5, }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); + return TCG_REG_O0 + slot; +} =20 #define INSN_OP(x) ((x) << 30) #define INSN_OP2(x) ((x) << 22) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 633345d74b..cd53cb6b6b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -200,12 +200,12 @@ static const int tcg_target_reg_alloc_order[] =3D { /* No call arguments via registers. All will be stored on the "stack". */ static const int tcg_target_call_iarg_regs[] =3D { }; =20 -static const int tcg_target_call_oarg_regs[] =3D { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS =3D=3D 32 - TCG_REG_R1 -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + return TCG_REG_R0 + slot; +} =20 #ifdef CONFIG_DEBUG_TCG static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146550; cv=none; d=zohomail.com; s=zohoarc; b=KsPHlEcsX9SLPcaHGFWIRn91RKeK6s0U+3OZ//Sa4idV0aZt9X2a2WglWh6CBdIZlsgwtNFggHDoFK29XwJsaEaij2s99rujvYhyMSjC10YIAjBMxO7PLc2qMLLr4/1OMxYRYNc+FGDpvaSO5bbd32tXCdvEgyQr5LDv5kwVbaQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146550; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KwGYqVGD9ayC3AoH0H/svPpb9D46lwJjNWaf8TUEnLU=; b=E2ITnGFiGktpz/V2BXs53ljjGSMmJGJXRq1IVKYRjURYdHjpGX3QIiISA+TA6/ncLgATBZ4zZSegnZFAAGgsxl1X6Fl9eEZWY5yO3gwVGqOBlQHBIHebOsitgl2Upon5b4Mld+sexfa9UVxnThhGdc5lFs/tN/MC96E9uAmAgBU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146550810648.4535721291467; Sat, 7 Jan 2023 18:55:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZD-0004o5-Qu; Sat, 07 Jan 2023 21:37:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZC-0004nW-Px for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:46 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYw-0004Y1-4i for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:46 -0500 Received: by mail-pj1-x1036.google.com with SMTP id o7-20020a17090a0a0700b00226c9b82c3aso5820227pjo.3 for ; Sat, 07 Jan 2023 18:37:29 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KwGYqVGD9ayC3AoH0H/svPpb9D46lwJjNWaf8TUEnLU=; b=wo92Lmrg8YD5vmSAR4Njag3d7RjIflVg0qFT/FuisA8HWhC99wUN6pl72nAHTHIXC1 m9qx2+ZH893MqiWmY+ZKAOMKIMOybMJ+CNP82Wn/2U7Ihku+KQJz9oddghm+k6QqLbY+ /T+hysSGmq6i9kOGePI8M25ZlcAb3W0eub1ZvUInIqI3bK8DMIOukN2Y2RUEWTjchQPr YPp/mdD+aqWKlC8zPhN1Xn7PbIGuuyXS3Q8tzsHSWvU836rbpVaBHHKMEpfeySPrJps2 kY/3EqK4L5ZHCyGHndh7yLAvasBEFFEYxYjbAs4XolIH+si8uitooS3Bh0G+wzyi4RCp 6tzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KwGYqVGD9ayC3AoH0H/svPpb9D46lwJjNWaf8TUEnLU=; b=HpU53WWec+v6iKuQbKUMhhjfRSvH6cYLzv2DYAgcuvdOJqcEuMZ8cpJpwXo7tA7+yu BVYd/BmCyaSabzAjCo3eIiEmv14uK96RtY0+3Ac+hDbbap+C34J4uYS0lQdgghBD3quZ Ia0SU/qVApe+BVt6jmVGlvSDpBcrOiGuxpN4JilW0ROyGHxmSzjolcHT/XPdmSg/xVTs TL99462no4QkUep49iK6vSXNYsAaQ7uc7MB6Qvvq5pFb2IHyQzwcEmh10PKucFY8Bd6W CiVbiu+bNhCqQ6K8vGkmryASTF8i1lbSwtpzB8sM7083V+c5hUaIb8PvSX8SUmMHDGTz F2iA== X-Gm-Message-State: AFqh2kpBk4jVpaeZ4kWfzWhCSRpZCqMDU3clPsAaLmQ19kcKrWs+TnI9 nAC8Bt+dLTjZp3oqbw3T/j20gDkzq5KSC67+ X-Google-Smtp-Source: AMrXdXuvchFuNHxD5uxFyiEdD06AjVAaZQm4Sg+cipC99x3zOt9lqSTMkfEKHS3DFSMNh8ifrvfB2Q== X-Received: by 2002:a17:902:7c08:b0:193:13fc:8840 with SMTP id x8-20020a1709027c0800b0019313fc8840mr6381304pll.21.1673145448869; Sat, 07 Jan 2023 18:37:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 07/36] tcg: Add TCG_CALL_RET_BY_VEC Date: Sat, 7 Jan 2023 18:36:50 -0800 Message-Id: <20230108023719.2466341-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146552915100003 Content-Type: text/plain; charset="utf-8" This will be used by _WIN64 to return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2ec1ea01df..33f1d8b411 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -37,6 +37,7 @@ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ TCG_CALL_RET_BY_REF, /* for i128, by reference */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ } TCGCallReturnKind; =20 typedef enum { diff --git a/tcg/tcg.c b/tcg/tcg.c index 092cdaf422..c032606b21 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -731,6 +731,10 @@ static void init_call_layout(TCGHelperInfo *info) /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; + case TCG_CALL_RET_BY_VEC: + /* Query the single register now to trigger any assert early. = */ + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); + break; case TCG_CALL_RET_BY_REF: /* * Allocate the first argument to the output. @@ -4576,6 +4580,21 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) } break; =20 + case TCG_CALL_RET_BY_VEC: + { + TCGTemp *ts =3D arg_temp(op->args[0]); + + tcg_debug_assert(ts->base_type =3D=3D TCG_TYPE_I128); + tcg_debug_assert(ts->temp_subindex =3D=3D 0); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + tcg_out_st(s, TCG_TYPE_V128, + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), + ts->mem_base->reg, ts->mem_offset); + } + /* fall through to mark all parts in memory */ + case TCG_CALL_RET_BY_REF: /* The callee has performed a write through the reference. */ for (i =3D 0; i < nb_oargs; i++) { --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145835; cv=none; d=zohomail.com; s=zohoarc; b=gjve3tzFjRlI3BqNlYQhy6OBx0P1YEkvV+w8j/KZtmZ67D3XLpQ9IKmivPLC8pwo4cpF+h9id2lS1/9YZP0gATT1xCKb6ef7r2deWgj/svWkJqr7z6C+YojtDog3Icu+XLx1JsONyS3qXu680vyLM624Xnh4/zqcywjd/kZPY10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145835; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WlfgTKwjPzR9xe9xdxRaR9DbAja99BeWVoRkY0FKPGQ=; b=FJaf+yYVzVBA34H3Pkf5sfM+I4pMeBtZxwwYeRbinXOFqVCmj5dLGJB/2ELj7zWufbIS+LAAKjbRXXgd+CKjbkTSzRjnCWUN9U9hh8oemZ9KOc2ZAPIE+QydhOMRGvSNOQ7oqjmdsyvd5RwJSX+7gY6NvrXyzVM4e5vI1whGH7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167314583552644.84071498343019; Sat, 7 Jan 2023 18:43:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZH-0004r2-EG; Sat, 07 Jan 2023 21:37:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZF-0004pV-L1 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:49 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYx-0004YR-C8 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:49 -0500 Received: by mail-pj1-x1029.google.com with SMTP id b9-20020a17090a7ac900b00226ef160dcaso4079588pjl.2 for ; Sat, 07 Jan 2023 18:37:30 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WlfgTKwjPzR9xe9xdxRaR9DbAja99BeWVoRkY0FKPGQ=; b=e+v4MiVwddxBp2l39jIW6RzLdqvz5YNLBQIU7Y9Gn3yNmqKxhyiMJNExnpzQZprhki FeoH8b66BVuwewFCwvguHlvdebxJ8pnskAzLruSDArkmkR3gqR+58SI19WATcmAErkkW rD++O8ptdlvusHuUk/+nu8awE5Jb6xTWBl7JKkn65eFzq7ONaV4yluVx64o5lhcMmRL+ 6suYI9cKVUEg4MHJX1vUDfubFLTP1B1D+BKUZpsoYLdEgc9TcBUDGMbJ0DsNsUr/SnoF eHowhcb8tsMN1AOzO9lJ4LpYtWDaV7/ifWKcV75eLNDu/wYncUtRbOfBN4PCdNIgwgtt CZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WlfgTKwjPzR9xe9xdxRaR9DbAja99BeWVoRkY0FKPGQ=; b=dK8qhNDBTE76cSdBTCzIQyhhQfbfroxQWu1vJ438TUEykQwlQ4LpQ3p0xlt64OfESU LUy+/ePv5x6tsdTHpC9GNzPsiQlqiYglpKWqfCC8zeMrbIcTIMxfoeiaAKWEC6JhAoBO u3BJtafAJwywDqxcfpslCoyF6iYYSiNDwL1JEo1WgkDTodNPQKaqRQJhO+DPmXH9cXvp owVF1FnuFHsyPX9fd2WQ1kiKy+XA2kJTxKy9Be5eua6/QKyL/N6SiOW6hv9egOcHYjss u4WITywpstcZV8WIeWPk2zz1GcgbYHcmZtZsRFvY112GN48wYSUEr+D2sf+vBhvep4aZ PSkQ== X-Gm-Message-State: AFqh2kqrf57AM+X1zRLh/2EwSw80Aq+l8zBunJ4L/JzgvAs5sfCaLYY/ NvMRpQH8TRz2dwfSPiM2its+CU6w9rXZF0xW X-Google-Smtp-Source: AMrXdXsOLRLhUgqTsaAtzFwaH1QwckHBo7X0260/iPPIE7n7FpKtPadT+ACSyQrQE/159C3r09bS7A== X-Received: by 2002:a17:902:a5ca:b0:191:3aad:cf33 with SMTP id t10-20020a170902a5ca00b001913aadcf33mr58019695plq.55.1673145450098; Sat, 07 Jan 2023 18:37:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 08/36] include/qemu/int128: Use Int128 structure for TCI Date: Sat, 7 Jan 2023 18:36:51 -0800 Message-Id: <20230108023719.2466341-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145837048100003 Content-Type: text/plain; charset="utf-8" We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure. In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this. We cannot modify Int128 itself, as any changed alignment would also break libffi. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/atomic128.h | 29 +++++++++++++++++++++------ include/qemu/int128.h | 25 +++++++++++++++++++++--- util/int128.c | 42 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 9 deletions(-) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index adb9a1a260..d0ba0b9c65 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -44,13 +44,23 @@ #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return qatomic_cmpxchg__nocheck(ptr, cmp, new); + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(CONFIG_CMPXCHG128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return __sync_val_compare_and_swap_16(ptr, cmp, new); + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(__aarch64__) @@ -89,12 +99,18 @@ Int128 QEMU_ERROR("unsupported atomic") #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_read(Int128 *ptr) { - return qatomic_read__nocheck(ptr); + Int128Alias r; + + r.i =3D qatomic_read__nocheck((__int128_t *)ptr); + return r.s; } =20 static inline void atomic16_set(Int128 *ptr, Int128 val) { - qatomic_set__nocheck(ptr, val); + Int128Alias v; + + v.s =3D val; + qatomic_set__nocheck((__int128_t *)ptr, v.i); } =20 # define HAVE_ATOMIC128 1 @@ -132,7 +148,8 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) static inline Int128 atomic16_read(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ - return atomic16_cmpxchg(ptr, 0, 0); + Int128 z =3D int128_make64(0); + return atomic16_cmpxchg(ptr, z, z); } =20 static inline void atomic16_set(Int128 *ptr, Int128 val) @@ -141,7 +158,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) do { cmp =3D old; old =3D atomic16_cmpxchg(ptr, cmp, val); - } while (old !=3D cmp); + } while (int128_ne(old, cmp)); } =20 # define HAVE_ATOMIC128 1 diff --git a/include/qemu/int128.h b/include/qemu/int128.h index d2b76ca6ac..f62a46b48c 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -3,7 +3,12 @@ =20 #include "qemu/bswap.h" =20 -#ifdef CONFIG_INT128 +/* + * With TCI, we need to use libffi for interfacing with TCG helpers. + * But libffi does not support __int128_t, and therefore cannot pass + * or return values of this type, force use of the Int128 struct. + */ +#if defined(CONFIG_INT128) && !defined(CONFIG_TCG_INTERPRETER) typedef __int128_t Int128; =20 static inline Int128 int128_make64(uint64_t a) @@ -460,8 +465,7 @@ Int128 int128_divu(Int128, Int128); Int128 int128_remu(Int128, Int128); Int128 int128_divs(Int128, Int128); Int128 int128_rems(Int128, Int128); - -#endif /* CONFIG_INT128 */ +#endif /* CONFIG_INT128 && !CONFIG_TCG_INTERPRETER */ =20 static inline void bswap128s(Int128 *s) { @@ -472,4 +476,19 @@ static inline void bswap128s(Int128 *s) #define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX) #define INT128_MIN int128_make128(0, INT64_MIN) =20 +/* + * When compiler supports a 128-bit type, define a combination of + * a possible structure and the native types. Ease parameter passing + * via use of the transparent union extension. + */ +#ifdef CONFIG_INT128 +typedef union { + Int128 s; + __int128_t i; + __uint128_t u; +} Int128Alias __attribute__((transparent_union)); +#else +typedef Int128 Int128Alias; +#endif /* CONFIG_INT128 */ + #endif /* INT128_H */ diff --git a/util/int128.c b/util/int128.c index ed8f25fef1..df6c6331bd 100644 --- a/util/int128.c +++ b/util/int128.c @@ -144,4 +144,46 @@ Int128 int128_rems(Int128 a, Int128 b) return r; } =20 +#elif defined(CONFIG_TCG_INTERPRETER) + +Int128 int128_divu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.u =3D a.u / b.u; + return r.s; +} + +Int128 int128_remu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.u =3D a.u % b.u; + return r.s; +} + +Int128 int128_divs(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.i =3D a.i / b.i; + return r.s; +} + +Int128 int128_rems(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s =3D a_s; + b.s =3D b_s; + r.i =3D a.i % b.i; + return r.s; +} + #endif --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146224; cv=none; d=zohomail.com; s=zohoarc; b=GkCObDPnEDvwy2RbZV8Rwjo++/k5GB58q3+CwYg6rVGO88/57cB1zXJmAo8Ed8FWjhVdn6nhHWuRUSAs04MO+4NIlaQLp+LMGZhQ3rK7jfF2E8SK0jJ1H2u2DgCbXRXGgerRYqZqrNhc3WV/2DdVxLl9xwzYRmZZqQyF7dexf0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146224; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xWtD/TEe250UHjk6klCm4KJGVjq9QANqtB38KitJ/cg=; b=k4MO91M5CmBXNBN2h5UsOHaUO/BEn252tIlnTxnwdGbYIkSzQm5K1rEU5Hg7vRa1vv68m86uRN0x/9LT/E8bd4mrQ5NGPrdDGYCQ7+J5LNSNi4o+Xw4/Mw7NTOSeUlvqY1MvUYB5onaL+pRigmriI3GNRteoYq6EONEh3sGrOOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167314622439993.47226723556298; Sat, 7 Jan 2023 18:50:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZK-0004tN-AM; Sat, 07 Jan 2023 21:37:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZI-0004rm-RC for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:52 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYy-0004Yv-8a for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:52 -0500 Received: by mail-pl1-x635.google.com with SMTP id b2so5869222pld.7 for ; Sat, 07 Jan 2023 18:37:31 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xWtD/TEe250UHjk6klCm4KJGVjq9QANqtB38KitJ/cg=; b=H71P5HjcjjY9BV2F+Dlma7KDkuHyDeXp3KNRbW/tziJni06kJBEC5OW13d4PNcyNcV 6DfelLA5jmSd0gkKdRuW9acjj8HoYxZnRCgZwh4qTMo6XPS7BIGM1sE1bSkA5iigGglx KKL0FeGLhC5wBlex2xT3W43GUuffxP/NWZ4xJQDsMjXFkPhW48xDRN2ddQDQ67+Imj5r hA2iKzH3dnt6j7MtlnE/OGBK9twOqR9WAkVB+dvBxcWnsmjC3kK+ZKxcO0a9qR438lqC BwhEcnNswVahg8IqHvxsysfI0MRc8ociGYFLGKpeZ/ExHnUaQCj3qsFNRtnI502tVJg4 ApKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xWtD/TEe250UHjk6klCm4KJGVjq9QANqtB38KitJ/cg=; b=b0c3+K3edgx3zbA3OTKymiFIxcHJtkDiGF1zoFCoIKq/p5xD+eJzAn4hxsHd3U0fFP ApChSf9Fs5KQhiGtykrMg+EKOxYqqUv+7OjHemzm4KzaoA2i7/XuHi5Qxd19dXtXZItb f01d/QgM2wM1qAJl206UcWSazRhLhIVvlJXTvn0uf4XhOUjo00fzG95hBFcZ44eUohx5 gAo1mpdA/ArDPzMeJbT7XI5fc8HLFWDVcBHmdOe9LawQmI4a8+3WK7CV/bxlnKomTo9B Yii4Dk1XsHWFosNzTL5qaQmCz7Xl3ZhV+eYcYLVodqW6ssM3uRZi/R356dmHfTP3Afc1 XfyQ== X-Gm-Message-State: AFqh2kpAaodzDXcogv3sc+8ywyVaVnwnFgw1sv7T3nUYA5baZ4t5d/Xi 7W67d30JmQRSBpU/oIismRXw3FraUv6CWo7r X-Google-Smtp-Source: AMrXdXuteIDC/nhFnd3xhoSK4LQbIhQOSs2gg8voRi2TXc1aqi+nJ2V5NkckHMhOzCVGDQhDw/Jc9w== X-Received: by 2002:a17:903:230c:b0:192:64a9:62f5 with SMTP id d12-20020a170903230c00b0019264a962f5mr76931754plh.29.1673145450991; Sat, 07 Jan 2023 18:37:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 09/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Sat, 7 Jan 2023 18:36:52 -0800 Message-Id: <20230108023719.2466341-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146225619100006 Content-Type: text/plain; charset="utf-8" Fill in the parameters for the host ABI for Int128. Adjust tcg_target_call_oarg_reg for _WIN64, and tcg_out_call for i386 sysv. Allow TCG_TYPE_V128 stores without AVX enabled. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 10 ++++++++++ tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7edb7f1d9a..9e0e82d80a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -100,6 +100,16 @@ typedef enum { #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#if defined(_WIN64) +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC +#elif TCG_TARGET_REG_BITS =3D=3D 64 +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL +#else +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF +#endif =20 extern bool have_bmi1; extern bool have_popcnt; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ab6881a4f3..c96b5a6f43 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -115,6 +115,11 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) case TCG_CALL_RET_NORMAL: tcg_debug_assert(slot >=3D 0 && slot <=3D 1); return slot ? TCG_REG_EDX : TCG_REG_EAX; +#ifdef _WIN64 + case TCG_CALL_RET_BY_VEC: + tcg_debug_assert(slot =3D=3D 0); + return TCG_REG_XMM0; +#endif default: g_assert_not_reached(); } @@ -1188,9 +1193,16 @@ static void tcg_out_st(TCGContext *s, TCGType type, = TCGReg arg, * The gvec infrastructure is asserts that v128 vector loads * and stores use a 16-byte aligned offset. Validate that the * final pointer is aligned by using an insn that will SIGSEGV. + * + * This specific instance is also used by TCG_CALL_RET_BY_VEC, + * for _WIN64, which must have SSE2 but may not have AVX. */ tcg_debug_assert(arg >=3D 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + if (have_avx1) { + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg= 2); + } else { + tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); + } break; case TCG_TYPE_V256: /* @@ -1677,6 +1689,22 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *dest, const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); + +#ifndef _WIN32 + if (TCG_TARGET_REG_BITS =3D=3D 32 && info->out_kind =3D=3D TCG_CALL_RE= T_BY_REF) { + /* + * The sysv i386 abi for struct return places a reference as the + * first argument of the stack, and pops that argument with the + * return statement. Since we want to retain the aligned stack + * pointer for the callee, we do not want to actually push that + * argument before the call but rely on the normal store to the + * stack slot. But we do need to compensate for the pop in order + * to reset our correct stack pointer value. + * Pushing a garbage value back onto the stack is quickest. + */ + tcg_out_push(s, TCG_REG_EAX); + } +#endif } =20 static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146616; cv=none; d=zohomail.com; s=zohoarc; b=UDxkmYEub07QiJ2mFYeLGrS1enbHKUgv3eYhmtXuPzeVL/5N8FPPHOpRh0HVxOCDyGbH5uUg0O7KIhnQNO1+TqNrHnD41c7MFvUc3DedUgI5OXX+AUaMFCK8PQsALT4lnpcZVN8vJWFFkxxnJCf7CXkP5qa79CQ7MGyE/YRv9VI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146616; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vaZgOeSJc5X20dDhSfYmqdZAzqI99H2R1i2kilXRvO0=; b=ERozKxfkCZ6gtJs+0ZQLNH0R2KbC7zdNvD41YDStUui5hFcb67X4OepP/Lkr4LxocX+zBc0UiWGrlsKmZoZJSxXFAD/DalPplopJBZPB990hBkH7EX31wHj9wrYe2Pl/sG55fr4He0UmHMnLJ9+0vbfh1OVP4RffeRMoii8a4dE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146616053201.52641822708904; Sat, 7 Jan 2023 18:56:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZO-0004vN-04; Sat, 07 Jan 2023 21:37:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZM-0004uV-IP for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:56 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYz-0004ZY-B3 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:56 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d3so5853985plr.10 for ; Sat, 07 Jan 2023 18:37:32 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vaZgOeSJc5X20dDhSfYmqdZAzqI99H2R1i2kilXRvO0=; b=zfcdQM4/5q2ta7iuqZJrCCSzlJEXqS0WhwPx4k2uaLccpH7A3ev/saSPpc+LYwyd0J AgrpsdRZIn2LzaDQb7iloaUOiQHpAtZA2+Yx5ujE8QjfSECJA1y8Ul7Fuftx36LL4UDr 1nPYjlb50GAEO+JSU1QP4LOjqH7F+b0yu0EEiekrmaMZOX+R46lczBguI9VnwXd3hpxC BEzpB8Y+jHE650tRX9R7SqkvtIbUXLhh9TGPgCDk3VbExPINozRY927zKsmZc2y2DGvm 695kj/+z4hboxGHIU6LzH/UrqmsVrfqqX3QDNCn4pa/AH59Y9M62pU1cgXtpKf4gNOv8 chow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vaZgOeSJc5X20dDhSfYmqdZAzqI99H2R1i2kilXRvO0=; b=D5wTUQo6tHXwUacTs2NxjfVgNO30zpFbSVEah8potjJpXbLVIMRZrAYHNn41hamXSd KpmYnXTladgTeihsTXQmc1D1XtZ2mSB+4fhIhEDZd5sGY7m0gD0HZY6ttwQHQmb0Rdv8 MJliLOTZ+cSkWsb4EE1H3MN9QHGxegfYmaFRWuQ3r+AjcL8dLaKrS4ffmyBJ9Ryyh3xL t/pHU183fKw6/2HHbWY4U+kYQfA3FVnw70Zqz24ZW5CLhzaQr8iwAGQEUbQWau/M9l8y b0vLMBofkx3eK5IGqR8T/PTl1ToP26MSRYL86a1im8HBbJgL+ml6zMyJdrAmNIqS2xh5 xydg== X-Gm-Message-State: AFqh2kpNfPYWPtsffb4ohhbaxCrZ/oD762XLcB8MjdtxVf1QdSFcEynQ 128sReUOntFDsvo8I4U+eEtMwMibjCrxQIMh X-Google-Smtp-Source: AMrXdXunXck1RbJjtxPZRS4Fns32CadcdIyHqyR4VBZfg8T+f4zdjP7ao1DXYsALrVylTfbC76QznQ== X-Received: by 2002:a17:903:451:b0:192:820d:d1 with SMTP id iw17-20020a170903045100b00192820d00d1mr51051507plb.25.1673145452040; Sat, 07 Jan 2023 18:37:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering Date: Sat, 7 Jan 2023 18:36:53 -0800 Message-Id: <20230108023719.2466341-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146617051100003 Content-Type: text/plain; charset="utf-8" We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 05a24163d3..eeccdde8bc 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, ffi_call(pptr[1], pptr[0], stack, call_slots); } =20 - /* Any result winds up "left-aligned" in the stack[0] slot. */ switch (len) { case 0: /* void */ break; case 1: /* uint32_t */ /* + * The result winds up "left-aligned" in the stack[0] slot. * Note that libffi has an odd special case in that it will * always widen an integral result to ffi_arg. */ - if (sizeof(ffi_arg) =3D=3D 4) { - regs[TCG_REG_R0] =3D *(uint32_t *)stack; - break; - } - /* fall through */ - case 2: /* uint64_t */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]= ); + if (sizeof(ffi_arg) =3D=3D 8) { + regs[TCG_REG_R0] =3D (uint32_t)stack[0]; } else { - regs[TCG_REG_R0] =3D stack[0]; + regs[TCG_REG_R0] =3D *(uint32_t *)stack; } break; + case 2: /* uint64_t */ + /* + * For TCG_TARGET_REG_BITS =3D=3D 32, the register pair + * must stay in host memory order. + */ + memcpy(®s[TCG_REG_R0], stack, 8); + break; default: g_assert_not_reached(); } --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145972; cv=none; d=zohomail.com; s=zohoarc; b=bKsBWsjF5eQDLNWVddJY5SgRUgghgbU2KRDfip5ls0D1cEvrI74hjrLncmSWoZIqFk39JERWo/yj2U0TN1oR7Yf56sS5iPPHx1sczkJQlAxUTg4oLS//Kc6DUspujMvJJwEXy5Xpy8y0QxQg8ehWMfpCzvnUyI9tkOhDIRb/cLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145972; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lb1zdPDt2cXDP2uVEHjfwAEEiR/vLZlM3+YRRoy+01g=; b=mdFhiRv2xoTtsdj+Qpt0a6rNSo8Aqbfc8qvqbA/9jN9HxYugshzqSHp8vKW3tJzi0oN+fDDjUkC2qBxbXLoPN2ddI/mh5YknKGIQDrbIFcRFUmKZPnLjnBUahvi27bVnlDtLYcXTT4nHdKJHr9c78+2DwVgREJlBSFhzpNM33kI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145972536690.7899836192053; Sat, 7 Jan 2023 18:46:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZQ-0004wx-Lr; Sat, 07 Jan 2023 21:38:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZP-0004vj-4Y for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:59 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYz-0004VF-VB for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:37:58 -0500 Received: by mail-pl1-x636.google.com with SMTP id jl4so5863813plb.8 for ; Sat, 07 Jan 2023 18:37:33 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lb1zdPDt2cXDP2uVEHjfwAEEiR/vLZlM3+YRRoy+01g=; b=g1ePDDqFj2G6YHcZNLvj5WFVz4qK2f8FLFqzMf7+cf3Yp4/wMbTjSh6aaVpQ+PNfgR V03xuAGeQ5PHxHHExiG7M4Bgj2bcKSrlkydUKs5hkMTgov3VSmoPyDcRd1+Rfis6I8WH 2NhU/sA85MX+DAawF0m6b5cVYoEwDPIoQi2d3EybkWLzR7Mojoj+Dt3RtPtOsw8M9zBd ndwXLIAEMrU8tN2PMJubPsEMx0Vs5JFkPRt10KOk09HPFnFPFviUj/eYHVo8WTdtJVmd k+7gqNo2gC2g23LWfviAuDwughcnfJSzApTXH9888+9kfNWq5EvdKGFqCxqhg4wrqSmg vJ2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lb1zdPDt2cXDP2uVEHjfwAEEiR/vLZlM3+YRRoy+01g=; b=fpYgoxpxRDUPzhOdSGoSXImwyOtc4/Tbc0HpY3Fw7lja/5I/y9jW+z+GFT8lcinKMq NQWoI/hhyQju/Czke93+xpjI1gqnIeC1PgBUfeYjH/c+ZrPZijBcB5DoFsE1ON8AICyz QLLKlt43yMtIeHqAjh2M11OQKcGbfhPDj4vfiOejgBNtSUxDkXgDRw2qI7NlmnbQh23c MOnuJn5n9+sAhn7CgKYCy/5QOgR9JD3v+o5q9T4VxjU/XoElWxRSu64N5LUzXzaCkSCQ JFPUdLlUNBuPcHZxgww5TEkA4mA5IcatpqGn8ICYgzI8J0MM/HidhxmMkJ7IkNWC4Zpu +WEQ== X-Gm-Message-State: AFqh2kpC0hTVhpPxjvX1IfScrRtFO0veoOkNVA8f9ZpesmSwi2ZL+f1C wu2C6qDoACc0YIhrPRC4F4euP0O70A5DDI+W X-Google-Smtp-Source: AMrXdXtU22bKLYqtLjqmSKL8wJxOtEXKHoK2cKx6usN8OqH3mKXOdRFtxnog9XbB84W3A0UvhmW/Uw== X-Received: by 2002:a17:902:864a:b0:193:ab5:39c7 with SMTP id y10-20020a170902864a00b001930ab539c7mr7840520plt.11.1673145453160; Sat, 07 Jan 2023 18:37:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Sat, 7 Jan 2023 18:36:54 -0800 Message-Id: <20230108023719.2466341-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145973649100003 Content-Type: text/plain; charset="utf-8" Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now, but only fill in slots required for the call we're about to make. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 3 +++ tcg/tcg.c | 19 +++++++++++++++++ tcg/tci.c | 44 ++++++++++++++++++++-------------------- tcg/tci/tcg-target.c.inc | 10 ++++----- 4 files changed, 49 insertions(+), 27 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 94ec541b4e..9d569c9e04 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,10 +161,13 @@ typedef enum { #if TCG_TARGET_REG_BITS =3D=3D 32 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index c032606b21..6f72d4157a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -549,6 +549,22 @@ static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { + /* + * libffi does not support __int128_t, so we have forced Int128 + * to use the structure definition instead of the builtin type. + */ + static ffi_type *ffi_type_i128_elements[3] =3D { + &ffi_type_uint64, + &ffi_type_uint64, + NULL + }; + static ffi_type ffi_type_i128 =3D { + .size =3D 16, + .alignment =3D __alignof__(Int128), + .type =3D FFI_TYPE_STRUCT, + .elements =3D ffi_type_i128_elements, + }; + switch (argmask) { case dh_typecode_void: return &ffi_type_void; @@ -562,6 +578,8 @@ static ffi_type *typecode_to_ffi(int argmask) return &ffi_type_sint64; case dh_typecode_ptr: return &ffi_type_pointer; + case dh_typecode_i128: + return &ffi_type_i128; } g_assert_not_reached(); } @@ -592,6 +610,7 @@ static void init_ffi_layouts(void) /* Ignoring the return type, find the last non-zero field. */ nargs =3D 32 - clz32(typemask >> 3); nargs =3D DIV_ROUND_UP(nargs, 3); + assert(nargs <=3D MAX_CALL_IARGS); =20 ca =3D g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); ca->cif.rtype =3D typecode_to_ffi(typemask & 7); diff --git a/tcg/tci.c b/tcg/tci.c index eeccdde8bc..022fe9d0f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -470,12 +470,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; - void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; =20 regs[TCG_AREG0] =3D (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] =3D (uintptr_t)stack; - /* Other call_slots entries initialized at first use (see below). */ - call_slots[0] =3D NULL; tci_assert(tb_ptr); =20 for (;;) { @@ -498,26 +495,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 switch (opc) { case INDEX_op_call: - /* - * Set up the ffi_avalue array once, delayed until now - * because many TB's do not make any calls. In tcg_gen_callN, - * we arranged for every real argument to be "left-aligned" - * in each 64-bit slot. - */ - if (unlikely(call_slots[0] =3D=3D NULL)) { - for (int i =3D 0; i < ARRAY_SIZE(call_slots); ++i) { - call_slots[i] =3D &stack[i]; - } - } - - tci_args_nl(insn, tb_ptr, &len, &ptr); - - /* Helper functions may need to access the "return address" */ - tci_tb_ptr =3D (uintptr_t)tb_ptr; - { - void **pptr =3D ptr; - ffi_call(pptr[1], pptr[0], stack, call_slots); + void *call_slots[MAX_CALL_IARGS]; + ffi_cif *cif; + void *func; + unsigned i, s, n; + + tci_args_nl(insn, tb_ptr, &len, &ptr); + func =3D ((void **)ptr)[0]; + cif =3D ((void **)ptr)[1]; + + n =3D cif->nargs; + for (i =3D s =3D 0; i < n; ++i) { + ffi_type *t =3D cif->arg_types[i]; + call_slots[i] =3D &stack[s]; + s +=3D DIV_ROUND_UP(t->size, 8); + } + + /* Helper functions may need to access the "return address= " */ + tci_tb_ptr =3D (uintptr_t)tb_ptr; + ffi_call(cif, func, stack, call_slots); } =20 switch (len) { @@ -542,6 +539,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, */ memcpy(®s[TCG_REG_R0], stack, 8); break; + case 3: /* Int128 */ + memcpy(®s[TCG_REG_R0], stack, 16); + break; default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cd53cb6b6b..357888a532 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -203,7 +203,7 @@ static const int tcg_target_call_iarg_regs[] =3D { }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); - tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); + tcg_debug_assert(slot >=3D 0 && slot < 128 / TCG_TARGET_REG_BITS); return TCG_REG_R0 + slot; } =20 @@ -573,11 +573,11 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *func, =20 if (cif->rtype =3D=3D &ffi_type_void) { which =3D 0; - } else if (cif->rtype->size =3D=3D 4) { - which =3D 1; } else { - tcg_debug_assert(cif->rtype->size =3D=3D 8); - which =3D 2; + tcg_debug_assert(cif->rtype->size =3D=3D 4 || + cif->rtype->size =3D=3D 8 || + cif->rtype->size =3D=3D 16); + which =3D ctz32(cif->rtype->size) - 1; } new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); insn =3D deposit32(insn, 0, 8, INDEX_op_call); --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146260; cv=none; d=zohomail.com; s=zohoarc; b=EIWmPSe8VDROlkpd8V/6sN/x7oe7iUrQnUYGWiZcJcBUiUlggbbd1GXIGvcyCMqbbt60RyYxlnYq2FnTbNnmtweI5w1Oo4t2AqbIC0Zewcy71OAYVGh0YnzzfmVFtbg8dFtr2usS6u0mirBwmlcZG5RotUL9z3QAQIKfFzQowos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146260; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SYNYnzLrz9KCAUVy04IP4XZxPYGmUgBISTp436OAjA8=; b=GVg9LE+skfwz2LXgCzIj+OWw4Fluz3T6A94Rm99+qbn5qHrJL+3j+YRlah7bvjeatvVZt1TDpiAHeWogXXqKqDfsZUAiLbO7IfRp+WdXrgouNJC+aSvkzWa5GEBf0JVZIw9RvRjWK5SwN6NiU7ABm+PnWKH3r26PvZTXapooDFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146260317351.9130618486903; Sat, 7 Jan 2023 18:51:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZZ-00054F-Jt; Sat, 07 Jan 2023 21:38:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZW-000516-LC for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:06 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ1-0004at-DT for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:06 -0500 Received: by mail-pl1-x633.google.com with SMTP id c4so5881031plc.5 for ; Sat, 07 Jan 2023 18:37:35 -0800 (PST) Received: from stoup.. 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Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 3 +++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tcg.c | 6 +++--- tcg/ppc/tcg-target.c.inc | 3 +++ 9 files changed, 21 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 413a5410c5..0253e226d1 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -54,6 +54,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b7843d2d54..6613d3d791 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -91,6 +91,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index e5f7a1f09d..9d0db8fdfe 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -95,6 +95,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 15721c3e42..b235cba8ba 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,6 +89,8 @@ typedef enum { # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >=3D 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 232537ccea..d61ca902d3 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -85,9 +85,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS =3D=3D 32 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 22d70d431b..aca22efeb8 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -168,6 +168,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 0044ac8d78..53cfa843da 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -73,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 #if defined(__VIS__) && __VIS__ >=3D 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 6f72d4157a..e9bb1f329f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -744,8 +744,8 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: info->nr_out =3D 128 / TCG_TARGET_REG_BITS; - info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ - switch (/* TODO */ TCG_CALL_RET_NORMAL) { + info->out_kind =3D TCG_TARGET_CALL_RET_I128; + switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); @@ -833,7 +833,7 @@ static void init_call_layout(TCGHelperInfo *info) break; =20 case TCG_TYPE_I128: - switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + switch (TCG_TARGET_CALL_ARG_I128) { case TCG_CALL_ARG_EVEN: layout_arg_even(&cum); /* fall through */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d31e6c3de4..38d6e2ed21 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -54,6 +54,9 @@ #else # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +/* Note sysv arg alignment applies only to 2-word types, not more. */ +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* For some memory operations, we need a scratch that isn't R0. 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The type is not yet usable, as we have not yet added data movement ops. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg.h | 32 +++++++++++++++++++++++++ tcg/tcg.c | 60 +++++++++++++++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 18 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 7d346192ca..a996da60b5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -697,6 +697,11 @@ static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) return tcgv_i32_temp((TCGv_i32)v); } =20 +static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) +{ + return tcgv_i32_temp((TCGv_i32)v); +} + static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { return tcgv_i32_temp((TCGv_i32)v); @@ -717,6 +722,11 @@ static inline TCGArg tcgv_i64_arg(TCGv_i64 v) return temp_arg(tcgv_i64_temp(v)); } =20 +static inline TCGArg tcgv_i128_arg(TCGv_i128 v) +{ + return temp_arg(tcgv_i128_temp(v)); +} + static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); @@ -738,6 +748,11 @@ static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) return (TCGv_i64)temp_tcgv_i32(t); } =20 +static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) +{ + return (TCGv_i128)temp_tcgv_i32(t); +} + static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { return (TCGv_ptr)temp_tcgv_i32(t); @@ -860,6 +875,11 @@ static inline void tcg_temp_free_i64(TCGv_i64 arg) tcg_temp_free_internal(tcgv_i64_temp(arg)); } =20 +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + static inline void tcg_temp_free_ptr(TCGv_ptr arg) { tcg_temp_free_internal(tcgv_ptr_temp(arg)); @@ -908,6 +928,18 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return temp_tcgv_i64(t); } =20 +static inline TCGv_i128 tcg_temp_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, false); + return temp_tcgv_i128(t); +} + +static inline TCGv_i128 tcg_temp_local_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, true); + return temp_tcgv_i128(t); +} + static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offse= t, const char *name) { diff --git a/tcg/tcg.c b/tcg/tcg.c index e9bb1f329f..2ab012a095 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1251,26 +1251,45 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool t= emp_local) tcg_debug_assert(ts->base_type =3D=3D type); tcg_debug_assert(ts->kind =3D=3D kind); } else { + int i, n; + + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + n =3D 1; + break; + case TCG_TYPE_I64: + n =3D 64 / TCG_TARGET_REG_BITS; + break; + case TCG_TYPE_I128: + n =3D 128 / TCG_TARGET_REG_BITS; + break; + default: + g_assert_not_reached(); + } + ts =3D tcg_temp_alloc(s); - if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D TCG_TYPE_I64) { - TCGTemp *ts2 =3D tcg_temp_alloc(s); + ts->base_type =3D type; + ts->temp_allocated =3D 1; + ts->kind =3D kind; =20 - ts->base_type =3D type; - ts->type =3D TCG_TYPE_I32; - ts->temp_allocated =3D 1; - ts->kind =3D kind; - - tcg_debug_assert(ts2 =3D=3D ts + 1); - ts2->base_type =3D TCG_TYPE_I64; - ts2->type =3D TCG_TYPE_I32; - ts2->temp_allocated =3D 1; - ts2->temp_subindex =3D 1; - ts2->kind =3D kind; - } else { - ts->base_type =3D type; + if (n =3D=3D 1) { ts->type =3D type; - ts->temp_allocated =3D 1; - ts->kind =3D kind; + } else { + ts->type =3D TCG_TYPE_REG; + + for (i =3D 1; i < n; ++i) { + TCGTemp *ts2 =3D tcg_temp_alloc(s); + + tcg_debug_assert(ts2 =3D=3D ts + i); + ts2->base_type =3D type; + ts2->type =3D TCG_TYPE_REG; + ts2->temp_allocated =3D 1; + ts2->temp_subindex =3D i; + ts2->kind =3D kind; + } } } =20 @@ -3359,9 +3378,14 @@ static void temp_allocate_frame(TCGContext *s, TCGTe= mp *ts) case TCG_TYPE_V64: align =3D 8; break; + case TCG_TYPE_I128: case TCG_TYPE_V128: case TCG_TYPE_V256: - /* Note that we do not require aligned storage for V256. */ + /* + * Note that we do not require aligned storage for V256, + * and that we provide alignment for I128 to match V128, + * even if that's above what the host ABI requires. + */ align =3D 16; break; default: --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WRIZMZP9j9SPp1EX0fHgPhfmFfX9VpYNwtU5BnkhtFg=; b=dzEegWKN0lhR9o3FqsyRlrHUM6H3fJWmbhFz+W0s89m2HANADWVdmESrbC33slMYwR t06DIMmIR0SbKjPcG9DV2roWlaUOjEANTxHHF+kIjY7b+3RfUXudmMRcsWeG7B4hShxa 9TQBlZnxsTxQnGosARi0Y4eOZELSZ+XR51zr2wZz0uIEYYjeer8rhPxIz2gk1KQXB5g2 ozclQCH+zdkH10a9bS5qAxsclLmBZK+dBk2OO3pdbq6WLjwgyBO1RwzZQ8U9W5wZpblt EqIfi6jUlrr46AwWz34lmWNE5nTBJwYdbs+0JdV8aEXnHBC27DUCkVxtly37ZwKoO0dv wEDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WRIZMZP9j9SPp1EX0fHgPhfmFfX9VpYNwtU5BnkhtFg=; b=R6WEYr3W86ab9n/WTxBdhocwuTLLbZIZiGoh3Dh4IPssrzUk7hcAIBX0F+4gQWMllE Cg7hQY36G4zxp6YAE5JWGbLxAuYLQ9IgleFXn1fVSanJILtAYp7nDLNX9Ol/ZnO3G7nC 1Ko0ZeKx32pQwycW1i/9Ryak9o1DIkvXp0wcdeUBfI/SZbwDiNnF6/+5AjLTartby7Gs SUPOAN3P9BLMmFKtyczm8TtGCsf81rzvornnusFwiTeI+6Jpea5GwnwlskCeDQa1vsMw paNBIJlnDdrMui/QDQpClTmVvY1+S8Orwi1X5ZfFZaPgzoTQPDcSmkSUy51aEuAYxWNW Galw== X-Gm-Message-State: AFqh2kqBIINFiT9OPiApcKREcSQZYtUZ0RKvoqL4R3I1kGZyBpZ1H68h 3nVuajNXB5o0lUPkdm0ponhjUF/WNTRFepZN X-Google-Smtp-Source: AMrXdXtz0VMmNsWF4CybmuoYlPOtAwaIDDTZt15Je39VXOu3NtHzl8ury7Y6uuguMPLpHrhXHB+Lww== X-Received: by 2002:a17:902:f80d:b0:192:f6d0:6029 with SMTP id ix13-20020a170902f80d00b00192f6d06029mr14720846plb.15.1673145456385; Sat, 07 Jan 2023 18:37:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 14/36] tcg: Add basic data movement for TCGv_i128 Date: Sat, 7 Jan 2023 18:36:57 -0800 Message-Id: <20230108023719.2466341-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145544067100001 Content-Type: text/plain; charset="utf-8" Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 4 ++++ tcg/tcg-internal.h | 13 +++++++++++++ tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 79b1cf786f..c4276767d1 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -712,6 +712,10 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); =20 +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i6= 4 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 33f1d8b411..e542a4e9b7 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -117,4 +117,17 @@ extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit = code path is reachable"); extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reacha= ble"); #endif =20 +static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) +{ + /* For 32-bit, offset by 2, which may then have TCGV_{LOW,HIGH} applie= d. */ + int o =3D HOST_BIG_ENDIAN ? 64 / TCG_TARGET_REG_BITS : 0; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + +static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) +{ + int o =3D HOST_BIG_ENDIAN ? 0 : 64 / TCG_TARGET_REG_BITS; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cd1cd4e736..658cee7d6c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2745,6 +2745,26 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TC= Gv_i64 arg) tcg_gen_shri_i64(hi, arg, 32); } =20 +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg) +{ + tcg_gen_mov_i64(lo, TCGV128_LOW(arg)); + tcg_gen_mov_i64(hi, TCGV128_HIGH(arg)); +} + +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi) +{ + tcg_gen_mov_i64(TCGV128_LOW(ret), lo); + tcg_gen_mov_i64(TCGV128_HIGH(ret), hi); +} + +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src) +{ + if (dst !=3D src) { + tcg_gen_mov_i64(TCGV128_LOW(dst), TCGV128_LOW(src)); + tcg_gen_mov_i64(TCGV128_HIGH(dst), TCGV128_HIGH(src)); + } +} + /* QEMU specific operations. */ =20 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145823; cv=none; d=zohomail.com; s=zohoarc; b=AXsVcHR/TH+YkOdejXJ5UADO8I5sjMgazOb/LzBPKX6MXRxJXlV2uL4wGbtTcNC6JzUb7/2Ny3D6z4DdoLz5SVL3iauCWZRFHBdVBWTCrm8XrolepGhtKSFxolTz1RGK6hF5kCkdvctACHvCAggdUP68YJxDAC7O+rebsOV6elQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145823; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5+iMiL/8rgFPrMnNMdPuUjiub5+xvYqydBuIyCcmAyA=; b=dLOHFoASCJHo/n9K2cIkMISf9wBEicVadDHyVAQZgQ/p/VXw3cMQISRgO+G7xb5yd/sp0cikcza4ecPG4lVaXTlrFmoKMZIf3k0g4ovi4APJEhoKZpZ+wIsJ7PAqZ4TjyvAQt+Sc8Fq2vf5oUSdMixfvTvAwAw1cukURw4xb51A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145823586179.6883920318436; Sat, 7 Jan 2023 18:43:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZp-0005Mq-Ml; Sat, 07 Jan 2023 21:38:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZd-0005Bb-Rq for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:13 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ4-0004ce-MW for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:13 -0500 Received: by mail-pj1-x1030.google.com with SMTP id b9-20020a17090a7ac900b00226ef160dcaso4079707pjl.2 for ; Sat, 07 Jan 2023 18:37:38 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5+iMiL/8rgFPrMnNMdPuUjiub5+xvYqydBuIyCcmAyA=; b=CQucPtp99wrW052p96VDpp74jcLL4GmB1ZC6pQGJp+vK2smTP0KDLMPGrAnsLs/fyy 0+wA7ya4iP+839DrMyaz2p9UWNSfOgyyfDVUZiD6PLatIOejf48X+8ber/WhS5jiQkLn ryB2FsuzB0CYqEtufP4ciFHfYy8UBv29wbgyJ84OZnnK/fVABvhmQKh6F12eHE/C+TjY RRWHBw94279T50rVpLFTgPq8WMzG+4ABOOc4NZG3GSh13ouXNG6a4jx6H1+s29HCQHOW wG49SEPYpj4Zj64Xh8zsxDXKmfIQ16NLM+RS95pcjEnjSSIWclUCTn611Mw3zNJu74rA Iscw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5+iMiL/8rgFPrMnNMdPuUjiub5+xvYqydBuIyCcmAyA=; b=GqtOPUPbxMHRp4wY6942hLofDaGJy67E1WRwGe+ahmnWpA0TS6uC4/KCi7K15GSZjH m989vuNFJnnz9p7HC1SdPvzoif8FNe5DQ6+JB8JLDpWXXGW6Qfb8CJaEtLAXbbn7/V/p Nd1kQkoGBGPn/LQcQw+gi12Ubdat64huER9RaV6MG1FWOMkwV0ahaQ4CR0P8L/m/kBBE 3iQNEZHjLHu4RgSI/4O7KtYsTmTqcyh6OcRSY6QG+VvkyOKCYFpJotnsjUONcL931ZDR tu20gqP0V+4RIHfACXZtLHwW8vWSOs3FvrRZqbdekkGSYpa8Zk91tWhDls0PejvZsRX3 Ndlw== X-Gm-Message-State: AFqh2kptoES7+PvLRrh8vFYpt5+m/pLdEeHYloC7LZeVSTZL2GpfNDB+ aU3JhlAxqgRbzXJLw+9cRIS8bFRnuxzgWAbz X-Google-Smtp-Source: AMrXdXsIrKReg7nYqoCfO3iRpS0vB/7XZJPXG6Rtt7BwVMGlK4qdl0rt0gB83CT22ZCddpt3k2V4KA== X-Received: by 2002:a17:902:e846:b0:189:f990:24af with SMTP id t6-20020a170902e84600b00189f99024afmr88812058plg.20.1673145457430; Sat, 07 Jan 2023 18:37:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 15/36] tcg: Add guest load/store primitives for TCGv_i128 Date: Sat, 7 Jan 2023 18:36:58 -0800 Message-Id: <20230108023719.2466341-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145824966100003 Content-Type: text/plain; charset="utf-8" These are not yet considering atomicity of the 16-byte value; this is a direct replacement for the current target code which uses a pair of 8-byte operations. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 10 +++ include/tcg/tcg-op.h | 2 + accel/tcg/cputlb.c | 112 +++++++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 66 ++++++++++++++++++++ tcg/tcg-op.c | 134 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 324 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d0c7c0d5fe..09b55cc0ee 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -220,6 +220,11 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra); =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); + void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, MemOpIdx oi, uintptr_t ra); void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, @@ -235,6 +240,11 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, ui= nt32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); + uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index c4276767d1..e5f5b63c37 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -845,6 +845,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); =20 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4948729917..79101306a3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2187,6 +2187,64 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr a= ddr, return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + h =3D helper_be_ldq_mmu(env, addr, new_oi, ra); + l =3D helper_be_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + l =3D helper_le_ldq_mmu(env, addr, new_oi, ra); + h =3D helper_le_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + /* * Store Helpers */ @@ -2541,6 +2599,60 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong = addr, uint64_t val, cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + helper_be_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int mmu_idx =3D get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); + a_bits =3D get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi =3D make_memop_idx(mop, mmu_idx); + + helper_le_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + #include "ldst_common.c.inc" =20 /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a8eb63ab96..ae67d84638 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1031,6 +1031,42 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr a= ddr, return ret; } =20 +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_BE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (!HOST_BIG_ENDIAN) { + ret =3D bswap128(ret); + } + return ret; +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_LE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (HOST_BIG_ENDIAN) { + ret =3D bswap128(ret); + } + return ret; +} + void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, MemOpIdx oi, uintptr_t ra) { @@ -1115,6 +1151,36 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr,= uint64_t val, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_BE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (!HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_LE); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) { uint32_t ret; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 658cee7d6c..55ecedb66f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3107,6 +3107,140 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, T= CGArg idx, MemOp memop) } } =20 +static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) +{ + MemOp mop_1 =3D orig, mop_2; + + tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); + + /* Use a memory ordering implemented by the host. */ + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (orig & MO_BSWAP)) { + mop_1 &=3D ~MO_BSWAP; + } + + /* Reduce the size to 64-bit. */ + mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; + + /* Retain the alignment constraints of the original. */ + switch (orig & MO_AMASK) { + case MO_UNALN: + case MO_ALIGN_2: + case MO_ALIGN_4: + mop_2 =3D mop_1; + break; + case MO_ALIGN_8: + /* Prefer MO_ALIGN+MO_64 to MO_ALIGN_8+MO_64. */ + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + mop_2 =3D mop_1; + break; + case MO_ALIGN: + /* Second has 8-byte alignment; first has 16-byte alignment. */ + mop_2 =3D mop_1; + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN_16; + break; + case MO_ALIGN_16: + case MO_ALIGN_32: + case MO_ALIGN_64: + /* Second has 8-byte alignment; first retains original. */ + mop_2 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + break; + default: + g_assert_not_reached(); + } + ret[0] =3D mop_1; + ret[1] =3D mop_2; +} + +void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + /* + * Since there are no global TCGv_i128, there is no visible state + * changed if the second load faults. Load directly into the two + * subwords. + */ + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(x, x); + } + + addr_p8 =3D tcg_temp_new(); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); + tcg_temp_free(addr_p8); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(y, y); + } + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_R); +} + +void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + addr_p8 =3D tcg_temp_new(); + if ((mop[0] ^ memop) & MO_BSWAP) { + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_bswap64_i64(t, x); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); + tcg_gen_bswap64_i64(t, y); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); + tcg_temp_free_i64(t); + } else { + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + } + tcg_temp_free(addr_p8); + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_W); +} + static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) { switch (opc & MO_SSIZE) { --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146315; cv=none; d=zohomail.com; s=zohoarc; b=aGeyJcGr4mWiYBLahbxVhCAo+vRdS6G4ll8wiKDwTKpZ0Vx49RstwlIZrJQlgYBusp5Wuv/9veXCNXxdreA6maEhg2POCUa0W6+QIbCvfs/frfWyGOWzWN6UUqSX/VVhzl8J9mDagA6sTVgKQYjw+pXoOkWdNAME17GYEDO946o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146315; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tmU0MjgiKsSxPUHRGzRVInhdiWEFNbDXapXPwryhCsg=; b=REffql+OwbXE43W8fN3n3g0hyCHTV7tN69pfQT8GzaX7sAWbT4iSxxlB3C8Z9bBugoI90IqoFfBXg+dsXJ5yHBZEN5UYKIzG8GBTref9ihBg8iruc/L1h+Xwqot1CP0GNofkwpgT/pWak/I5b10kCfkH4j47xX2wvwtZMesxM20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146315626593.1694890409071; Sat, 7 Jan 2023 18:51:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZq-0005O3-8M; Sat, 07 Jan 2023 21:38:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZk-0005IW-KZ for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:21 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ5-0004d3-Kz for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:20 -0500 Received: by mail-pj1-x1033.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso9256189pjp.4 for ; Sat, 07 Jan 2023 18:37:39 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tmU0MjgiKsSxPUHRGzRVInhdiWEFNbDXapXPwryhCsg=; b=dVPjSWSVfw3dl+K0WrjZQUtWVtasW1reVIEELlM9F/TvOFEnsRyHTV7neQKKF0yDq0 zWZ7VC8avBIbay8SO1uxz1pN7XNarj00p0ljqQio0+igPCW075mN1y3Kk+BVFZ/TVkl1 H14q04qgtIopeXhtxBT82aELAfULRloENIut2Uk/8piyu4a+jMIvsLkCTj06VNuJOcGA vQtUBveoUTqvGYhZkytToXTi/1sweQfKDUV4TOGHFkFbI7Ddby6iIhVB6fkmJLJV8EsH 2Q05RxM9udcCSC493hceEzCq3fyyQWSKrpPuAgOZ7a6VATnDEo+9zDl6MbsEeJwfpb2W 1z/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tmU0MjgiKsSxPUHRGzRVInhdiWEFNbDXapXPwryhCsg=; b=e+YCE/APvS0BSxpQ0egAOICPWVmqKR7f7XCLhQffy6m6a7gBCFKI2UQ7vaosmbr1Kz ihoE3s5VeK/0cD6RbgONERSlZRW5famnUV5mzEyU4/1xfZ4xcGbZzmfWCw6j2ZLHYxSR iuS21rGWwVSap1YEkOKlLBKy5MZWGP7wuVsZeLCuLaNRD2EZg1qSxYOZFvYsFcSpShGY mgYs5UdZ/bJLbhs9TLK2diMwMHKS7QduC+s48ZbrHAecwcCyRBwDcR4a76iGhyNoitiF 09NFN98mvr+CGxXBScH2EvXNnpq5IHyWM0CJIf3NH+2iUyB5vE/C2uwsvyQNQZ5LMtwm QfKg== X-Gm-Message-State: AFqh2kpEheiPgBYr1/i3eYPzCrJHFlrRJkDMieYVMsBuABr7J6FIs4sS PSwY/pPRDEugz16kkFVJzh0+ShYvGHcm5x58 X-Google-Smtp-Source: AMrXdXtQAF1iIe2yb+kn0a3+q+s7wVHxHtEe1ezf/KHN5Ycay/z3DWneG/bBUmfvL2X0omsUa/PkLA== X-Received: by 2002:a17:902:8e86:b0:192:b43e:272 with SMTP id bg6-20020a1709028e8600b00192b43e0272mr28292109plb.53.1673145458376; Sat, 07 Jan 2023 18:37:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Date: Sat, 7 Jan 2023 18:36:59 -0800 Message-Id: <20230108023719.2466341-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146317942100001 Content-Type: text/plain; charset="utf-8" This will allow targets to avoid rolling their own. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 11 +++++ include/tcg/tcg-op.h | 5 +++ tcg/tcg-op.c | 85 +++++++++++++++++++++++++++++++++++ accel/tcg/atomic_common.c.inc | 45 +++++++++++++++++++ 4 files changed, 146 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 37cbd722bf..e141a6ab24 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -55,6 +55,17 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64, i32) #endif +#ifdef CONFIG_CMPXCHG128 +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +#endif + +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) =20 #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e5f5b63c37..31bf3d287e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -907,6 +907,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i= 32, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); + +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); =20 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 55ecedb66f..66f9c894ad 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3293,6 +3293,8 @@ typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env,= TCGv, TCGv_i32, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv_i64, TCGv_i32); +typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, + TCGv_i128, TCGv_i128, TCGv_i32); typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, @@ -3303,6 +3305,11 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env= , TCGv, #else # define WITH_ATOMIC64(X) #endif +#ifdef CONFIG_CMPXCHG128 +# define WITH_ATOMIC128(X) X, +#else +# define WITH_ATOMIC128(X) +#endif =20 static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { [MO_8] =3D gen_helper_atomic_cmpxchgb, @@ -3312,6 +3319,8 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP= ) + 1] =3D { [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) + WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) + WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, @@ -3410,6 +3419,82 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv = addr, TCGv_i64 cmpv, } } =20 +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 c= mpv, + TCGv_i128 newv, TCGArg idx, MemOp memo= p) +{ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Inline expansion below is simply too large for 32-bit hosts. */ + gen_atomic_cx_i128 gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE + ? gen_helper_nonatomic_cmpxchgo_le=20 + : gen_helper_nonatomic_cmpxchgo_be); + MemOpIdx oi =3D make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + } else { + TCGv_i128 oldv =3D tcg_temp_new_i128(); + TCGv_i128 tmpv =3D tcg_temp_new_i128(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + + tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); + + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); + + /* tmpv =3D equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); + } +} + +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, + TCGv_i128 newv, TCGArg idx, MemOp memop) +{ + gen_atomic_cx_i128 gen; + + if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); + return; + } + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } + + gen_helper_exit_atomic(cpu_env); + + /* + * Produce a result for a well-formed opcode stream. This satisfies + * liveness for set before used, which happens before this dead code + * is removed. + */ + tcg_gen_movi_i64(TCGV128_LOW(retv), 0); + tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); +} + static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6602d7689f..8f2ce43ee6 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -55,8 +55,53 @@ CMPXCHG_HELPER(cmpxchgq_be, uint64_t) CMPXCHG_HELPER(cmpxchgq_le, uint64_t) #endif =20 +#ifdef CONFIG_CMPXCHG128 +CMPXCHG_HELPER(cmpxchgo_be, Int128) +CMPXCHG_HELPER(cmpxchgo_le, Int128) +#endif + #undef CMPXCHG_HELPER =20 +Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS =3D=3D 32 + uintptr_t ra =3D GETPC(); + Int128 oldv; + + oldv =3D cpu_ld16_be_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_be_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + +Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS =3D=3D 32 + uintptr_t ra =3D GETPC(); + Int128 oldv; + + oldv =3D cpu_ld16_le_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_le_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + #define ATOMIC_HELPER(OP, TYPE) \ TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, target_ulong addr, \ TYPE val, uint32_t oi) \ --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145819; cv=none; d=zohomail.com; s=zohoarc; b=hkaeoZX/EnNTxArT5n1R+lC+VxOp74I27HGtVL7yu5ijBGww1e4HyLa3jgwqxTcuHVIPF0F8itXSeoxMEyaV1yvuJCwFJXFCLy6x9lP1cyCGVROkvXIn9B9iJvTs23gBWg7ssZ4y/oRai/IWNv768NZOO8VMZapmROCgHB+uD6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145819; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dmbx+CEV8/se/3fSeHkhg92bMZKxyEmSGS7vO3Es65k=; b=bsEzsmtgrPlm8tkJvfNnFOQ+bQ/wYI85lROVAtsWyOmCYW0mnkLZxI84ri8LaWyyK9Uw7YwVCdMuoZApwrF/fZ4J/5QTJFgHlFFQhN5hdacBJjleYDPXIckbNz+GFbEmENtYg3iMGDtLAxc8i2YvS4ZQ1wgAIR219Ozla/wonig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145819834974.5865022753486; Sat, 7 Jan 2023 18:43:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZt-0005S9-2Z; Sat, 07 Jan 2023 21:38:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZk-0005IX-PD for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:22 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ7-0004dl-47 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:20 -0500 Received: by mail-pj1-x1032.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so9292383pjj.2 for ; Sat, 07 Jan 2023 18:37:40 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dmbx+CEV8/se/3fSeHkhg92bMZKxyEmSGS7vO3Es65k=; b=V7TA51xu0YrekvE5bYlUMOc9bVTyaRXvKmshwELH4W3Yz8wv+Jl47GOYNQAITlBu1s MpLcLBZhsD4J7IDz1foZtUn88h226C50XvfNM0GemIPzynwRMUTPRyyRoY9K5+MCsbj7 bow9UuU5lo+K53si936Dk1rG3lt6oNs0qDm9zdRejb2vN+XveeOXqcjZx1nZ4Ua9ynVw 8cTFWpGP+FCP3v3tWOboVYeOzn9m3TEjQZb2I+bmpDZuq1TsPC62qN7HaHHUTgXljYZd +vDvS9VwmPrXG7mqSvbFvUsId45cNnxB4tOi/+T9hYgV3coEIupFbE2/dYDG4hibN4gc jNnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmbx+CEV8/se/3fSeHkhg92bMZKxyEmSGS7vO3Es65k=; b=Pi9+hEtc7Lni2tFDB2U0I3Sj8dJTAa5+0Pbu6stZ/L1+8fiUnlcIbXG6vRZtgcs7X+ ZfoeTYDcelWPHqr+Y560f92ItveVWEG+J/XTlmurWJzK54R7RojUPEJ8LRA0XVE0Jxwb POKq9Hi6wNAA0Oy3DSBh2nfHfvwPAqkRQzA8EphL03cRtpYmTggJpMlTdc4Mf+9MHv0d AgYYR9d+VA5YiLCyRf7e3Wq213XCamTExocq2eCLgG9NZwipCvuyU7P8OYfA1VhAT0uh HrP/eNtIwohB3lg9GzQbj314jOTvD/cAro6k6djK4LgZEySlpJsvNPRVJOoa4kOI6UdF K+iQ== X-Gm-Message-State: AFqh2krxNGtVsJRor8KRRfAFcusfwMKTeYgQ2mfMA7iVUm8S+Tn3qJd4 MBVKOHCg0z0gh59mSK8mXVF2PG+LVRU1u5u9 X-Google-Smtp-Source: AMrXdXt23+d8sCttNfmCtj752BqPiwctOrcmTTLOW01Ch8j+GU86BHQunP6wor0juB0QByLoo9PCsA== X-Received: by 2002:a17:902:8688:b0:192:fc9c:a238 with SMTP id g8-20020a170902868800b00192fc9ca238mr10509389plo.66.1673145459591; Sat, 07 Jan 2023 18:37:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} Date: Sat, 7 Jan 2023 18:37:00 -0800 Message-Id: <20230108023719.2466341-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145820947100003 Content-Type: text/plain; charset="utf-8" Normally this is automatically handled by the CF_PARALLEL checks with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special case of !PREFIX_LOCK where it always wants the non-atomic version. Split these out so that x86 does not have to roll its own. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ++ tcg/tcg-op.c | 154 +++++++++++++++++++++++++++---------------- 2 files changed, 101 insertions(+), 57 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 31bf3d287e..839d91c0c7 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -910,6 +910,10 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i= 64, TCGv_i64, void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); =20 +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, + TCGArg, MemOp); +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, + TCGArg, MemOp); void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 66f9c894ad..e7e4951a3c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3323,82 +3323,122 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BS= WAP) + 1] =3D { WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, + TCGv_i32 newv, TCGArg idx, MemOp memop) +{ + TCGv_i32 t1 =3D tcg_temp_new_i32(); + TCGv_i32 t2 =3D tcg_temp_new_i32(); + + tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_temp_free_i32(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, t1, memop); + } else { + tcg_gen_mov_i32(retv, t1); + } + tcg_temp_free_i32(t1); +} + void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, TCGv_i32 newv, TCGArg idx, MemOp memop) { - memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen_atomic_cx_i32 gen; + MemOpIdx oi; =20 if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { - TCGv_i32 t1 =3D tcg_temp_new_i32(); - TCGv_i32 t2 =3D tcg_temp_new_i32(); - - tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); - tcg_temp_free_i32(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, t1, memop); - } else { - tcg_gen_mov_i32(retv, t1); - } - tcg_temp_free_i32(t1); - } else { - gen_atomic_cx_i32 gen; - MemOpIdx oi; - - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, retv, memop); - } + tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); + return; } + + memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, retv, memop); + } +} + +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, + TCGv_i64 newv, TCGArg idx, MemOp memop) +{ + TCGv_i64 t1, t2; + + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } + return; + } + + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + + tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_temp_free_i64(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(retv, t1, memop); + } else { + tcg_gen_mov_i64(retv, t1); + } + tcg_temp_free_i64(t1); } =20 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, TCGv_i64 newv, TCGArg idx, MemOp memop) { - memop =3D tcg_canonicalize_memop(memop, 1, 0); - if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { - TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 t2 =3D tcg_temp_new_i64(); + tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); + return; + } =20 - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); - tcg_temp_free_i64(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, t1, memop); - } else { - tcg_gen_mov_i64(retv, t1); - } - tcg_temp_free_i64(t1); - } else if ((memop & MO_SIZE) =3D=3D MO_64) { -#ifdef CONFIG_ATOMIC64 + if ((memop & MO_SIZE) =3D=3D MO_64) { gen_atomic_cx_i64 gen; - MemOpIdx oi; =20 + memop =3D tcg_canonicalize_memop(memop, 1, 0); gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } =20 - oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); -#else gen_helper_exit_atomic(cpu_env); - /* Produce a result, so that we have a well-formed opcode stream - with respect to uses of the result in the (dead) code following= . */ + + /* + * Produce a result for a well-formed opcode stream. This satisfi= es + * liveness for set before used, which happens before this dead co= de + * is removed. + */ tcg_gen_movi_i64(retv, 0); -#endif /* CONFIG_ATOMIC64 */ + return; + } + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } } else { TCGv_i32 c32 =3D tcg_temp_new_i32(); TCGv_i32 n32 =3D tcg_temp_new_i32(); --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145813; cv=none; d=zohomail.com; s=zohoarc; b=AKEja8YiVA/Zv7B/btYyqoqB2TFZe2uSEcheYetEQLJvOKCBPdWpTtm1F5ldI4F8h3G/Be106liekDZmwG3QGSkV8Q+VxJ3xfuuU6YAOQhO4zVmnb+RKyTXXXlgdmTbXtNg2jy/5/g3C1Wk8G3YF4w9fuZ7YPv85zLx3DbknKZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145813; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fBe81AYf+h+ZBpFhnMwhRAiDvhJXmvmqR7+o6P3dQKY=; b=dwMWYKOJJ2h8nTUYFDDvL1O7c7o7JaPg547JsdL8t1xj1w3LLbz24oxxdICILcqZWptepQpsa0qqCb4MmyYRi4mpIfip0NuIsEBqGphjMqrrVkSP0KaohRAyxuJhVEs/MF1mRbia/cDClPtqIh9YiNx1NKwb7Ti2TGh5e6tlTls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673145813752496.38692556228557; Sat, 7 Jan 2023 18:43:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZr-0005Pi-Bu; Sat, 07 Jan 2023 21:38:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZn-0005Iv-8S for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:24 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ8-0004eU-3M for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:23 -0500 Received: by mail-pj1-x102c.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso9256242pjp.4 for ; Sat, 07 Jan 2023 18:37:41 -0800 (PST) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145814967100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-2-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 6 --- target/arm/helper-a64.c | 104 ------------------------------------- target/arm/translate-a64.c | 60 ++++++++++++--------- 3 files changed, 35 insertions(+), 135 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b706571bb..94065d1917 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,12 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16= , ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 77a8502b6b..7dbdb2c233 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,110 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val= , uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); - Int128 newv =3D int128_make128(new_lo, new_hi); - Int128 oldv; - uintptr_t ra =3D GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi0 =3D make_memop_idx(MO_LEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 =3D make_memop_idx(MO_LEUQ, mem_idx); - - o0 =3D cpu_ldq_le_mmu(env, addr + 0, oi0, ra); - o1 =3D cpu_ldq_le_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - success =3D int128_eq(oldv, cmpv); - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - Int128 cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val= ); - Int128 newv =3D int128_make128(new_hi, new_lo); - Int128 oldv; - uintptr_t ra =3D GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi0 =3D make_memop_idx(MO_BEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 =3D make_memop_idx(MO_BEUQ, mem_idx); - - o1 =3D cpu_ldq_be_mmu(env, addr + 0, oi0, ra); - o0 =3D cpu_ldq_be_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); - - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); - newv =3D int128_make128(new_hi, new_lo); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - success =3D int128_eq(oldv, cmpv); - return !success; -} - /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2ee171f249..dffd7ee737 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2580,32 +2580,42 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (!HAVE_CMPXCHG128) { - gen_helper_exit_atomic(cpu_env); - /* - * Produce a result so we have a well-formed opcode - * stream when the following (dead) code uses 'tmp'. - * TCG will remove the dead ops for us. - */ - tcg_gen_movi_i64(tmp, 0); - } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } - } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, - cpu_reg(s, rt), cpu_reg(s, rt2)= ); + TCGv_i128 t16 =3D tcg_temp_new_i128(); + TCGv_i128 c16 =3D tcg_temp_new_i128(); + TCGv_i64 a, b; + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt), cpu_reg(s, rt= 2)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_val, + cpu_exclusive_high); + } else { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt2), cpu_reg(s, r= t)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_high, + cpu_exclusive_val); + } + + tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, + get_mem_index(s), + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(c16); + + a =3D tcg_temp_new_i64(); + b =3D tcg_temp_new_i64(); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(a, b, t16); + } else { + tcg_gen_extr_i128_i64(b, a, t16); + } + + tcg_gen_xor_i64(a, a, cpu_exclusive_val); + tcg_gen_xor_i64(b, b, cpu_exclusive_high); + tcg_gen_or_i64(tmp, a, b); + tcg_temp_free_i64(a); + tcg_temp_free_i64(b); + tcg_temp_free_i128(t16); + + tcg_gen_setcondi_i64(TCG_COND_NE, tmp, tmp, 0); } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145978; cv=none; d=zohomail.com; s=zohoarc; b=Akqrj7tWE5WDidpBXYjC3H+EVYaYQSIxn+Sv67K+R+P3chi7ikk1MMfk9NGZGXwxW+4p+xMke6V26WMMdER9oHCv/VwtsJUu5g16DLkUSDICmoZf1kVoj9n7aMdL4QdIL2+VlMMf8Tj9tqqppDylnz7u5t+hIG8NRaNRvNjBtt0= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145979672100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-3-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 2 -- target/arm/helper-a64.c | 43 --------------------------- target/arm/translate-a64.c | 61 +++++++++++--------------------------- 3 files changed, 18 insertions(+), 88 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 94065d1917..ff56807247 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,8 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16,= ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) -DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7dbdb2c233..0972a4bdd0 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,49 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Writes back the old data into Rs. */ -void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs] =3D int128_getlo(oldv); - env->xregs[rs + 1] =3D int128_gethi(oldv); -} - -void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_hi, uint64_t new_lo) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs + 1] =3D int128_getlo(oldv); - env->xregs[rs] =3D int128_gethi(oldv); -} - /* * AdvSIMD half-precision */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dffd7ee737..067426baef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2688,53 +2688,28 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, tcg_gen_extr32_i64(s2, s1, cmp); } tcg_temp_free_i64(cmp); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 tcg_rs =3D tcg_constant_i32(rs); - if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } - } else { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp =3D DISAS_NORETURN; - } } else { - TCGv_i64 d1 =3D tcg_temp_new_i64(); - TCGv_i64 d2 =3D tcg_temp_new_i64(); - TCGv_i64 a2 =3D tcg_temp_new_i64(); - TCGv_i64 c1 =3D tcg_temp_new_i64(); - TCGv_i64 c2 =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_constant_i64(0); + TCGv_i128 cmp =3D tcg_temp_new_i128(); + TCGv_i128 val =3D tcg_temp_new_i128(); =20 - /* Load the two words, in memory order. */ - tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, - MO_64 | MO_ALIGN_16 | s->be_data); - tcg_gen_addi_i64(a2, clean_addr, 8); - tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(val, t1, t2); + tcg_gen_concat_i64_i128(cmp, s1, s2); + } else { + tcg_gen_concat_i64_i128(val, t2, t1); + tcg_gen_concat_i64_i128(cmp, s2, s1); + } =20 - /* Compare the two words, also in memory order. */ - tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); - tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); - tcg_gen_and_i64(c2, c2, c1); + tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(val); =20 - /* If compare equal, write back new data, else write back old data= . */ - tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); - tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); - tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); - tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); - tcg_temp_free_i64(a2); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - - /* Write back the data from memory to Rs. */ - tcg_gen_mov_i64(s1, d1); - tcg_gen_mov_i64(s2, d2); - tcg_temp_free_i64(d1); - tcg_temp_free_i64(d2); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(s1, s2, cmp); + } else { + tcg_gen_extr_i128_i64(s2, s1, cmp); + } + tcg_temp_free_i128(cmp); } } =20 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=VbUwq7tlCgfO36Oth8TSVLgJMqybrSeTGcCl1IdamNJ23TJWhQ4pTLvHnSb03OwH6J Mm/6nx+5eD3sc+wxXLs71NKAX1IgVAkWjZk92johrHQn6y0JRUeOZZ3Sq9iR+MzaO7u5 Bw462YzSnUIF4NKdYRk5WS+E2kKtrY58N6p7QjB+240Bp0jBsE2pjy74amXiYv69jok6 6G8MSAnOLenX4K9LeF8dw47SvoZfwYBSkhi2jgZ2lBn9Em+xBbFRHrTDoD22KkeFKJbh WagiRbfFpyu4UKiDpkcb9rZPKfft/l1xAjARHDOs9Wrv9AupBbtOf6hh3J/f8chlq7Ay rXYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=rz+M783twKS0mL7mIMfkEPjIhRDsVyhfEF/Ww9MdBttO+iQZPV6fCo/ZdXYbZtiKkp CSXnvAhBKRBwHSGVt3Hssmf5V71cgq+eK/z2QkTPWotIb1M8mPJllbZl3BAkjQbUi2sr YXfceTg64JodftBm57ye0Zc4x49eW7AFTOCtJhfLrpKlVZgW9dNlnXPmSbtCm9WEALco 6Qx5XZSWEiRKjzusi8PWbz90KBhVJZSd7R37Ie8t1PG1xFcdatnYnK4HYFJA/6XSOyCn IGNKOs0W7T37EB3oriCoBU1BylQ4t8Kl68TOod8ZVOFGpuCyXoWd2JYEGPM60sQckHFG sG6g== X-Gm-Message-State: AFqh2kqrX2egtIyWSJUjgVdsc304QvzSHV8pvcrUDWltTHFXUjNp2pri 1DOfmWTGdV/t8wyRlITeFVtiWCVfVAXLEo6/ X-Google-Smtp-Source: AMrXdXss8BGh5z3qj8f331v9I9FqYqmKAcV0MdGfTWZIzcd4RsPN3FtitSKJFZnDvXI4KVFEPADw+w== X-Received: by 2002:a17:902:c10c:b0:192:b5b1:eb1a with SMTP id 12-20020a170902c10c00b00192b5b1eb1amr29033572pli.69.1673145462728; Sat, 07 Jan 2023 18:37:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 20/36] target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX Date: Sat, 7 Jan 2023 18:37:03 -0800 Message-Id: <20230108023719.2466341-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146239667100002 Content-Type: text/plain; charset="utf-8" Note that the previous direct reference to reserve_val, - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))); was incorrect because all references should have gone through cpu_reserve_val. Create a cpu_reserve_val2 tcg temp to fix this. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20221112061122.2720163-2-richard.henderson@linaro.org> --- target/ppc/helper.h | 2 - target/ppc/mem_helper.c | 44 ----------------- target/ppc/translate.c | 102 ++++++++++++++++++---------------------- 3 files changed, 47 insertions(+), 101 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 8dd22a35e4..0beaca5c7a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -818,6 +818,4 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index d1163f316c..1578887a8f 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -413,50 +413,6 @@ void helper_stq_be_parallel(CPUPPCState *env, target_u= long addr, val =3D int128_make128(lo, hi); cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } - -uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success =3D false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr =3D=3D env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success =3D int128_eq(oldv, cmpv); - } - env->reserve_addr =3D -1; - return env->so + success * CRF_EQ_BIT; -} - -uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success =3D false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr =3D=3D env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); - newv =3D int128_make128(new_lo, new_hi); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success =3D int128_eq(oldv, cmpv); - } - env->reserve_addr =3D -1; - return env->so + success * CRF_EQ_BIT; -} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index edb3daa9b5..1c17d5a558 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -72,6 +72,7 @@ static TCGv cpu_cfar; static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_reserve_val; +static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; =20 @@ -141,8 +142,11 @@ void ppc_translate_init(void) offsetof(CPUPPCState, reserve_addr), "reserve_addr"); cpu_reserve_val =3D tcg_global_mem_new(cpu_env, - offsetof(CPUPPCState, reserve_val), - "reserve_val"); + offsetof(CPUPPCState, reserve_val= ), + "reserve_val"); + cpu_reserve_val2 =3D tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, reserve_va= l2), + "reserve_val2"); =20 cpu_fpscr =3D tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, fpscr), "fpscr"); @@ -3998,78 +4002,66 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { + TCGLabel *lab_fail, *lab_over; int rs =3D rS(ctx->opcode); - TCGv EA, hi, lo; + TCGv EA, t0, t1; + TCGv_i128 cmp, val; =20 if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } =20 + lab_fail =3D gen_new_label(); + lab_over =3D gen_new_label(); + gen_set_access_type(ctx, ACCESS_RES); EA =3D tcg_temp_new(); gen_addr_reg_index(ctx, EA); =20 + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_temp_free(EA); + + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + /* Note that the low part is always in RS+1, even in LE mode. */ - lo =3D cpu_gpr[rs + 1]; - hi =3D cpu_gpr[rs]; + tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); =20 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); - if (ctx->le_mode) { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } else { - gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } - tcg_temp_free_i32(oi); - } else { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } - tcg_temp_free(EA); - } else { - TCGLabel *lab_fail =3D gen_new_label(); - TCGLabel *lab_over =3D gen_new_label(); - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + tcg_temp_free_i128(cmp); =20 - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_temp_free(EA); + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + tcg_gen_extr_i128_i64(t1, t0, val); + tcg_temp_free_i128(val); =20 - gen_qemu_ld64_i64(ctx, t0, cpu_reserve); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))= ); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); =20 - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_ld64_i64(ctx, t0, t0); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val) - : offsetof(CPUPPCState, reserve_val2)= )); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(t0, t0, cpu_so); + tcg_gen_trunc_tl_i32(cpu_crf[0], t0); + tcg_temp_free(t0); =20 - /* Success */ - gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); + tcg_gen_br(lab_over); + gen_set_label(lab_fail); =20 - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); - tcg_gen_br(lab_over); + /* + * Address mismatch implies failure. But we still need to provide + * the memory barrier semantics of the instruction. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); =20 - gen_set_label(lab_fail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(lab_over); - tcg_gen_movi_tl(cpu_reserve, -1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } + gen_set_label(lab_over); + tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */ =20 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146662; cv=none; d=zohomail.com; s=zohoarc; b=Gta6g9DlFI7mxLVlNbb+Qqa7E0n0D/YdAoO7Gn87AxsWEBUKfTcOLfC48EC4J8SCBZq6UyALHDZHakh2ZW2oPi5HdqoBk2Wj+GEslJuYou6XnLWGumwKVBobrlM8B9WCJfxzVEPDJO6FvEtY+8NwGHvKtbREWtu2GGIcehEy/F8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146662; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=Ui9E+qqcSpiBT/KPNVuZruLdG67AKEiFJf6K+nnR4f7m3wGBew0vvFtvFL7pUmVn2cs7KOPeXbwN5eDjnNx3jeFlAgrN3eRqj89eT6UZXWTUUobhor5dCOAajNB+wJseoNPUlnwvzRDuEmCAvMgpXFx6PRXaUWXsl9kC3sUM+PI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146662875287.2174057712182; Sat, 7 Jan 2023 18:57:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZx-0005aD-35; Sat, 07 Jan 2023 21:38:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZu-0005UP-Ah for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:30 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZA-0004gD-UI for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:30 -0500 Received: by mail-pj1-x102d.google.com with SMTP id l1-20020a17090a384100b00226f05b9595so3801468pjf.0 for ; Sat, 07 Jan 2023 18:37:44 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=OJiP8Km0LIo65GowqB6hEQC0cb6+H2GTFuEr23RyvHYc5n9ACypQTLSyh1I7LHGWFi D0kr+Bl4emeiYv/9tL8pXEMmZZnZt9633B7xoXfl/wwu0D1+tcoiid9nF2Fs2wa/HaPs 2Y8hUzAeJnwRCID5Dw9E4iJT6ZAzVVgJSu8IpKnoVdmRb82hCbKM97WeVDCBsDQQmrEQ +a7mmzMp/WGrn+1eIb21gCNp9W/3UjCdMFIl0gA8qcZ9GG6q5bzgpZzV+iWuszcxlx75 W4scD1e2MWM0F+aDAxwxHA0waA5KY3VClZmpUHfTkZymNVLGG+pYUchfmZ0kstUzCesX Q1Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lE4xtEA+pGCE8llxbq4kNT+2kFoTqQa5IGjt6U1bFuE=; b=XLAiHSciCAf12f1KPhNPkrLUzRQuKY6un5rfImzS8eSr0sqGBYn4H6CsIryoZB3Z0O TWi0twqDZ/qfEVwLYIoClIDx2wio80Yqowh8QeQEyUBFKZBbRCMiRB9PTlnC7h0sxCPg Hu918CPBBwVAo0VfskSJF53MZq6wfepPTI1All5a+J9swfN6DI9t/s4ELb4RJUqQu9Nm LYvASkV9o598KBKufcjrEywSvehKQd4ghZg88HqdZQy84mOtcSuCdXI44NX+HrD72qJ8 FBpSqglK4P25Det2f9Q/UGiMJw2jl7xJOazoXInMBR3fvbxtsHzi0TKNB90X2UHBdNNQ /HWQ== X-Gm-Message-State: AFqh2kqdB38Fo0dVi2KIEf0HXA5l4CePIBorzKoNNYpK8jQGXo8ZKcTP W92+RC9rJRJh8EikCt3oG+RAXd9gLSg2SasU X-Google-Smtp-Source: AMrXdXsiBsglispZb5gp3AG7BUWzgtlj9mgUmnLWokD2UGSwnX7/QWTypmlkm+kHmrYBENDJZgWHFg== X-Received: by 2002:a17:902:a9c1:b0:193:1557:457c with SMTP id b1-20020a170902a9c100b001931557457cmr5559835plr.62.1673145463667; Sat, 07 Jan 2023 18:37:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich Subject: [PATCH v4 21/36] tests/tcg/s390x: Add div.c Date: Sat, 7 Jan 2023 18:37:04 -0800 Message-Id: <20230108023719.2466341-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146663382100001 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/div.c | 40 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 41 insertions(+) create mode 100644 tests/tcg/s390x/div.c diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c new file mode 100644 index 0000000000..5807295614 --- /dev/null +++ b/tests/tcg/s390x/div.c @@ -0,0 +1,40 @@ +#include +#include + +static void test_dr(void) +{ + register int32_t r0 asm("r0") =3D -1; + register int32_t r1 asm("r1") =3D -4241; + int32_t b =3D 101, q, r; + + asm("dr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D -41); + assert(r =3D=3D -100); +} + +static void test_dlr(void) +{ + register uint32_t r0 asm("r0") =3D 0; + register uint32_t r1 asm("r1") =3D 4243; + uint32_t b =3D 101, q, r; + + asm("dlr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D 42); + assert(r =3D=3D 1); +} + +int main(void) +{ + test_dr(); + test_dlr(); +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 07fcc6d0ce..ab7a3bcfb2 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -24,6 +24,7 @@ TESTS+=3Dtrap TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec +TESTS+=3Ddiv =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146283; cv=none; d=zohomail.com; s=zohoarc; b=LdEK2ZsSuQH7qnX6AXAFklTHYuIGf9ktgEI/p0JIOOQLEevniIn8vIUp3JRhnxBHdqHLiTjY9v8bx08l1vB64Ev9yUfx6LWWPffQkfA6VAFB23ruEfoXHh+IiTtwErDbpyQpyNIg76QLHfgv8p+x26OBxvvsy7Yt8Y06dXh5yOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146283; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=EBY5Ym/11WB8BbDyx8AL4upzqOUNHgCVNnA5X81e4J4Azu0SeYZbtE/av2mB+zOPzT5TwCH15JW9twfV0A0DHVwHf+QHlJ6XEa5Sf8Fw5KQ5w2OzTMMI7JNDFFx8JJV3GK64oPdUI+TY7+beNGD/Hie3yLCq5xoE9c4/rukWeAU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146283016342.07765094561273; Sat, 7 Jan 2023 18:51:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELZz-0005cd-2o; Sat, 07 Jan 2023 21:38:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZw-0005YE-BS for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:32 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZB-0004Ve-Fm for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:32 -0500 Received: by mail-pl1-x62a.google.com with SMTP id jl4so5864032plb.8 for ; Sat, 07 Jan 2023 18:37:45 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=YTwxzUVTIaPoRoMrrMr3xZVtTxHkxcoWUY/Z2XQDOSB9OBwIAea0LWF4lZprz0utdL bz8oAXkZ3pbK8ENWVfDUPWyMxSf5qcWI7FdLHPzVhOdyqjkbnc7RYerBxQdmB9Sd4SNc W53FcipIv/fYzM1CT+uvFYlDuvdAk2/kogBSiHH30yV1gAPucUS4CmvT7tD6r8j3GoeP e3C4JRG6yLBzathSHildNLFQ87fxBqI7WxbiZTxvKKqIeunYgevwxILHvH32/SSN3Z4G nJwT+chTNLjwGHbuETD1YlinuW3PASIxxePuuoD/RrS4xa3rYjivcBCSGBfLjUJGJLuQ MlWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=gDIf+SaukPH3hjZq85/TNeCnL8WQ/9mXBEYBPr4ZlJOI7so+nyFHDMa219/8kQKxGh IUcQvYHdjq8edMICVaiKKMlhHcnyjxy6xUbfwl1IHJqGQjhzJmcM0eqrc7AmEDEo7SEh PK4nXGCAUUArpIS3mpdUcBB2ZIyqXIlPJjkkcBORsiesII7x9SztVwIZJxWVKViFQOHH KBdWd31DpnQdp2eSpY7HvT0CNMsf3qXZffBtXwRP+JmwT5CLuHryhL7Veq0zSJxTygXt b1nyVqy4640kXr5p9CD6paM/tvu7QIHQmVKXv2nwFylONmElw8w5Mx2W7mGi7nQGxhWU vaBA== X-Gm-Message-State: AFqh2kqX0BF5BCKBHXNSkcMD8QDz6ztNyuLXCNETdGQaJD2MYKS0yafa fMxR9EckrbX4HBMYwdAPAVY8qLT6GZLjPr/U X-Google-Smtp-Source: AMrXdXtWkkVxrDI5jAepvQBu55pf/8Pkk8TEqq3iuXCppr2qwzq8jDajDuGDsPrBDdPoMgPJH321zw== X-Received: by 2002:a17:902:fe0c:b0:192:5c3e:8939 with SMTP id g12-20020a170902fe0c00b001925c3e8939mr52348852plj.0.1673145464761; Sat, 07 Jan 2023 18:37:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich Subject: [PATCH v4 22/36] tests/tcg/s390x: Add clst.c Date: Sat, 7 Jan 2023 18:37:05 -0800 Message-Id: <20230108023719.2466341-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146283818100003 Content-Type: text/plain; charset="utf-8" From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/clst.c | 82 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 83 insertions(+) create mode 100644 tests/tcg/s390x/clst.c diff --git a/tests/tcg/s390x/clst.c b/tests/tcg/s390x/clst.c new file mode 100644 index 0000000000..ed2fe7326c --- /dev/null +++ b/tests/tcg/s390x/clst.c @@ -0,0 +1,82 @@ +#define _GNU_SOURCE +#include +#include + +static int clst(char sep, const char **s1, const char **s2) +{ + const char *r1 =3D *s1; + const char *r2 =3D *s2; + int cc; + + do { + register int r0 asm("r0") =3D sep; + + asm("clst %[r1],%[r2]\n" + "ipm %[cc]\n" + "srl %[cc],28" + : [r1] "+r" (r1), [r2] "+r" (r2), "+r" (r0), [cc] "=3Dr" (cc) + : + : "cc"); + *s1 =3D r1; + *s2 =3D r2; + } while (cc =3D=3D 3); + + return cc; +} + +static const struct test { + const char *name; + char sep; + const char *s1; + const char *s2; + int exp_cc; + int exp_off; +} tests[] =3D { + { + .name =3D "cc0", + .sep =3D 0, + .s1 =3D "aa", + .s2 =3D "aa", + .exp_cc =3D 0, + .exp_off =3D 0, + }, + { + .name =3D "cc1", + .sep =3D 1, + .s1 =3D "a\x01", + .s2 =3D "aa\x01", + .exp_cc =3D 1, + .exp_off =3D 1, + }, + { + .name =3D "cc2", + .sep =3D 2, + .s1 =3D "abc\x02", + .s2 =3D "abb\x02", + .exp_cc =3D 2, + .exp_off =3D 2, + }, +}; + +int main(void) +{ + const struct test *t; + const char *s1, *s2; + size_t i; + int cc; + + for (i =3D 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + t =3D &tests[i]; + s1 =3D t->s1; + s2 =3D t->s2; + cc =3D clst(t->sep, &s1, &s2); + if (cc !=3D t->exp_cc || + s1 !=3D t->s1 + t->exp_off || + s2 !=3D t->s2 + t->exp_off) { + fprintf(stderr, "%s\n", t->name); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index ab7a3bcfb2..79250f31dd 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -25,6 +25,7 @@ TESTS+=3Dsignals-s390x TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec TESTS+=3Ddiv +TESTS+=3Dclst =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146101; cv=none; d=zohomail.com; s=zohoarc; b=eAS6t6AD3IpIPMv/V3Hzr0k/QsVEGKC41MzkWZlzylz/CDlF9EAp8puhsjJ6ybPleKD+RUX3lP4O2GVJ+31Y4u/ivMy88Bpxu4PFcUcdfymgpd/EMgilqyOcazpC8GEJx+sqQ1FgmPMoQye81ZjW9pMXO1iTIo1WFqvghvV3Yd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146101; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wHZLFNNm0ZFp31ulDF75QeL44+XwFwYbg39T7b6YDuI=; b=dYfg0h1YOEUAPNxtxYL/zXrglrnBXKnVo8U6pAPGP5oagmIzioyMQ4NlR3+jlqd86sqddfLBQwAW4iXtIpFSqAl0AgQN0xS1KJzE/zjfhc2c3ZQ4Df1RGYzgRV+6+9atOji8Z0jg/neMs1pqJ9lkxpe/Ctc7y+0Z8h2cnL86NPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146101336523.215268091944; Sat, 7 Jan 2023 18:48:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELa2-0005ms-WB; Sat, 07 Jan 2023 21:38:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa1-0005iT-Ij for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:37 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZD-0004hO-EE for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:37 -0500 Received: by mail-pj1-x1030.google.com with SMTP id fz16-20020a17090b025000b002269d6c2d83so8701502pjb.0 for ; Sat, 07 Jan 2023 18:37:47 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wHZLFNNm0ZFp31ulDF75QeL44+XwFwYbg39T7b6YDuI=; b=yz/Vv9hfx11fLSInlmwJJ1MiPWzE7D/6OdyIY8MRsTs5VPjdFjXiWqOie9g2r6ox8f xOqANbE5cvmgQPJkBPDFqa5M2lDwRmrPO5Ps35nPdBDp/2jfCaf6CekDebjqcusMcNtI e7wjIooMErSThlYi6DKx+5bT78BY7IWdlWjBAxF/xzojETPLYpH5Z/I+a8obKDiWp/ee bJzNJbVRYOKS6Q8NF8c1Y86wXQ9zdyEsto8R0ACvTaT20gzVGLqEhlTB+5Y/1jRRtwpr V35qfYdz/Kax42wBGbUZfcRkscrNi0Rw4aNaCmMirA+Hmopcpyj06pGB8fvY153nHJ0P tosw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146103223100002 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tests/tcg/s390x/long-double.c | 24 ++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/long-double.c diff --git a/tests/tcg/s390x/long-double.c b/tests/tcg/s390x/long-double.c new file mode 100644 index 0000000000..757a6262fd --- /dev/null +++ b/tests/tcg/s390x/long-double.c @@ -0,0 +1,24 @@ +/* + * Perform some basic arithmetic with long double, as a sanity check. + * With small integral numbers, we can cross-check with integers. + */ + +#include + +int main() +{ + int i, j; + + for (i =3D 1; i < 5; i++) { + for (j =3D 1; j < 5; j++) { + long double la =3D (long double)i + j; + long double lm =3D (long double)i * j; + long double ls =3D (long double)i - j; + + assert(la =3D=3D i + j); + assert(lm =3D=3D i * j); + assert(ls =3D=3D i - j); + } + } + return 0; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index 79250f31dd..1d454270c0 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -26,6 +26,7 @@ TESTS+=3Dbranch-relative-long TESTS+=3Dnoexec TESTS+=3Ddiv TESTS+=3Dclst +TESTS+=3Dlong-double =20 Z13_TESTS=3Dvistr $(Z13_TESTS): CFLAGS+=3D-march=3Dz13 -O2 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0m37yJViirw0Wc/T2o6kI/jHDeYjleRW0O5TzNJ6/Gw=; b=h4+cxeTYl00k+rgoM0vv41/Usl7td91koPjOdPmbIrk9Ea10TDSD1uGzQBwgxvqv48 OsoS1rK0TA8yfiadWo4InJ+9YJ3xPMKYi5rxK0YG4SyEJK9yPu8ZtnmSo6J79MaJbzBc wjQvhWqFw4mTmUFfLQc6eZbWD7QbT/ByITs7ttr6HJ7GThC0EbQkEq+kVYiawTXFKTV+ h1jSXt5sM3RMsEhpU8r1OB7CiJiAtFwROctYRt3qP1RmJjmvP5/wYUKqt4En2ocWs4UK c1Qvt/KAy8hd2ecxd8W+Swd/WGhGKr7RonpbqmsH6mI/EPiHlxD+KurTJIjmsCoDd3Ct hU6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0m37yJViirw0Wc/T2o6kI/jHDeYjleRW0O5TzNJ6/Gw=; b=EUECOFgtdR1gMJXw4XqTQDaoeVgeICsrnq1qdnRvlpKCwYd3nZhWVdlGYRIeJdzSB9 xwHrBRGINucc91rSKlNyke9d0FkgMyUlUe3CvBT/XTXQzQUfzxXgAUQ5/cjJfe4mJsoo QaWOCqiZ4eClve44+EvJwJLdHGwuwlbG/IY1a2vcfkae34/rkFioxioGPsFVr+hneHfe pryPirK5fFipMP4ka1y5A7VDYZa5ucDLNdB5AY8kWk+T5+THBld1b9p6OhkltGePzPIK 5LMmnzM6qlm1UbdYco4U+Ivdqtfl2VwuOQk5ZsoNA3Yeay782Sv1nMBiwc0XM14H6v1z XdGg== X-Gm-Message-State: AFqh2kqey7vopbF9dg0gmj6XniyAjNX+pbtBhm0huVka/fhWdxrpnGZU pk5/XiKgk6JLKQISAyUphRoBt28CPXVYN8oI X-Google-Smtp-Source: AMrXdXuWbDFrK2c7CNgFID6FzP7cLwTU9VSqrQ7/GmJ/yBTUQ1xfxnwlqiQisWjVWs96GZGs2VCj1Q== X-Received: by 2002:a17:903:40c4:b0:193:197e:494f with SMTP id t4-20020a17090340c400b00193197e494fmr5227036pld.27.1673145467340; Sat, 07 Jan 2023 18:37:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 24/36] target/s390x: Use a single return for helper_divs32/u32 Date: Sat, 7 Jan 2023 18:37:07 -0800 Message-Id: <20230108023719.2466341-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145975593100007 Content-Type: text/plain; charset="utf-8" Pack the quotient and remainder into a single uint64_t. Signed-off-by: Richard Henderson --- v2: Fix operand ordering; use tcg_extr32_i64. --- target/s390x/helper.h | 2 +- target/s390x/tcg/int_helper.c | 26 +++++++++++++------------- target/s390x/tcg/translate.c | 8 ++++---- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 93923ca153..bc828d976b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -10,7 +10,7 @@ DEF_HELPER_FLAGS_4(clc, TCG_CALL_NO_WG, i32, env, i32, i6= 4, i64) DEF_HELPER_3(mvcl, i32, env, i32, i32) DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) -DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64) +DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 954542388a..7260583cf2 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -34,45 +34,45 @@ #endif =20 /* 64/32 -> 32 signed division */ -int64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) +uint64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) { - int32_t ret, b =3D b64; - int64_t q; + int32_t b =3D b64; + int64_t q, r; =20 if (b =3D=3D 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - ret =3D q =3D a / b; - env->retxl =3D a % b; + q =3D a / b; + r =3D a % b; =20 /* Catch non-representable quotient. */ - if (ret !=3D q) { + if (q !=3D (int32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - return ret; + return deposit64(q, 32, 32, r); } =20 /* 64/32 -> 32 unsigned division */ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a, uint64_t b64) { - uint32_t ret, b =3D b64; - uint64_t q; + uint32_t b =3D b64; + uint64_t q, r; =20 if (b =3D=3D 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - ret =3D q =3D a / b; - env->retxl =3D a % b; + q =3D a / b; + r =3D a % b; =20 /* Catch non-representable quotient. */ - if (ret !=3D q) { + if (q !=3D (uint32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 - return ret; + return deposit64(q, 32, 32, r); } =20 /* 64/64 -> 64 signed division */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a339b277e9..169f7ee1b2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2395,15 +2395,15 @@ static DisasJumpType op_diag(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_divs32(DisasContext *s, DisasOps *o) { - gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divs32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 static DisasJumpType op_divu32(DisasContext *s, DisasOps *o) { - gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divu32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145667; cv=none; d=zohomail.com; s=zohoarc; b=AQMbl7BmTt5gaAUhQ0aDQKfrATJjRfF6/HGxX5tDLWG5EMZQUdaJu2mcOZSsFiD2Pv1qW3xhWhqHe/qhLg8cdgHRF6/S9HHRJ4thFkjYEPHgiToOW17xen5UPmZWb/WN1JopRdmj4AmqC3OfNw+Qr7exyGRvQ0EPvo1skxnKL3g= ARC-Message-Signature: i=1; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zggxelJn7xEGVyzBGDuJjR27fAkYzw0xoPZGZDzp+DI=; b=VisuC+Ip5u7W5Df4yZw2ra/bK4L+aaxmLjRiPI0JTwtLDfluPWINCP4LBcndxPi7aW g3l8Hvf/4Fc8vOu3ONeRS12Ag3XhLAccELa3JXAN1GI92t/2FhNwuGmcZQRSjJ3ubK8X QN0s53nX6mP04kyq4PstivRBZ03LkKLtt4QDMvtZ2EE1Gom4p0LQaNDNHtKNhUlZuT7m z83oXwE/9eSLowL66/9lKab+3F6sQwdN1nXUrYNjsUxc3YI9xz+X3VI8WshxBu4OslHo ZNbR4ECkZAX2ND4cR9fFlZqwCsDDq898uVJjsroJf3srf7PlsPFgn9ZGmN5NQnFfa9ts 5tAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zggxelJn7xEGVyzBGDuJjR27fAkYzw0xoPZGZDzp+DI=; b=jZxnnNizqp0PD0JiJl1Q1gKZfA1d0TydNeu1Fgfiya3CWCFDqym236wtjIHUJ++bRq PGd4htoukjt9zT8X4ugP0473nZO1WS36vhoKi5ykRhpjjnSu8WrttrSTLh4RL6n9MqBD FgoSrTkrSOaxUg7NfgnXB9AZHoj6ZbpQnzqzFpbflssG3LmIIMvEd/v6rI/zRKZLC2vI fiVha6+rX8ySuSkcYDRmKsXF7VoNqaah5+2w7rkN21L79nRCepLE+UfhAXdIMNY32Bpr 6C0wS8OVKZdHU58IBku81ZjWJnS3SzBp9UVbyRCW6q4ZVwQ+wXKBset5JxqKDFOi5nYu UR8g== X-Gm-Message-State: AFqh2kr0Rn0ygvb3EAwbLeuLANgpmbdabQdP3TZI+nDDOM1KlvwmO+BO jMh6qUeFkI+qrlG8PtzSii0uYWUo2DY/cEYn X-Google-Smtp-Source: AMrXdXucn3ETdl9rH82UdLM0w5gSwaHo27rHzBCQcprS+ZvTq7UDKV9muRNeEMHkyIPJuU+ritQEGg== X-Received: by 2002:a17:902:d491:b0:192:b40b:e41 with SMTP id c17-20020a170902d49100b00192b40b0e41mr46754706plg.61.1673145468501; Sat, 07 Jan 2023 18:37:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 25/36] target/s390x: Use a single return for helper_divs64/u64 Date: Sat, 7 Jan 2023 18:37:08 -0800 Message-Id: <20230108023719.2466341-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145668492100003 Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- v2: Extended div test case to cover these insns. --- target/s390x/helper.h | 4 ++-- target/s390x/tcg/int_helper.c | 38 +++++++++-------------------------- target/s390x/tcg/translate.c | 14 +++++++++---- tests/tcg/s390x/div.c | 35 ++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 35 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bc828d976b..593f3c8bee 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -12,8 +12,8 @@ DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) -DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64, s64) +DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) DEF_HELPER_4(clst, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 7260583cf2..eb8e6dd1b5 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -76,46 +76,26 @@ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a,= uint64_t b64) } =20 /* 64/64 -> 64 signed division */ -int64_t HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) +Int128 HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) { /* Catch divide by zero, and non-representable quotient (MIN / -1). */ if (b =3D=3D 0 || (b =3D=3D -1 && a =3D=3D (1ll << 63))) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - env->retxl =3D a % b; - return a / b; + return int128_make128(a / b, a % b); } =20 /* 128 -> 64/64 unsigned division */ -uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t b) +Int128 HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64= _t b) { - uint64_t ret; - /* Signal divide by zero. */ - if (b =3D=3D 0) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); - } - if (ah =3D=3D 0) { - /* 64 -> 64/64 case */ - env->retxl =3D al % b; - ret =3D al / b; - } else { - /* ??? Move i386 idivq helper to host-utils. */ -#ifdef CONFIG_INT128 - __uint128_t a =3D ((__uint128_t)ah << 64) | al; - __uint128_t q =3D a / b; - env->retxl =3D a % b; - ret =3D q; - if (ret !=3D q) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); + if (b !=3D 0) { + uint64_t r =3D divu128(&al, &ah, b); + if (ah =3D=3D 0) { + return int128_make128(al, r); } -#else - /* 32-bit hosts would need special wrapper functionality - just ab= ort if - we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); -#endif } - return ret; + /* divide by zero or overflow */ + tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } =20 uint64_t HELPER(cvd)(int32_t reg) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 169f7ee1b2..6953b81de7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2409,15 +2409,21 @@ static DisasJumpType op_divu32(DisasContext *s, Dis= asOps *o) =20 static DisasJumpType op_divs64(DisasContext *s, DisasOps *o) { - gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + TCGv_i128 t =3D tcg_temp_new_i128(); + + gen_helper_divs64(t, cpu_env, o->in1, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } =20 static DisasJumpType op_divu64(DisasContext *s, DisasOps *o) { - gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out); + TCGv_i128 t =3D tcg_temp_new_i128(); + + gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } =20 diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c index 5807295614..6ad9900e08 100644 --- a/tests/tcg/s390x/div.c +++ b/tests/tcg/s390x/div.c @@ -33,8 +33,43 @@ static void test_dlr(void) assert(r =3D=3D 1); } =20 +static void test_dsgr(void) +{ + register int64_t r0 asm("r0") =3D -1; + register int64_t r1 asm("r1") =3D -4241; + int64_t b =3D 101, q, r; + + asm("dsgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D -41); + assert(r =3D=3D -100); +} + +static void test_dlgr(void) +{ + register uint64_t r0 asm("r0") =3D 0; + register uint64_t r1 asm("r1") =3D 4243; + uint64_t b =3D 101, q, r; + + asm("dlgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q =3D r1; + r =3D r0; + assert(q =3D=3D 42); + assert(r =3D=3D 1); +} + int main(void) { test_dr(); test_dlr(); + test_dsgr(); + test_dlgr(); + return 0; } --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145564; cv=none; d=zohomail.com; s=zohoarc; b=avcC6GA239eRYc3Bqee2JYcdC6cvFVo8mCUDpex3qm8uHd2e+6aEUs6aLgej6zZwZu4GQ2dYxzIL7oaBVDZAcSRpIrUsjmDb1jAldocWvTWmjfLXXRvnfE7HkBdSAmneBhxt1Exo83+FtHXSbTLXxfd5N1AH9FGbW3vNSq96Ewc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673145564; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SzDpq4p4TZ0OiGc3bd/AjIVDg1qF6XupmGP3awuLITw=; b=mh9iTEjAhO/mCrWhZWcF45E6pde952c1GiyBnMSI5xaJs8kQRrnRx/1bv40JO01G5SfNoRuAQf2EzJIQl0fdjQzRE9NoDAsXlRUWOSFSXBWXBwKfeIoJ1gVTEVoAHad3Izpf2zCXHyrYDoBijqKokSIsaTfW+EC7p4FNYEKuMm8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16731455643811022.4628197463021; Sat, 7 Jan 2023 18:39:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELaA-00063j-I4; Sat, 07 Jan 2023 21:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa6-0005qY-Up for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:42 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZH-0004YR-F9 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:41 -0500 Received: by mail-pj1-x1029.google.com with SMTP id b9-20020a17090a7ac900b00226ef160dcaso4079944pjl.2 for ; Sat, 07 Jan 2023 18:37:49 -0800 (PST) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145566102100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 11 ++++------- target/s390x/tcg/translate.c | 8 ++++++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 593f3c8bee..25c2dd0b3c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -16,7 +16,7 @@ DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64= , s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) -DEF_HELPER_4(clst, i64, env, i64, i64, i64) +DEF_HELPER_4(clst, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index cb82cd1c1d..9be42851d8 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -886,7 +886,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) } =20 /* unsigned string compare (c is string terminator) */ -uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_= t s2) +Int128 HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t = s2) { uintptr_t ra =3D GETPC(); uint32_t len; @@ -904,23 +904,20 @@ uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c,= uint64_t s1, uint64_t s2) if (v1 =3D=3D c) { /* Equal. CC=3D0, and don't advance the registers. */ env->cc_op =3D 0; - env->retxl =3D s2; - return s1; + return int128_make128(s2, s1); } } else { /* Unequal. CC=3D{1,2}, and advance the registers. Note that the terminator need not be zero, but the string that contai= ns the terminator is by definition "low". */ env->cc_op =3D (v1 =3D=3D c ? 1 : v2 =3D=3D c ? 2 : v1 < v2 ? = 1 : 2); - env->retxl =3D s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } } =20 /* CPU-determined bytes equal; advance the registers. */ env->cc_op =3D 3; - env->retxl =3D s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } =20 /* move page */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 6953b81de7..8397fe2bd8 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2164,9 +2164,13 @@ static DisasJumpType op_clm(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_clst(DisasContext *s, DisasOps *o) { - gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2); + TCGv_i128 pair =3D tcg_temp_new_i128(); + + gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); + tcg_gen_extr_i128_i64(o->in2, o->in1, pair); + tcg_temp_free_i128(pair); + set_cc_static(s); - return_low128(o->in2); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146159; cv=none; d=zohomail.com; s=zohoarc; b=iskEPNKH93yfco/gD0tmOyW9jRl8acHfB120tnNnWoZVJuVwvytIk+wkEUAekcrnI/1lzzlhz5QzUaXzSiV3hb9bt2upQQBbCSHulM/ojOo8wUZrMZRFtx/8ALF8Xov9Bld3vGngKjDc4lZTB1eNwLbktObZaaRg+XngC8CR3Fw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146159; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=Q4XpJOrO/Yv9qvYrAdEREoKltdKxwoVGXxuSjeP6kZ+rbWk9h1u097hAxHgHocNlvNhcHw4qGNuoK02rBzy4za3YEgG/LO+df6amwnnsjMPUn4jJYYjEGpojpEHyiZnGEECG6S6So+9T0dLU82C1YdP0CU1AiUlyg4xvqg8Kugs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146159535864.861277312545; Sat, 7 Jan 2023 18:49:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELaC-0006CL-WB; Sat, 07 Jan 2023 21:38:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa8-0005u5-8U for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:44 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZH-0004jl-Tg for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:38:43 -0500 Received: by mail-pj1-x1035.google.com with SMTP id h7-20020a17090aa88700b00225f3e4c992so9303945pjq.1 for ; Sat, 07 Jan 2023 18:37:51 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=TegwglnL6q7iVTSGCpZcoM+tVYYCB0J+zT6QfcVW8A3uqu9fs9/M/S7aIYXTb9MeCq 6dAGsHTy/eqwhddJoWnJcioaLlzMzqXE8wwz9dgy5CIYcZuaaFqXuIVFmTXn76ZmOS7I GaPS5AFZt3FGUrr5CqsMUhPdM4gu1mGkSO9qRjiafE2nqMnN8XWaAcJ1Pbg9mAYxDT84 1ZGu4l/knxUXydyMvkAlbE9mnv021BghbD8jZUXdlittqV6cmkxoylWR0F20J4Z6nSyT RqCM/WbUSfr+fyaLfHdwxfSRQubpUcbI2T2TDki/jkvoylrffqxMV6s7FCq3nuxo7Dpr 7kqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146161487100003 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 6 ++++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 25c2dd0b3c..03b29efa3e 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -103,7 +103,7 @@ DEF_HELPER_4(tre, i64, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) -DEF_HELPER_4(cksm, i64, env, i64, i64, i64) +DEF_HELPER_4(cksm, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i= 64) DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 9be42851d8..b0b403e23a 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1350,8 +1350,8 @@ uint32_t HELPER(clclu)(CPUS390XState *env, uint32_t r= 1, uint64_t a2, } =20 /* checksum */ -uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, - uint64_t src, uint64_t src_len) +Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, + uint64_t src, uint64_t src_len) { uintptr_t ra =3D GETPC(); uint64_t max_len, len; @@ -1392,8 +1392,7 @@ uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, env->cc_op =3D (len =3D=3D src_len ? 0 : 3); =20 /* Return both cksm and processed length. */ - env->retxl =3D cksm; - return len; + return int128_make128(cksm, len); } =20 void HELPER(pack)(CPUS390XState *env, uint32_t len, uint64_t dest, uint64_= t src) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8397fe2bd8..1a7aa9e4ae 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2041,11 +2041,13 @@ static DisasJumpType op_cxlgb(DisasContext *s, Disa= sOps *o) static DisasJumpType op_cksm(DisasContext *s, DisasOps *o) { int r2 =3D get_field(s, r2); + TCGv_i128 pair =3D tcg_temp_new_i128(); TCGv_i64 len =3D tcg_temp_new_i64(); =20 - gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]); + gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); - return_low128(o->out); + tcg_gen_extr_i128_i64(o->out, len, pair); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146530820100008 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 7 +++++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 03b29efa3e..b4170a4256 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_4(unpka, TCG_CALL_NO_WG, i32, env, i64, = i32, i64) DEF_HELPER_FLAGS_4(unpku, TCG_CALL_NO_WG, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32) DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64) -DEF_HELPER_4(tre, i64, env, i64, i64, i64) +DEF_HELPER_4(tre, i128, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b0b403e23a..49969abda7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1632,8 +1632,8 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uin= t64_t array, do_helper_tr(env, len, array, trans, GETPC()); } =20 -uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, - uint64_t len, uint64_t trans) +Int128 HELPER(tre)(CPUS390XState *env, uint64_t array, + uint64_t len, uint64_t trans) { uintptr_t ra =3D GETPC(); uint8_t end =3D env->regs[0] & 0xff; @@ -1668,8 +1668,7 @@ uint64_t HELPER(tre)(CPUS390XState *env, uint64_t arr= ay, } =20 env->cc_op =3D cc; - env->retxl =3D len - i; - return array + i; + return int128_make128(len - i, array + i); } =20 static inline uint32_t do_helper_trt(CPUS390XState *env, int len, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1a7aa9e4ae..f3e4b70ed9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -4905,8 +4905,11 @@ static DisasJumpType op_tr(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_tre(DisasContext *s, DisasOps *o) { - gen_helper_tre(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + TCGv_i128 pair =3D tcg_temp_new_i128(); + + gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; b=kx3dZpEnOsRyJybrCApOMyixn7rk94XTr86uSFAz4gz4LCGvDUzT8H3U2TvjF/zo4U shqAEmhOxZxKOdvz9+dVhcG7otKDN35yjmul1xbZ02fFffIkV3cEfnSwL34W2F/gtyeE EVl/vBlO5zfUrrhOsrSpBl3NhR8u5OBEKApfMEo6eOsvlFS9sOHF0s0IqwI2aPBJDhZm 4RniVlYOeDWSx0pB/+tjO8kscq1pqJ23fJMT3CToo6q/HvjmB/XcPOuTAryvjKrjxUqP P0WMbvcJs06QrCb0iGqqT4/5e/FTyIQT3aqPlnl13F92l5ysLVI9yyiQM120ORH3dpeS iYdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+jhW1VfMMjd/T4xu5tAsEJqCQwclAn0GfVV3GJNGabg=; b=kETHA7Rrt8L31cKLXcUiJx92OzvXjIfVmh9yzzU3f5nt0aolgMW2XVKwc3KqhfNQ52 73HJZfVhGd+XwJUT7U7FsR79DQCVbQ5L43Qmpkmw+R38o2USfl1ZBHerA0XgyhWGfuiy vq03wTDFChbiefpfdEFEQ6BuHfcLimjhWHB7Gxtb0YlusxOZ1zWEHcsCvgUBsHSWqNw4 d/scFcT0k7bY6xbHv6i+hLpeJKEaAhNq94ViqVew61PiJheYmjxFDcRtcuQ4BCwib+9d j+G9BCe+TkypU7MFZyziyI7j1QiGv5lx5qwkSRRcINklxDTxUflGvsoix3ApSkm79EeM tJEw== X-Gm-Message-State: AFqh2kqvv/mzFdo/81KG6unK4gDQgxjBFsK3Pr3dCW9kwLAy1a/lEDgW b41HEhFpTTQFXjJsTCG/Ci0PGTuQfl8KbOwB X-Google-Smtp-Source: AMrXdXuvDxAZnMo1is9x/LroMRMBk9qdOto9Z9/wW/cVRaWq7NqZrO09poD3kVHDMDC0yx4hxiTxfw== X-Received: by 2002:a17:902:e944:b0:189:d8fb:1523 with SMTP id b4-20020a170902e94400b00189d8fb1523mr70590119pll.36.1673145473024; Sat, 07 Jan 2023 18:37:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich Subject: [PATCH v4 29/36] target/s390x: Copy wout_x1 to wout_x1_P Date: Sat, 7 Jan 2023 18:37:12 -0800 Message-Id: <20230108023719.2466341-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145732670100003 Content-Type: text/plain; charset="utf-8" Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 12 ++++++------ target/s390x/tcg/translate.c | 8 ++++++++ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 79c6ab509a..d0814cb218 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -422,7 +422,7 @@ F(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0, IF_AFP1 |= IF_AFP2) F(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) F(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) - F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1, movx, 0, IF_AFP1) + F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1_P, movx, 0, IF_AFP1) /* LOAD IMMEDIATE */ C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0) /* LOAD RELATIVE LONG */ @@ -461,7 +461,7 @@ C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64) F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP) F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP) - F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1, movx, f128, IF_BFP) + F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP) /* LOAD AND TRAP */ C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0) C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0) @@ -483,7 +483,7 @@ C(0xb913, LCGFR, RRE, Z, 0, r2_32s, r1, 0, neg, neg64) F(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32, IF_BFP) F(0xb313, LCDBR, RRE, Z, 0, f2, new, f1, negf64, f64, IF_BFP) - F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1, negf128, f128, IF_= BFP) + F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1_P, negf128, f128, I= F_BFP) F(0xb373, LCDFR, RRE, FPSSH, 0, f2, new, f1, negf64, 0, IF_AFP1 | = IF_AFP2) /* LOAD COUNT TO BLOCK BOUNDARY */ C(0xe727, LCBB, RXE, V, la2, 0, r1, 0, lcbb, 0) @@ -552,7 +552,7 @@ C(0xb911, LNGFR, RRE, Z, 0, r2_32s, r1, 0, nabs, nabs64) F(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32, IF_BFP) F(0xb311, LNDBR, RRE, Z, 0, f2, new, f1, nabsf64, f64, IF_BFP) - F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1, nabsf128, f128, IF= _BFP) + F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1_P, nabsf128, f128, = IF_BFP) F(0xb371, LNDFR, RRE, FPSSH, 0, f2, new, f1, nabsf64, 0, IF_AFP1 |= IF_AFP2) /* LOAD ON CONDITION */ C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0) @@ -577,7 +577,7 @@ C(0xb910, LPGFR, RRE, Z, 0, r2_32s, r1, 0, abs, abs64) F(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32, IF_BFP) F(0xb310, LPDBR, RRE, Z, 0, f2, new, f1, absf64, f64, IF_BFP) - F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1, absf128, f128, IF_= BFP) + F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1_P, absf128, f128, I= F_BFP) F(0xb370, LPDFR, RRE, FPSSH, 0, f2, new, f1, absf64, 0, IF_AFP1 | = IF_AFP2) /* LOAD REVERSED */ C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0) @@ -588,7 +588,7 @@ /* LOAD ZERO */ F(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0, IF_AFP1) F(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0, IF_AFP1) - F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0, IF_AFP1) + F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1_P, zero2, 0, IF_AFP1) =20 /* LOAD FPC */ F(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0, IF_BFP) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f3e4b70ed9..d25b6f3c03 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5518,6 +5518,14 @@ static void wout_x1(DisasContext *s, DisasOps *o) } #define SPEC_wout_x1 SPEC_r1_f128 =20 +static void wout_x1_P(DisasContext *s, DisasOps *o) +{ + int f1 =3D get_field(s, r1); + store_freg(f1, o->out); + store_freg(f1 + 2, o->out2); +} +#define SPEC_wout_x1_P SPEC_r1_f128 + static void wout_cond_r1r2_32(DisasContext *s, DisasOps *o) { if (get_field(s, r1) !=3D get_field(s, r2)) { --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146572; cv=none; d=zohomail.com; s=zohoarc; b=Y5v4rVnh2vvhUzn8zl534UFPMH6n1BlPFDHc1/D+iXAWAXR/Z2WbztTeJg5bw8l3WTQwWMe8Gtiw/VT0Le72eaVAZ62mv31TcFT+85/HpgwlS+7QBVmRE90iVCrHEWLurMaoJdTMCwfa4ksaLotOLQcr0A/MnXH+Y3vHhjq3nRo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146572; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 30/36] target/s390x: Use Int128 for returning float128 Date: Sat, 7 Jan 2023 18:37:13 -0800 Message-Id: <20230108023719.2466341-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146572897100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v2: Remove extraneous return_low128. --- target/s390x/helper.h | 22 +++++++------- target/s390x/tcg/insn-data.h.inc | 20 ++++++------- target/s390x/tcg/fpu_helper.c | 29 +++++++++--------- target/s390x/tcg/translate.c | 51 +++++++++++++++++--------------- 4 files changed, 63 insertions(+), 59 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b4170a4256..d40aeb471f 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -31,32 +31,32 @@ DEF_HELPER_4(clcle, i32, env, i32, i64, i32) DEF_HELPER_4(clclu, i32, env, i32, i64, i32) DEF_HELPER_3(cegb, i64, env, s64, i32) DEF_HELPER_3(cdgb, i64, env, s64, i32) -DEF_HELPER_3(cxgb, i64, env, s64, i32) +DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) -DEF_HELPER_3(cxlgb, i64, env, i64, i32) +DEF_HELPER_3(cxlgb, i128, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) -DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) +DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) @@ -79,7 +79,7 @@ DEF_HELPER_3(clfdb, i64, env, i64, i32) DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) @@ -89,7 +89,7 @@ DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i6= 4, i64) DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index d0814cb218..517a4500ae 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -306,10 +306,10 @@ /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) - F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_P, x1, cxgb, 0, IF_BFP) + F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_x, x1, cxgb, 0, IF_BFP) F(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0, IF_BFP) F(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, new, f1, cdgb, 0, IF_BFP) - F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_P, x1, cxgb, 0, IF_BFP) + F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_x, x1, cxgb, 0, IF_BFP) /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) @@ -320,10 +320,10 @@ /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) - F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_x, x1, cxlgb, 0, IF_BFP) F(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0, IF_BFP) F(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, new, f1, cdlgb, 0, IF_BFP) - F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_x, x1, cxlgb, 0, IF_BFP) =20 /* CONVERT UTF-8 TO UTF-16 */ D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12) @@ -597,15 +597,15 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_P, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) =20 /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) - F(0xb305, LXDBR, RRE, Z, 0, f2, new_P, x1, lxdb, 0, IF_BFP) - F(0xb306, LXEBR, RRE, Z, 0, e2, new_P, x1, lxeb, 0, IF_BFP) + F(0xb305, LXDBR, RRE, Z, 0, f2, new_x, x1, lxdb, 0, IF_BFP) + F(0xb306, LXEBR, RRE, Z, 0, e2, new_x, x1, lxeb, 0, IF_BFP) F(0xed04, LDEB, RXE, Z, 0, m2_32u, new, f1, ldeb, 0, IF_BFP) - F(0xed05, LXDB, RXE, Z, 0, m2_64, new_P, x1, lxdb, 0, IF_BFP) - F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_P, x1, lxeb, 0, IF_BFP) + F(0xed05, LXDB, RXE, Z, 0, m2_64, new_x, x1, lxdb, 0, IF_BFP) + F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_x, x1, lxeb, 0, IF_BFP) F(0xb324, LDER, RXE, Z, 0, e2, new, f1, lde, 0, IF_AFP1) F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_P, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) =20 diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index be80b2373c..13be44499b 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -34,7 +34,10 @@ #define HELPER_LOG(x...) #endif =20 -#define RET128(F) (env->retxl =3D F.low, F.high) +static inline Int128 RET128(float128 f) +{ + return int128_make128(f.low, f.high); +} =20 uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { @@ -224,7 +227,7 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP addition */ -uint64_t HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_add(make_float128(ah, al), @@ -251,7 +254,7 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP subtraction */ -uint64_t HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_sub(make_float128(ah, al), @@ -278,7 +281,7 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, u= int64_t f2) } =20 /* 128-bit FP division */ -uint64_t HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_div(make_float128(ah, al), @@ -314,7 +317,7 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP multiplication */ -uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret =3D float128_mul(make_float128(ah, al), @@ -325,8 +328,7 @@ uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, u= int64_t al, } =20 /* 128/64-bit FP multiplication */ -uint64_t HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t f2) +Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t= f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); ret =3D float128_mul(make_float128(ah, al), ret, &env->fpu_status); @@ -355,7 +357,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, = uint64_t al, } =20 /* convert 64-bit float to 128-bit float */ -uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -363,7 +365,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) } =20 /* convert 32-bit float to 128-bit float */ -uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret =3D float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -486,7 +488,7 @@ uint64_t HELPER(cdgb)(CPUS390XState *env, int64_t v2, u= int32_t m34) } =20 /* convert 64-bit int to 128-bit float */ -uint64_t HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) +Int128 HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D int64_to_float128(v2, &env->fpu_status); @@ -519,7 +521,7 @@ uint64_t HELPER(cdlgb)(CPUS390XState *env, uint64_t v2,= uint32_t m34) } =20 /* convert 64-bit uint to 128-bit float */ -uint64_t HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) +Int128 HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D uint64_to_float128(v2, &env->fpu_status); @@ -748,8 +750,7 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2, = uint32_t m34) } =20 /* round to integer 128-bit */ -uint64_t HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t= m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret =3D float128_round_to_int(make_float128(ah, al), @@ -890,7 +891,7 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } =20 /* square root 128-bit */ -uint64_t HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float128 ret =3D float128_sqrt(make_float128(ah, al), &env->fpu_status= ); handle_exceptions(env, false, GETPC()); diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d25b6f3c03..0a750a5467 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1103,6 +1103,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; + TCGv_i128 out_128; } DisasOps; =20 /* Instructions can place constraints on their operands, raising specifica= tion @@ -1461,8 +1462,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -1995,9 +1995,8 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } =20 @@ -2032,9 +2031,8 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxlgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } =20 @@ -2447,8 +2445,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -2553,8 +2550,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34); - return_low128(o->out2); + gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2866,15 +2862,13 @@ static DisasJumpType op_lexb(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o) { - gen_helper_lxdb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxdb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o) { - gen_helper_lxeb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxeb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } =20 @@ -3590,15 +3584,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); return DISAS_NEXT; } =20 @@ -4063,8 +4055,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -4082,8 +4073,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -5395,6 +5385,14 @@ static void prep_new_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_new_P 0 =20 +static void prep_new_x(DisasContext *s, DisasOps *o) +{ + o->out =3D tcg_temp_new_i64(); + o->out2 =3D tcg_temp_new_i64(); + o->out_128 =3D tcg_temp_new_i128(); +} +#define SPEC_prep_new_x 0 + static void prep_r1(DisasContext *s, DisasOps *o) { o->out =3D regs[get_field(s, r1)]; @@ -5411,11 +5409,12 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even =20 -/* Whenever we need x1 in addition to other inputs, we'll load it to out/o= ut2 */ static void prep_x1(DisasContext *s, DisasOps *o) { o->out =3D load_freg(get_field(s, r1)); o->out2 =3D load_freg(get_field(s, r1) + 2); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); } #define SPEC_prep_x1 SPEC_r1_f128 =20 @@ -5513,6 +5512,8 @@ static void wout_f1(DisasContext *s, DisasOps *o) static void wout_x1(DisasContext *s, DisasOps *o) { int f1 =3D get_field(s, r1); + + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); } @@ -6588,7 +6589,9 @@ static DisasJumpType translate_one(CPUS390XState *env= , DisasContext *s) if (o.addr1) { tcg_temp_free_i64(o.addr1); } - + if (o.out_128) { + tcg_temp_free_i128(o.out_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 31/36] target/s390x: Use Int128 for passing float128 Date: Sat, 7 Jan 2023 18:37:14 -0800 Message-Id: <20230108023719.2466341-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146530883100011 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- v2: Fix SPEC_in1_x1. --- target/s390x/helper.h | 32 ++++++------ target/s390x/tcg/insn-data.h.inc | 30 +++++------ target/s390x/tcg/fpu_helper.c | 88 ++++++++++++++------------------ target/s390x/tcg/translate.c | 76 ++++++++++++++++++--------- 4 files changed, 121 insertions(+), 105 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index d40aeb471f..bccd3bfca6 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -41,55 +41,55 @@ DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(axb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(sxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(dxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(mxb, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(mxdb, TCG_CALL_NO_WG, i128, env, i128, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(ldxb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(lexb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(cdb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(cxb, TCG_CALL_NO_WG_SE, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(cxb, TCG_CALL_NO_WG_SE, i32, env, i128, i128) DEF_HELPER_FLAGS_3(keb, TCG_CALL_NO_WG, i32, env, i64, i64) DEF_HELPER_FLAGS_3(kdb, TCG_CALL_NO_WG, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(kxb, TCG_CALL_NO_WG, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(kxb, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_3(cgeb, i64, env, i64, i32) DEF_HELPER_3(cgdb, i64, env, i64, i32) -DEF_HELPER_4(cgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cgxb, i64, env, i128, i32) DEF_HELPER_3(cfeb, i64, env, i64, i32) DEF_HELPER_3(cfdb, i64, env, i64, i32) -DEF_HELPER_4(cfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cfxb, i64, env, i128, i32) DEF_HELPER_3(clgeb, i64, env, i64, i32) DEF_HELPER_3(clgdb, i64, env, i64, i32) -DEF_HELPER_4(clgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clgxb, i64, env, i128, i32) DEF_HELPER_3(clfeb, i64, env, i64, i32) DEF_HELPER_3(clfdb, i64, env, i64, i32) -DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clfxb, i64, env, i128, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(fixb, TCG_CALL_NO_WG, i128, env, i128, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i128, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) +DEF_HELPER_FLAGS_2(sqxb, TCG_CALL_NO_WG, i128, env, i128) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 517a4500ae..893f4b48db 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -34,7 +34,7 @@ C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64) F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP) F(0xb31a, ADBR, RRE, Z, f1, f2, new, f1, adb, f64, IF_BFP) - F(0xb34a, AXBR, RRE, Z, x2h, x2l, x1, x1, axb, f128, IF_BFP) + F(0xb34a, AXBR, RRE, Z, x1, x2, new_x, x1, axb, f128, IF_BFP) F(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32, IF_BFP) F(0xed1a, ADB, RXE, Z, f1, m2_64, new, f1, adb, f64, IF_BFP) /* ADD HIGH */ @@ -172,13 +172,13 @@ C(0xe330, CGF, RXY_a, Z, r1_o, m2_32s, 0, 0, 0, cmps64) F(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0, IF_BFP) F(0xb319, CDBR, RRE, Z, f1, f2, 0, 0, cdb, 0, IF_BFP) - F(0xb349, CXBR, RRE, Z, x2h, x2l, x1, 0, cxb, 0, IF_BFP) + F(0xb349, CXBR, RRE, Z, x1, x2, 0, 0, cxb, 0, IF_BFP) F(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0, IF_BFP) F(0xed19, CDB, RXE, Z, f1, m2_64, 0, 0, cdb, 0, IF_BFP) /* COMPARE AND SIGNAL */ F(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0, IF_BFP) F(0xb318, KDBR, RRE, Z, f1, f2, 0, 0, kdb, 0, IF_BFP) - F(0xb348, KXBR, RRE, Z, x2h, x2l, x1, 0, kxb, 0, IF_BFP) + F(0xb348, KXBR, RRE, Z, x1, x2, 0, 0, kxb, 0, IF_BFP) F(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0, IF_BFP) F(0xed18, KDB, RXE, Z, f1, m2_64, 0, 0, kdb, 0, IF_BFP) /* COMPARE IMMEDIATE */ @@ -299,10 +299,10 @@ /* CONVERT TO FIXED */ F(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0, IF_BFP) F(0xb399, CFDBR, RRF_e, Z, 0, f2, new, r1_32, cfdb, 0, IF_BFP) - F(0xb39a, CFXBR, RRF_e, Z, x2h, x2l, new, r1_32, cfxb, 0, IF_BFP) + F(0xb39a, CFXBR, RRF_e, Z, 0, x2, new, r1_32, cfxb, 0, IF_BFP) F(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0, IF_BFP) F(0xb3a9, CGDBR, RRF_e, Z, 0, f2, r1, 0, cgdb, 0, IF_BFP) - F(0xb3aa, CGXBR, RRF_e, Z, x2h, x2l, r1, 0, cgxb, 0, IF_BFP) + F(0xb3aa, CGXBR, RRF_e, Z, 0, x2, r1, 0, cgxb, 0, IF_BFP) /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) @@ -313,10 +313,10 @@ /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) - F(0xb39e, CLFXBR, RRF_e, FPE, x2h, x2l, new, r1_32, clfxb, 0, IF_BFP) + F(0xb39e, CLFXBR, RRF_e, FPE, 0, x2, new, r1_32, clfxb, 0, IF_BFP) F(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0, IF_BFP) F(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2, r1, 0, clgdb, 0, IF_BFP) - F(0xb3ae, CLGXBR, RRF_e, FPE, x2h, x2l, r1, 0, clgxb, 0, IF_BFP) + F(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2, r1, 0, clgxb, 0, IF_BFP) /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) @@ -343,7 +343,7 @@ C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, = 0) F(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0, IF_BFP) F(0xb31d, DDBR, RRE, Z, f1, f2, new, f1, ddb, 0, IF_BFP) - F(0xb34d, DXBR, RRE, Z, x2h, x2l, x1, x1, dxb, 0, IF_BFP) + F(0xb34d, DXBR, RRE, Z, x1, x2, new_x, x1, dxb, 0, IF_BFP) F(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0, IF_BFP) F(0xed1d, DDB, RXE, Z, f1, m2_64, new, f1, ddb, 0, IF_BFP) /* DIVIDE LOGICAL */ @@ -597,7 +597,7 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, 0, x2, new_x, x1, fixb, 0, IF_BFP) =20 /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) @@ -610,8 +610,8 @@ F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ F(0xb344, LEDBR, RRF_e, Z, 0, f2, new, e1, ledb, 0, IF_BFP) - F(0xb345, LDXBR, RRF_e, Z, x2h, x2l, new, f1, ldxb, 0, IF_BFP) - F(0xb346, LEXBR, RRF_e, Z, x2h, x2l, new, e1, lexb, 0, IF_BFP) + F(0xb345, LDXBR, RRF_e, Z, 0, x2, new, f1, ldxb, 0, IF_BFP) + F(0xb346, LEXBR, RRF_e, Z, 0, x2, new, e1, lexb, 0, IF_BFP) =20 /* LOAD MULTIPLE */ C(0x9800, LM, RS_a, Z, 0, a2, 0, 0, lm32, 0) @@ -666,7 +666,7 @@ C(0xe384, MG, RXY_a, MIE2,r1p1_o, m2_64, r1_P, 0, muls128, 0) F(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0, IF_BFP) F(0xb31c, MDBR, RRE, Z, f1, f2, new, f1, mdb, 0, IF_BFP) - F(0xb34c, MXBR, RRE, Z, x2h, x2l, x1, x1, mxb, 0, IF_BFP) + F(0xb34c, MXBR, RRE, Z, x1, x2, new_x, x1, mxb, 0, IF_BFP) F(0xb30c, MDEBR, RRE, Z, f1, e2, new, f1, mdeb, 0, IF_BFP) F(0xb307, MXDBR, RRE, Z, 0, f2, x1, x1, mxdb, 0, IF_BFP) F(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0, IF_BFP) @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, 0, x2, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) =20 @@ -913,7 +913,7 @@ C(0xe319, SGF, RXY_a, Z, r1, m2_32s, r1, 0, sub, subs64) F(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32, IF_BFP) F(0xb31b, SDBR, RRE, Z, f1, f2, new, f1, sdb, f64, IF_BFP) - F(0xb34b, SXBR, RRE, Z, x2h, x2l, x1, x1, sxb, f128, IF_BFP) + F(0xb34b, SXBR, RRE, Z, x1, x2, new_x, x1, sxb, f128, IF_BFP) F(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32, IF_BFP) F(0xed1b, SDB, RXE, Z, f1, m2_64, new, f1, sdb, f64, IF_BFP) /* SUBTRACT HALFWORD */ @@ -957,7 +957,7 @@ /* TEST DATA CLASS */ F(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0, IF_BFP) F(0xed11, TCDB, RXE, Z, f1, a2, 0, 0, tcdb, 0, IF_BFP) - F(0xed12, TCXB, RXE, Z, 0, a2, x1, 0, tcxb, 0, IF_BFP) + F(0xed12, TCXB, RXE, Z, x1, a2, 0, 0, tcxb, 0, IF_BFP) =20 /* TEST DECIMAL */ C(0xebc0, TP, RSL, E2, la1, 0, 0, 0, tp, 0) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 13be44499b..0bdab5bcf7 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -39,6 +39,11 @@ static inline Int128 RET128(float128 f) return int128_make128(f.low, f.high); } =20 +static inline float128 ARG128(Int128 i) +{ + return make_float128(int128_gethi(i), int128_getlo(i)); +} + uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { uint8_t s390_exc =3D 0; @@ -227,12 +232,9 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP addition */ -Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(axb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_add(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_add(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -254,12 +256,9 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP subtraction */ -Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(sxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_sub(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_sub(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -281,12 +280,9 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP division */ -Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_div(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_div(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -317,21 +313,18 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1= , uint64_t f2) } =20 /* 128-bit FP multiplication */ -Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(mxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret =3D float128_mul(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret =3D float128_mul(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } =20 /* 128/64-bit FP multiplication */ -Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t= f2) +Int128 HELPER(mxdb)(CPUS390XState *env, Int128 a, uint64_t f2) { float128 ret =3D float64_to_float128(f2, &env->fpu_status); - ret =3D float128_mul(make_float128(ah, al), ret, &env->fpu_status); + ret =3D float128_mul(ARG128(a), ret, &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -345,11 +338,10 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) } =20 /* convert 128-bit float to 64-bit float */ -uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(ldxb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float64 ret =3D float128_to_float64(make_float128(ah, al), &env->fpu_s= tatus); + float64 ret =3D float128_to_float64(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -384,11 +376,10 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2= , uint32_t m34) } =20 /* convert 128-bit float to 32-bit float */ -uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(lexb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float32 ret =3D float128_to_float32(make_float128(ah, al), &env->fpu_s= tatus); + float32 ret =3D float128_to_float32(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -412,11 +403,9 @@ uint32_t HELPER(cdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP compare */ -uint32_t HELPER(cxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(cxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp =3D float128_compare_quiet(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp =3D float128_compare_quiet(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -564,10 +553,10 @@ uint64_t HELPER(cgdb)(CPUS390XState *env, uint64_t v2= , uint32_t m34) } =20 /* convert 128-bit float to 64-bit int */ -uint64_t HELPER(cgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t= m34) +uint64_t HELPER(cgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); int64_t ret =3D float128_to_int64(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -613,10 +602,10 @@ uint64_t HELPER(cfdb)(CPUS390XState *env, uint64_t v2= , uint32_t m34) } =20 /* convert 128-bit float to 32-bit int */ -uint64_t HELPER(cfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t= m34) +uint64_t HELPER(cfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); int32_t ret =3D float128_to_int32(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -662,10 +651,10 @@ uint64_t HELPER(clgdb)(CPUS390XState *env, uint64_t v= 2, uint32_t m34) } =20 /* convert 128-bit float to 64-bit uint */ -uint64_t HELPER(clgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_= t m34) +uint64_t HELPER(clgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); uint64_t ret =3D float128_to_uint64(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -711,10 +700,10 @@ uint64_t HELPER(clfdb)(CPUS390XState *env, uint64_t v= 2, uint32_t m34) } =20 /* convert 128-bit float to 32-bit uint */ -uint64_t HELPER(clfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_= t m34) +uint64_t HELPER(clfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 =3D make_float128(h, l); + float128 v2 =3D ARG128(i2); uint32_t ret =3D float128_to_uint32(v2, &env->fpu_status); uint32_t cc =3D set_cc_conv_f128(v2, &env->fpu_status); =20 @@ -750,11 +739,10 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2= , uint32_t m34) } =20 /* round to integer 128-bit */ -Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t= m34) +Int128 HELPER(fixb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode =3D s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 ret =3D float128_round_to_int(make_float128(ah, al), - &env->fpu_status); + float128 ret =3D float128_round_to_int(ARG128(a), &env->fpu_status); =20 s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -778,11 +766,9 @@ uint32_t HELPER(kdb)(CPUS390XState *env, uint64_t f1, = uint64_t f2) } =20 /* 128-bit FP compare and signal */ -uint32_t HELPER(kxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(kxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp =3D float128_compare(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp =3D float128_compare(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -869,9 +855,9 @@ uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, = uint64_t m2) } =20 /* test data class 128-bit */ -uint32_t HELPER(tcxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64= _t m2) +uint32_t HELPER(tcxb)(CPUS390XState *env, Int128 a, uint64_t m2) { - return (m2 & float128_dcmask(env, make_float128(ah, al))) !=3D 0; + return (m2 & float128_dcmask(env, ARG128(a))) !=3D 0; } =20 /* square root 32-bit */ @@ -891,9 +877,9 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } =20 /* square root 128-bit */ -Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, Int128 a) { - float128 ret =3D float128_sqrt(make_float128(ah, al), &env->fpu_status= ); + float128 ret =3D float128_sqrt(ARG128(a), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0a750a5467..d422a1e62b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -305,6 +305,18 @@ static TCGv_i64 load_freg32_i64(int reg) return r; } =20 +static TCGv_i128 load_freg_128(int reg) +{ + TCGv_i64 h =3D load_freg(reg); + TCGv_i64 l =3D load_freg(reg + 2); + TCGv_i128 r =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(r, l, h); + tcg_temp_free_i64(h); + tcg_temp_free_i64(l); + return r; +} + static void store_reg(int reg, TCGv_i64 v) { tcg_gen_mov_i64(regs[reg], v); @@ -1103,7 +1115,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; - TCGv_i128 out_128; + TCGv_i128 out_128, in1_128, in2_128; } DisasOps; =20 /* Instructions can place constraints on their operands, raising specifica= tion @@ -1462,7 +1474,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_axb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -1778,7 +1790,7 @@ static DisasJumpType op_cdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_cxb(DisasContext *s, DisasOps *o) { - gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_cxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -1841,7 +1853,7 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1880,7 +1892,7 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1919,7 +1931,7 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1958,7 +1970,7 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -2445,7 +2457,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_dxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -2550,7 +2562,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); + gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2769,7 +2781,7 @@ static DisasJumpType op_kdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_kxb(DisasContext *s, DisasOps *o) { - gen_helper_kxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_kxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -2843,7 +2855,7 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2855,7 +2867,7 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -3584,13 +3596,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_mxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); + gen_helper_mxdb(o->out_128, cpu_env, o->in1_128, o->in2); return DISAS_NEXT; } =20 @@ -4055,7 +4067,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_sxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -4073,7 +4085,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); + gen_helper_sqxb(o->out_128, cpu_env, o->in2_128); return DISAS_NEXT; } =20 @@ -4852,7 +4864,7 @@ static DisasJumpType op_tcdb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o) { - gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2); + gen_helper_tcxb(cc_op, cpu_env, o->in1_128, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -5387,8 +5399,6 @@ static void prep_new_P(DisasContext *s, DisasOps *o) =20 static void prep_new_x(DisasContext *s, DisasOps *o) { - o->out =3D tcg_temp_new_i64(); - o->out2 =3D tcg_temp_new_i64(); o->out_128 =3D tcg_temp_new_i128(); } #define SPEC_prep_new_x 0 @@ -5411,10 +5421,7 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) =20 static void prep_x1(DisasContext *s, DisasOps *o) { - o->out =3D load_freg(get_field(s, r1)); - o->out2 =3D load_freg(get_field(s, r1) + 2); - o->out_128 =3D tcg_temp_new_i128(); - tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); + o->out_128 =3D load_freg_128(get_field(s, r1)); } #define SPEC_prep_x1 SPEC_r1_f128 =20 @@ -5513,6 +5520,11 @@ static void wout_x1(DisasContext *s, DisasOps *o) { int f1 =3D get_field(s, r1); =20 + /* Split out_128 into out+out2 for cout_f128. */ + tcg_debug_assert(o->out =3D=3D NULL); + o->out =3D tcg_temp_new_i64(); + o->out2 =3D tcg_temp_new_i64(); + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); @@ -5755,6 +5767,12 @@ static void in1_f1(DisasContext *s, DisasOps *o) } #define SPEC_in1_f1 0 =20 +static void in1_x1(DisasContext *s, DisasOps *o) +{ + o->in1_128 =3D load_freg_128(get_field(s, r1)); +} +#define SPEC_in1_x1 SPEC_r1_f128 + /* Load the high double word of an extended (128-bit) format FP number */ static void in1_x2h(DisasContext *s, DisasOps *o) { @@ -5964,6 +5982,12 @@ static void in2_f2(DisasContext *s, DisasOps *o) } #define SPEC_in2_f2 0 =20 +static void in2_x2(DisasContext *s, DisasOps *o) +{ + o->in2_128 =3D load_freg_128(get_field(s, r2)); +} +#define SPEC_in2_x2 SPEC_r2_f128 + /* Load the low double word of an extended (128-bit) format FP number */ static void in2_x2l(DisasContext *s, DisasOps *o) { @@ -6592,6 +6616,12 @@ static DisasJumpType translate_one(CPUS390XState *en= v, DisasContext *s) if (o.out_128) { tcg_temp_free_i128(o.out_128); } + if (o.in1_128) { + tcg_temp_free_i128(o.in1_128); + } + if (o.in2_128) { + tcg_temp_free_i128(o.in2_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Mon Feb 9 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146275785100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 -- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/mem_helper.c | 52 --------------------------- target/s390x/tcg/translate.c | 60 ++++++++++++++++++++------------ 4 files changed, 38 insertions(+), 78 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bccd3bfca6..341bc51ec2 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -35,8 +35,6 @@ DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i128, env, i64, i32) -DEF_HELPER_4(cdsg, void, env, i64, i32, i32) -DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 893f4b48db..ea34b4a277 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -276,7 +276,7 @@ /* COMPARE DOUBLE AND SWAP */ D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_= TEUQ) - C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) + C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, r1_D64, r1_D64, cdsg, 0) /* COMPARE AND SWAP AND STORE */ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) =20 diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 49969abda7..d6725fd18c 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1771,58 +1771,6 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r= 1, uint32_t r2, return cc; } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra =3D GETPC(); - Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); - Int128 oldv; - uint64_t oldh, oldl; - bool fail; - - check_alignment(env, addr, 16, ra); - - oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); - oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); - - oldv =3D int128_make128(oldl, oldh); - fail =3D !int128_eq(oldv, cmpv); - if (fail) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); - - env->cc_op =3D fail; - env->regs[r1] =3D int128_gethi(oldv); - env->regs[r1 + 1] =3D int128_getlo(oldv); -} - -void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra =3D GETPC(); - Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); - int mem_idx; - MemOpIdx oi; - Int128 oldv; - bool fail; - - assert(HAVE_CMPXCHG128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - fail =3D !int128_eq(oldv, cmpv); - - env->cc_op =3D fail; - env->regs[r1] =3D int128_gethi(oldv); - env->regs[r1 + 1] =3D int128_getlo(oldv); -} - static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d422a1e62b..0dafa27dab 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2224,31 +2224,22 @@ static DisasJumpType op_cs(DisasContext *s, DisasOp= s *o) static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) { int r1 =3D get_field(s, r1); - int r3 =3D get_field(s, r3); - int d2 =3D get_field(s, d2); - int b2 =3D get_field(s, b2); - DisasJumpType ret =3D DISAS_NEXT; - TCGv_i64 addr; - TCGv_i32 t_r1, t_r3; =20 - /* Note that R1:R1+1 =3D expected value and R3:R3+1 =3D new value. */ - addr =3D get_address(s, 0, b2, d2); - t_r1 =3D tcg_const_i32(r1); - t_r3 =3D tcg_const_i32(r3); - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); - } else if (HAVE_CMPXCHG128) { - gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); - } else { - gen_helper_exit_atomic(cpu_env); - ret =3D DISAS_NORETURN; - } - tcg_temp_free_i64(addr); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r3); + /* Note out (R1:R1+1) =3D expected value and in2 (R3:R3+1) =3D new val= ue. */ + tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_1= 28, + get_mem_index(s), MO_BE | MO_128 | MO_ALIG= N); =20 - set_cc_static(s); - return ret; + /* + * Extract result into cc_dst:cc_src, compare vs the expected value + * in the as yet unmodified input registers, then update CC_OP. + */ + tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128); + tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]); + tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]); + tcg_gen_or_i64(cc_dst, cc_dst, cc_src); + set_cc_nz_u64(s, cc_dst); + + return DISAS_NEXT; } =20 static DisasJumpType op_csst(DisasContext *s, DisasOps *o) @@ -5419,6 +5410,14 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even =20 +static void prep_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 =3D get_field(s, r1); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]); +} +#define SPEC_prep_r1_D64 SPEC_r1_even + static void prep_x1(DisasContext *s, DisasOps *o) { o->out_128 =3D load_freg_128(get_field(s, r1)); @@ -5488,6 +5487,13 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) } #define SPEC_wout_r1_D32 SPEC_r1_even =20 +static void wout_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 =3D get_field(s, r1); + tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128); +} +#define SPEC_wout_r1_D64 SPEC_r1_even + static void wout_r3_P32(DisasContext *s, DisasOps *o) { int r3 =3D get_field(s, r3); @@ -5935,6 +5941,14 @@ static void in2_r3(DisasContext *s, DisasOps *o) } #define SPEC_in2_r3 0 =20 +static void in2_r3_D64(DisasContext *s, DisasOps *o) +{ + int r3 =3D get_field(s, r3); + o->in2_128 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]); +} +#define SPEC_in2_r3_D64 SPEC_r3_even + static void in2_r3_sr32(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673145973; cv=none; d=zohomail.com; s=zohoarc; b=EPmcCNuNkM26fDdQroos1Az4thpyVtlVUQQZv0kbgveJXaHuzayv+jzgSAhY8LHurPS5hOZOM+4fHtCoOVvYmM62byCjoiSJTSSLSEl+KTkeNP808/VTbgeI/tzMMd0Lfqnu/jSbV1UyPi5H+2zCJJ+eS052QOh/ysvTWQSaj08= ARC-Message-Signature: i=1; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MdHoeH+hZ0t51S2EuQPsB5HeY/0JCfhoxTNUbpkf+2E=; b=XPo5xEUOrItF78dICgV6Q+o2yG+GIWyORRH2fq0KKJYRWTh2LPUmJ39WfST6SXa1Ee LX54/sh5jWr90y0USup6xo/zHnvJe9n2DOQG2UpIlqZNZflG8/q151TbDSbOLHgjdrfj 4oRycYWSxXZ5mnIvfzTQ/Sz6PqjAQAHKHq8uHTKHNRSM9HtFWjCexHygTW0BxJXJMJyJ MCia3QHaSJEp+0Dl1nnBhZnPINcrTSLlBHopy4Bhsd08+Nc3JJNusfe8yH9hOh0qNDsi 5u6D0VcWov+bT/RZT2rS0Fj1haEm/WVsnds3cLJV3mj+uyrE05/whMH0WLtvasUXS5i1 ekhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MdHoeH+hZ0t51S2EuQPsB5HeY/0JCfhoxTNUbpkf+2E=; b=0ebKee81XnPnf/GZ2m97bGj/C9Lnqa0FZBSuFQ1bvSdnHgwJG35Ew5FM+DNfXvgv+D VM5/SO3Qhq7+epuP4E+YgMTkkCaRcY3lNyV1MXCCmyzvRhc0ax6FGsmJkF4sMfkN9V75 z1J5v5nZNdWyo5RIze/y3ZFa64PUe5sd3Gx8g9ssKPLASfkpI2VC8XNzZK5NQSgiVNkK OBtu+8b6w9yuNr3MEn8+3mZB7LBfRiNIG4DOpoEVzg680iNg2k2GctrW5i4Fwde7EsSg /qSgVXEeXKhawvn4TL9JArw14mvFbwdTy+muyZvalLTu0YQe4927BBKQgTaRmynEF3UP l2HQ== X-Gm-Message-State: AFqh2kqmiE7EKC6D+3tggXWvy10CeuJxvJEASkyI0r0HggPK8tWuiz3q +kkOMiiGNjrRndiOHJEplb26xo9ap1b6gRXS X-Google-Smtp-Source: AMrXdXtE7kZ6fmDjzr7ktyC/V62m5EKKHyaGI3BuJ3qLC32xs1VMRPmbrHwXH5u8gjU9GcwyEMZyzw== X-Received: by 2002:a17:902:7d93:b0:186:644f:bef1 with SMTP id a19-20020a1709027d9300b00186644fbef1mr65128014plm.6.1673145477997; Sat, 07 Jan 2023 18:37:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 33/36] target/s390x: Implement CC_OP_NZ in gen_op_calc_cc Date: Sat, 7 Jan 2023 18:37:16 -0800 Message-Id: <20230108023719.2466341-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673145975611100008 Content-Type: text/plain; charset="utf-8" This case is trivial to implement inline. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0dafa27dab..b8cb21c395 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -625,6 +625,9 @@ static void gen_op_calc_cc(DisasContext *s) /* env->cc_op already is the cc value */ break; case CC_OP_NZ: + tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0); + tcg_gen_extrl_i64_i32(cc_op, cc_dst); + break; case CC_OP_ABS_64: case CC_OP_NABS_64: case CC_OP_ABS_32: --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146323; cv=none; d=zohomail.com; s=zohoarc; b=kCRBT9CEYKaPgE8UXGW7kWkWHQBCrNA3nlJlb1RIrHcBE0pVGAO/DIPRRwx9kdhKLJVCU7Qj2w0bch/xNC2ODM7nJOAFai9Enap9vNO4yTc9McNvGp+j3/QLCOhBfHAVlyHfuUSsBg7QhN+k/9GnF00D4enabCTuy2SM6lZS5KM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146323; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9ScRTiCetY4GULFmLSkWpnFNmGzWjdbMDLDjsbqu5fo=; b=IYF+pNbzpGHR7aGf+TQ1ys4UyHs9V/oSmFpWp1Ws2LlYAR80k8wb9b02z7mXkT3m0NFzR+Jw/sT/OfNZs8eccS5ntRcI/kXwx61/f7di4V8A/cRKlpKu2Q4INr7yDnDfombNU/4JbeJ1b5iPdyM2GB52fggO9ev6MRuF2SxD84E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16731463234091001.4530152970027; Sat, 7 Jan 2023 18:52:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELai-0006mx-G4; Sat, 07 Jan 2023 21:39:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaR-0006Zq-Lh for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:39:03 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZP-0004UT-P7 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:39:03 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9so5859943pll.9 for ; Sat, 07 Jan 2023 18:37:59 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9ScRTiCetY4GULFmLSkWpnFNmGzWjdbMDLDjsbqu5fo=; b=TOAXi5LNjIeY1nkvmNKr1LLyMMYFpHORFQuq1LndUTcqcW19FupH/WNFkTSqWN4rLE 4wt69j5xi2rQiFDqzem5zig+c29iLZJ3+RjDM4qc0pGvl0RBfz5lt/FgLanpFmqCMnVe PozALU5VBxd7h63o5rnKun4r2UJG/Wy2z0TlXW7JJRWi9wle9q9/gq05rab5xS7J1Gjw 93X6ifPoHPkeQy5TEZmmbUb3P0BufSHolivO079loX6zKFFFQM6E3Uvl4A4rLZ/DhVlz OJbGCtNekzyKOBmqHMtlCB+qWSqO+ZvqbLTVvFBXDigWzanuETn8rNH70KE30/ywiPds AbTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9ScRTiCetY4GULFmLSkWpnFNmGzWjdbMDLDjsbqu5fo=; b=hreBfG2ryoIy1G4Bsow39FG/pWcks8HKiEPQfoVkwnk03pTDnY9uONb0ZMh2//EmOG CzVjlW25ModcKVXIYFIggpT2PQ4nd5fXBiDenQH85aR4cdXy26BQMebkFwSZiR0ZdwCe UQsIY4UfoYqsVfUqLaBV9XvxEgAlePimklh1N9GelA1T5ZfSKHlHGg+TPjIKO5nNeLWr wnSlfZS9jpoAqeJi4E/KCibcmnBVbw4gjDlIBEtaSwilNHJ63fcrl6vF6v8Agp5sb4Jq MWOypkfFKunv5bvva2UJ+3sDDFYmQXmy77LNLqdEN52vbjrf8p27yYw9ljLBUO282tFY hf4w== X-Gm-Message-State: AFqh2kqwiSOqWmVn16gdQ/PGj4rEPjZA0tSd9FVOjcpyYaFn5zXkUfcn LBd+IuAkKNSy3fdWIGNqpsIcAgal3jw6dbLr X-Google-Smtp-Source: AMrXdXsffHGUNC1FPVOOyvPzoLG6DHbo1HOOC+3BkFPxIrPU8WfHrlZT9WG8uGe2vb/VQSUvC69/2w== X-Received: by 2002:a17:902:cf09:b0:191:3e64:a5ff with SMTP id i9-20020a170902cf0900b001913e64a5ffmr83605253plg.68.1673145479006; Sat, 07 Jan 2023 18:37:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 34/36] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Date: Sat, 7 Jan 2023 18:37:17 -0800 Message-Id: <20230108023719.2466341-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146323957100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/tcg/translate.c | 48 ++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e0b2a709a..a82131d635 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2993,6 +2993,34 @@ static void gen_sty_env_A0(DisasContext *s, int offs= et, bool align) #include "emit.c.inc" #include "decode-new.c.inc" =20 +static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg8b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} + +#ifdef TARGET_X86_64 +static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg16b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} +#endif + /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static bool disas_insn(DisasContext *s, CPUState *cpu) @@ -3844,28 +3872,14 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg16b(s, env, modrm); break; } -#endif =20 +#endif if (!(s->cpuid_features & CPUID_CX8)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg8b(s, env, modrm); break; =20 case 7: /* RDSEED */ --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146059; cv=none; d=zohomail.com; s=zohoarc; b=FEO0KGktHqUVPILQdPDfqqNx14EROj2CCWB0SvzKFdS4BOVaFBU+AsTs16H/CStYL8tpyhHi2vkasjpRrkpfYud1yY6EHrbEzZ7hA5ljI5gjWt9AuWj/vluhvhnSW/U+hMYYeVY0G1+c/U+GEe1HTWm/OIyc250bOTRp2xqGeN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146059; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3xrOaDJVPE/CmdkY8im+Dl4QkQvUXux7CRjkgzX7WCc=; b=emlncycWqAC4J4Gg0izaAe9+WP1qJnMP+RW9pSg2gLvGfIkL77AC/s1F5eKvk78zSpBIWsZth0G7so4vwdftQXZ+TwfDJ1Jazs40TgV01aJKHdzOGyLktgnx+R6LJLShP/kRpbxxzFbrDzw2GCKcpaDeTuHz557fuIGvjP6Q9S4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146059492681.1103141626352; Sat, 7 Jan 2023 18:47:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELam-0006y0-42; Sat, 07 Jan 2023 21:39:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaa-0006hs-Vg for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:39:13 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZR-0004oL-7B for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:39:05 -0500 Received: by mail-pj1-x102f.google.com with SMTP id c8-20020a17090a4d0800b00225c3614161so9249687pjg.5 for ; Sat, 07 Jan 2023 18:38:00 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3xrOaDJVPE/CmdkY8im+Dl4QkQvUXux7CRjkgzX7WCc=; b=Vr7pPQ0Vc0da8CqPlxQPFJ4iAo8IUHkomwGS3CyijOiziB7ECFHyQEeK4aFoJZLz7q S7fxY59hce7PqHpOkqVNUeTFwZhS68Ef/TTfCLwopjG29LAqTX11JnCX8LwO5kM35E1V 8quXLh8FYORyUirF3vO/1PscXa6siTIIGsVEo5mKLkZGi7qUEpM0F8jFU07I9LKKcZ5z GEQXkvMEhf2hqOCeUsvErTt0UVDnFsP5Ptwj9BG9TiuF/NoknW2RcIGlj0J+Wb7W61oR 53AvWjCV22JwemnUIvnYW10INtjETRKRGAfOYCpmhiee/jsqvFySxNy3s1OQEGSfKed2 sdyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3xrOaDJVPE/CmdkY8im+Dl4QkQvUXux7CRjkgzX7WCc=; b=sAuPV24Ew+Sj3N9ezGQ2NRkWbxLEGoJLJsEcZ8fnMcuI7iTCPo3CRj45P9jt8XEnc1 wL1dKdZ4FdpO+x2NghOJhhWdhPf6CkvkLD3Y0d+Cp9z3LGNfNfMn6GydshAn9mh3vt/v Lq224oQvq836Ln9BSEutRjWnK9/UtxKqKmTfqXaNqgCN6rVfUwvgzuWznySl/qe87vRM FEICkodQhd9PD4fpIWP6+oyWOhynWHfNg/XpQTJ98DP+V0bCp2sx1Dl7yZz5FmxcsSNc SW7gpPlOvktqzgkJM5n9uvvwAzX1o5ebGOQmY11uo0Ceo7OyIKKhPW006i/qXMlzz4PY Mb3w== X-Gm-Message-State: AFqh2kpQgNRkiyiIMlFwWh3GEvkiTylMb4azBViP5AYiH13zI4ee0bXN 2hBYauzVAe4zmxURE991CAU68urPtNOlckiQ X-Google-Smtp-Source: AMrXdXs6zlYtsN5O8W75nSeo0sOtBsn4uHgAwLvWjHAUGY8YABkDmResS2O353GK6NBU4IEM9CVcvw== X-Received: by 2002:a17:902:b609:b0:192:4ed2:7509 with SMTP id b9-20020a170902b60900b001924ed27509mr62839722pls.15.1673145480024; Sat, 07 Jan 2023 18:38:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 35/36] target/i386: Inline cmpxchg8b Date: Sat, 7 Jan 2023 18:37:18 -0800 Message-Id: <20230108023719.2466341-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146061168100003 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57 ------------------------------------ target/i386/tcg/translate.c | 54 ++++++++++++++++++++++++++++++---- 3 files changed, 49 insertions(+), 64 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index b7de5429ef..2df8049f91 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,8 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -DEF_HELPER_2(cmpxchg8b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg8b, void, env, tl) #ifdef TARGET_X86_64 DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e3cdafd2d4..814786bb87 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,63 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - oldv =3D cpu_ldq_data_ra(env, a0, ra); - newv =3D (cmpv =3D=3D oldv ? newv : oldv); - /* always do the store */ - cpu_stq_data_ra(env, a0, newv, ra); - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) -{ -#ifdef CONFIG_ATOMIC64 - uint64_t oldv, cmpv, newv; - int eflags; - - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - { - uintptr_t ra =3D GETPC(); - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mem_idx); - oldv =3D cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); - } - - if (oldv =3D=3D cmpv) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D (uint32_t)oldv; - env->regs[R_EDX] =3D (uint32_t)(oldv >> 32); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -#else - cpu_loop_exit_atomic(env_cpu(env), GETPC()); -#endif /* CONFIG_ATOMIC64 */ -} - #ifdef TARGET_X86_64 void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a82131d635..b542b084a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2995,15 +2995,59 @@ static void gen_sty_env_A0(DisasContext *s, int off= set, bool align) =20 static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) { + TCGv_i64 cmp, val, old; + TCGv Z; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i64(); + val =3D tcg_temp_new_i64(); + old =3D tcg_temp_new_i64(); + + /* Construct the comparison values from the register pair. */ + tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_= TEUQ); } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, + s->mem_index, MO_TEUQ); } - set_cc_op(s, CC_OP_EFLAGS); + tcg_temp_free_i64(val); + + /* Set tmp0 to match the required value of Z. */ + tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); + Z =3D tcg_temp_new(); + tcg_gen_trunc_i64_tl(Z, cmp); + tcg_temp_free_i64(cmp); + + /* + * Extract the result values for the register pair. + * For 32-bit, we may do this unconditionally, because on success (Z= =3D1), + * the old value matches the previous value in EDX:EAX. For x86_64, + * the store must be conditional, because we must leave the source + * registers unchanged on success, and zero-extend the writeback + * on failure (Z=3D0). + */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); + } else { + TCGv zero =3D tcg_constant_tl(0); + + tcg_gen_extr_i64_tl(s->T0, s->T1, old); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, + s->T0, cpu_regs[R_EAX]); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, + s->T1, cpu_regs[R_EDX]); + } + tcg_temp_free_i64(old); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); + tcg_temp_free(Z); } =20 #ifdef TARGET_X86_64 --=20 2.34.1 From nobody Mon Feb 9 15:03:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1673146224; cv=none; d=zohomail.com; s=zohoarc; b=EkFfNuCLQ4pdFSfYbZEz1d6tFxTCmiwhdWkP+sFgY71LMBPJrVjUtHnocyul2Qxugld3EWNoo9x3bR7XBlNflYMfrFM2mkMZFGz6LNwYvUXGyB2/uGy0exChfqouAcplpbdQglsW1x3WM6yNdaU7Y79IXyQ8mWblkXMegrKpUlM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673146224; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mhr3QIUQO1GxMkIggU7JbqoOmehoWj07MLx7q6K4qDk=; b=Fx1OUfw4sbZQiTV15OJi+lgySQ+9aYK5Ephm1y9LVkD7UreBTvnOoPiEekCKmd3PzWqDqW6dJKM6YyCMthHbQoJhHgkbnT74PClMZca2E55UIp5TciYoYcTCHghZdt4h2RpTjxlG0iI0KQevWE3TUdQIkd5mxmipt4ryWGK/6C8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673146224528115.84011686443671; Sat, 7 Jan 2023 18:50:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pELaj-0006ph-HI; Sat, 07 Jan 2023 21:39:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaa-0006hw-W5 for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:39:13 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZR-0004Y1-Tj for qemu-devel@nongnu.org; Sat, 07 Jan 2023 21:39:09 -0500 Received: by mail-pj1-x1036.google.com with SMTP id o7-20020a17090a0a0700b00226c9b82c3aso5820793pjo.3 for ; Sat, 07 Jan 2023 18:38:01 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:38:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mhr3QIUQO1GxMkIggU7JbqoOmehoWj07MLx7q6K4qDk=; b=hYrKynyZZDUSofsJs+xXcMB7/0fMnugQQY67q1cmym7W3997wg5VycoQ2RkOmRpSZt QdSdaHQDlpuna7ZYoyiqCBVAfxxxttbloqn8SXWa9g8Q4BgJTRs5gmdyPwgbwLFtQesM uL5f2e49JZVqm3/o2RRsPLPyXWR0xKVL3uk1bk1vJFaxquAGmD36KprD3yZn/BkzLGU5 DtwkqDeAdyMQOZDO7lwqhG1GahbRhVh6B0LZ44P2eRiDWtmVEHDAfBZj3qRTSwxY0GYC olI4A6VwTXVt/n4SXwwwHhFHZ882snHmHDJP38qXKstVeLZEzweh96+KYL5Igdb7wd83 1a6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mhr3QIUQO1GxMkIggU7JbqoOmehoWj07MLx7q6K4qDk=; b=aVrDkcNXVSKuFeXHQ63K8lsQyu/0V+zEww1jFBfJuxPSEb4wZhHC5xfRtNKnc2B1ci bhgUs2ZQo+jbktvdCTZUOXDQg8OPlCDG6ExcoTIKpZlLFXhB4xrs/MSDSS23Fo6/s8Lv NnKoJIa76UBRQP3oKSY1QLN+DRCwTuq5EjFWxVl8LrTnWrxE6nCZR+HmbeeS56yDcrrs tWXaUhoIZXHhXKGR0IEXFjW2KkdM9cY8gB3P1hynZLQSvVD3w6IosO4SXZDLFn9zBeEv 2Qx2l/ufrJcCN4cGSXREWHOWzTTsXSKgxGYIex7McW8Q4r1y8Uc4FI016iRkyIlR1uja 4JAw== X-Gm-Message-State: AFqh2krTR09UjiYwKQVJuREk3fTEBqhvzn7Bz3u6Q7mop9f9QE/HjGQF hCrZniYCo2jejWLU1A8/s+h2nyHWMPlpab7q X-Google-Smtp-Source: AMrXdXuTipe2JW3Lp97w1VhX2lUzlidEeI3sBYhB+s+uPaVq5nPRmTqf3B1ngjjIHB7MP7xL0SSVMA== X-Received: by 2002:a17:903:2312:b0:192:8c7f:2654 with SMTP id d18-20020a170903231200b001928c7f2654mr53462869plh.0.1673145481048; Sat, 07 Jan 2023 18:38:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 36/36] target/i386: Inline cmpxchg16b Date: Sat, 7 Jan 2023 18:37:19 -0800 Message-Id: <20230108023719.2466341-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1673146225598100005 Content-Type: text/plain; charset="utf-8" Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Signed-off-by: Richard Henderson --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69 ------------------------------------ target/i386/tcg/translate.c | 44 ++++++++++++++++++++--- 3 files changed, 39 insertions(+), 78 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 2df8049f91..e627a93107 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,10 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ =20 DEF_HELPER_2(into, void, env, int) -#ifdef TARGET_X86_64 -DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg16b, void, env, tl) -#endif DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 814786bb87..3ef84e90d9 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,75 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" =20 -#ifdef TARGET_X86_64 -void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - Int128 oldv, cmpv, newv; - uint64_t o0, o1; - int eflags; - bool success; - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - eflags =3D cpu_cc_compute_all(env, CC_OP); - - cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - o0 =3D cpu_ldq_data_ra(env, a0 + 0, ra); - o1 =3D cpu_ldq_data_ra(env, a0 + 8, ra); - - oldv =3D int128_make128(o0, o1); - success =3D int128_eq(oldv, cmpv); - if (!success) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra); - cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra); - - if (success) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; -} - -void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra =3D GETPC(); - - if ((a0 & 0xf) !=3D 0) { - raise_exception_ra(env, EXCP0D_GPF, ra); - } else if (HAVE_CMPXCHG128) { - int eflags =3D cpu_cc_compute_all(env, CC_OP); - - Int128 cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - Int128 newv =3D int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - int mem_idx =3D cpu_mmu_index(env, false); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); - - if (int128_eq(oldv, cmpv)) { - eflags |=3D CC_Z; - } else { - env->regs[R_EAX] =3D int128_getlo(oldv); - env->regs[R_EDX] =3D int128_gethi(oldv); - eflags &=3D ~CC_Z; - } - CC_SRC =3D eflags; - } else { - cpu_loop_exit_atomic(env_cpu(env), ra); - } -} -#endif - void helper_boundw(CPUX86State *env, target_ulong a0, int v) { int low, high; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b542b084a6..9d9392b009 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3053,15 +3053,49 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) #ifdef TARGET_X86_64 static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) { + MemOp mop =3D MO_TE | MO_128 | MO_ALIGN; + TCGv_i64 t0, t1; + TCGv_i128 cmp, val; + gen_lea_modrm(env, s, modrm); =20 - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); + cmp =3D tcg_temp_new_i128(); + val =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mo= p); } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index,= mop); } - set_cc_op(s, CC_OP_EFLAGS); + + tcg_gen_extr_i128_i64(s->T0, s->T1, val); + tcg_temp_free_i128(cmp); + tcg_temp_free_i128(val); + + /* Determine success after the fact. */ + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); + tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); + tcg_gen_or_i64(t0, t0, t1); + tcg_temp_free_i64(t1); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); + tcg_temp_free_i64(t0); + + /* + * Extract the result values for the register pair. We may do this + * unconditionally, because on success (Z=3D1), the old value matches + * the previous value in RDX:RAX. + */ + tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); + tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); } #endif =20 --=20 2.34.1