From nobody Sun Feb 8 01:16:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1673026191; cv=none; d=zohomail.com; s=zohoarc; b=gMcoU+ntsDSDQD+O5LVj0aVGyxZFMIsEnlxcqRxeS3xy+igdpJyKSfKqTSL4Npd5VdEpbNQEsNMBq0eUDiSh5PAlrEOzccJqe6TwTIsJ+LDuTsvGRavYo2f8x1sNpfnl6EuWBvAixL+BZRXBIO0as2kywP1aK7MiAJA2tiMPp8Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673026191; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fD2O4oH0Dmzzf9G/fxXOTB0KtH4/XlayZhdCdYqGvhQ=; b=C65oypgwzdkY61tGpcIEtav1vW0ejvej9rQZTLzGoYVTy/6Q2F7mfvW5/lyyokklyA9zHQGYPUEt27iZ9i2vlSpj9T+LcD8gTvGR0s0dXlwxO4ar71DS5ZrJcGehkI24gZ+WmzQI8c67ETG/Bzw9fZPkaqaHEn79+wBKoUOMqko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1673026191548252.31350714709367; Fri, 6 Jan 2023 09:29:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDqWg-0004S9-ID; Fri, 06 Jan 2023 12:29:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDqWc-0004Pw-3b; Fri, 06 Jan 2023 12:29:02 -0500 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDqWa-0004VB-C9; Fri, 06 Jan 2023 12:29:01 -0500 Received: from localhost.localdomain (unknown [77.64.253.186]) by linux.microsoft.com (Postfix) with ESMTPSA id C424620B92AC; Fri, 6 Jan 2023 09:28:57 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com C424620B92AC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1673026139; bh=fD2O4oH0Dmzzf9G/fxXOTB0KtH4/XlayZhdCdYqGvhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MBT+QwsH2NSK1PbRq0f1N5RD/AgAWeD8Jp2LCJU+yeJY0cYJHjGzZN2Rrn9d208pk y50JGLxmjH+J3xbj++kPx/+5P3QuSE0jOyVVTG4v+lVh1/yIr1I1CIQvnXRfg8n3B2 gHeurOG1udYIr6iOuzxPAS/zqijBFozzb+gUQ698= From: Evgeny Iakovlev To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, marcandre.lureau@redhat.com, pbonzini@redhat.com, peter.maydell@linaro.org Subject: [PATCH 1/2] hw/char/pl011: better handling of FIFO flags on LCR reset Date: Fri, 6 Jan 2023 18:28:50 +0100 Message-Id: <20230106172851.2430-2-eiakovlev@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106172851.2430-1-eiakovlev@linux.microsoft.com> References: <20230106172851.2430-1-eiakovlev@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=eiakovlev@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -197 X-Spam_score: -19.8 X-Spam_bar: ------------------- X-Spam_report: (-19.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1673026193794100003 Content-Type: text/plain; charset="utf-8" Current FIFO handling code does not reset RXFE/RXFF flags when guest resets FIFO by writing to UARTLCR register, although internal FIFO state is reset to 0 read count. Actual flag update will happen only on next read or write to UART. As a result of that any guest that expects RXFE flag to be set (and RXFF to be cleared) after resetting FIFO will just hang. Correctly reset FIFO flags on FIFO reset. Also, clean up some FIFO depth handling code based on current FIFO mode. Signed-off-by: Evgeny Iakovlev --- hw/char/pl011.c | 35 +++++++++++++++++++++-------------- include/hw/char/pl011.h | 5 ++++- 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c076813423..9108ed2be9 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -81,6 +81,18 @@ static void pl011_update(PL011State *s) } } =20 +static inline unsigned pl011_get_fifo_depth(PL011State *s) +{ + return s->lcr & 0x10 ? PL011_FIFO_DEPTH : 1; +} + +static inline void pl011_reset_pipe(PL011State *s) +{ + s->read_count =3D 0; + s->read_pos =3D 0; + s->flags =3D PL011_FLAG_RXFE | PL011_FLAG_TXFE; +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { @@ -94,7 +106,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, c =3D s->read_fifo[s->read_pos]; if (s->read_count > 0) { s->read_count--; - if (++s->read_pos =3D=3D 16) + if (++s->read_pos =3D=3D PL011_FIFO_DEPTH) s->read_pos =3D 0; } if (s->read_count =3D=3D 0) { @@ -229,8 +241,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & 0x10) { - s->read_count =3D 0; - s->read_pos =3D 0; + pl011_reset_pipe(s); } if ((s->lcr ^ value) & 0x1) { int break_enable =3D value & 0x1; @@ -273,11 +284,7 @@ static int pl011_can_receive(void *opaque) PL011State *s =3D (PL011State *)opaque; int r; =20 - if (s->lcr & 0x10) { - r =3D s->read_count < 16; - } else { - r =3D s->read_count < 1; - } + r =3D s->read_count < pl011_get_fifo_depth(s); trace_pl011_can_receive(s->lcr, s->read_count, r); return r; } @@ -286,15 +293,15 @@ static void pl011_put_fifo(void *opaque, uint32_t val= ue) { PL011State *s =3D (PL011State *)opaque; int slot; + unsigned pipe_depth; =20 - slot =3D s->read_pos + s->read_count; - if (slot >=3D 16) - slot -=3D 16; + pipe_depth =3D pl011_get_fifo_depth(s); + slot =3D (s->read_pos + s->read_count) % pipe_depth; s->read_fifo[slot] =3D value; s->read_count++; s->flags &=3D ~PL011_FLAG_RXFE; trace_pl011_put_fifo(value, s->read_count); - if (!(s->lcr & 0x10) || s->read_count =3D=3D 16) { + if (s->read_count =3D=3D pipe_depth) { trace_pl011_put_fifo_full(); s->flags |=3D PL011_FLAG_RXFF; } @@ -359,7 +366,7 @@ static const VMStateDescription vmstate_pl011 =3D { VMSTATE_UINT32(dmacr, PL011State), VMSTATE_UINT32(int_enabled, PL011State), VMSTATE_UINT32(int_level, PL011State), - VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16), + VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH), VMSTATE_UINT32(ilpr, PL011State), VMSTATE_UINT32(ibrd, PL011State), VMSTATE_UINT32(fbrd, PL011State), @@ -399,7 +406,7 @@ static void pl011_init(Object *obj) s->read_trigger =3D 1; s->ifl =3D 0x12; s->cr =3D 0x300; - s->flags =3D 0x90; + pl011_reset_pipe(s); =20 s->id =3D pl011_id_arm; } diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index dc2c90eedc..926322e242 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -27,6 +27,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011) /* This shares the same struct (and cast macro) as the base pl011 device */ #define TYPE_PL011_LUMINARY "pl011_luminary" =20 +/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth =3D= =3D 1) */ +#define PL011_FIFO_DEPTH 16 + struct PL011State { SysBusDevice parent_obj; =20 @@ -39,7 +42,7 @@ struct PL011State { uint32_t dmacr; uint32_t int_enabled; uint32_t int_level; - uint32_t read_fifo[16]; + uint32_t read_fifo[PL011_FIFO_DEPTH]; uint32_t ilpr; uint32_t ibrd; uint32_t fbrd; --=20 2.34.1 From nobody Sun Feb 8 01:16:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1673026140; bh=RNl0RohGyGYaN8i6oHuZhCcSkYfrH1wD8BSvwo4RLCY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IR11832L5qPu01VVESf/DM7MzzqP4FArqP2xn1fqcxjm1vVwfrSLpZI8Vc6J0Wqsq 3xIAlg5+5bMFgAZFJpgPKaz/KITItnofRyys/jetlNDZcFSIkQOdqpBM0TSO99DXfy PO2RYZp5A93ZgvLcUWSHeFx4MExwHaVL/LvKjXyg= From: Evgeny Iakovlev To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, marcandre.lureau@redhat.com, pbonzini@redhat.com, peter.maydell@linaro.org Subject: [PATCH 2/2] hw/char/pl011: check if UART is enabled before RX or TX operation Date: Fri, 6 Jan 2023 18:28:51 +0100 Message-Id: <20230106172851.2430-3-eiakovlev@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106172851.2430-1-eiakovlev@linux.microsoft.com> References: <20230106172851.2430-1-eiakovlev@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=eiakovlev@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -197 X-Spam_score: -19.8 X-Spam_bar: ------------------- X-Spam_report: (-19.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1673026201801100003 Content-Type: text/plain; charset="utf-8" UART should be enabled in general and have RX enabled specifically to be able to receive data from peripheral device. Same goes for transmitting data to peripheral device and a TXE flag. Check if UART CR register has EN and RXE or TXE bits enabled before trying to receive or transmit data. Signed-off-by: Evgeny Iakovlev Reviewed-by: Peter Maydell --- hw/char/pl011.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 9108ed2be9..fcc2600944 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -54,6 +54,11 @@ #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) =20 +/* UARTCR bits */ +#define PL011_CR_UARTEN (1 << 0) +#define PL011_CR_TXE (1 << 8) +#define PL011_CR_RXE (1 << 9) + static const unsigned char pl011_id_arm[8] =3D { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] =3D @@ -203,6 +208,11 @@ static void pl011_trace_baudrate_change(const PL011Sta= te *s) s->ibrd, s->fbrd); } =20 +static inline bool pl011_can_transmit(PL011State *s) +{ + return s->cr & PL011_CR_UARTEN && s->cr & PL011_CR_TXE; +} + static void pl011_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -213,7 +223,9 @@ static void pl011_write(void *opaque, hwaddr offset, =20 switch (offset >> 2) { case 0: /* UARTDR */ - /* ??? Check if transmitter is enabled. */ + if (!pl011_can_transmit(s)) { + break; + } ch =3D value; /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ @@ -284,7 +296,11 @@ static int pl011_can_receive(void *opaque) PL011State *s =3D (PL011State *)opaque; int r; =20 - r =3D s->read_count < pl011_get_fifo_depth(s); + if (!(s->cr & PL011_CR_UARTEN) || !(s->cr & PL011_CR_RXE)) { + r =3D 0; + } else { + r =3D s->read_count < pl011_get_fifo_depth(s); + } trace_pl011_can_receive(s->lcr, s->read_count, r); return r; } @@ -405,7 +421,7 @@ static void pl011_init(Object *obj) =20 s->read_trigger =3D 1; s->ifl =3D 0x12; - s->cr =3D 0x300; + s->cr =3D PL011_CR_RXE | PL011_CR_TXE; pl011_reset_pipe(s); =20 s->id =3D pl011_id_arm; --=20 2.34.1