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a="408688499" X-IronPort-AV: E=Sophos;i="5.96,304,1665471600"; d="scan'208";a="408688499" X-IronPort-AV: E=McAfee;i="6500,9779,10581"; a="724378847" X-IronPort-AV: E=Sophos;i="5.96,304,1665471600"; d="scan'208";a="724378847" From: Lei Wang To: pbonzini@redhat.com Cc: qemu-devel@nongnu.org, imammedo@redhat.com, dgilbert@redhat.com, berrange@redhat.com, xiaoyao.li@intel.com, yang.zhong@linux.intel.com, lei4.wang@intel.com Subject: [PATCH v3 4/6] i386: Mask and report unavailable multi-bit feature values Date: Fri, 6 Jan 2023 00:38:24 -0800 Message-Id: <20230106083826.5384-5-lei4.wang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230106083826.5384-1-lei4.wang@intel.com> References: <20230106083826.5384-1-lei4.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=lei4.wang@intel.com; helo=mga05.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1672995023094100003 Content-Type: text/plain; charset="utf-8" Some feature words, e.g., feature words in AMX-related CPUID leaf 0x1D and 0x1E are not bit-wise but multiple bits represents one value. Handle this situation when the values specified are not the same as which are reported by KVM. The handling includes: - The responsibility of masking bits and giving warnings are delegated to the feature enabler. A framework is also provided to enable this. - To simplify the initialization, a default function is provided if the the function is not specified. The reason why delegating this responsibility rather than just marking them as zeros when they are not same is because different multi-bit features may have different logic, which is case by case, for example: 1. CPUID.0x14_0x1:EBX[15:0]. Even though it's multi-bits field, it's a bitmap and each bit represents a separate capability. 2. CPUID.0x14_0x1:EAX[2:0] represents the number of configurable Address Ranges. 3 bits as a whole to represent a integer value. It means the maximum capability of HW. If KVM reports M, then M to 0 is legal value to configure (because KVM can emulate each value correctly). 3. CPUID.0x1D_0x1:EAX[31:16] represents palette 1 bytes_per_tile. 16 bits as a whole represent an integer value. It's not like case 2 and SW needs to configure the same value as reported. Because it's not possible for SW to configure to a different value and KVM cannot emulate it. So marking them blindly as zeros is incorrect, and delegating this responsibility can let each multi-bit feature have its own way to mask bits. Signed-off-by: Lei Wang --- target/i386/cpu-internal.h | 2 ++ target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 66b3d66cb4..83c7b53926 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -30,6 +30,8 @@ typedef struct MultiBitFeatureInfo { uint64_t mask; unsigned high_bit_position; unsigned low_bit_position; + void (*mark_unavailable_multi_bit)(X86CPU *cpu, FeatureWord w, int ind= ex, + const char *verbose_prefix); } MultiBitFeatureInfo; =20 typedef struct FeatureWordInfo { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 88aa780566..e638a31d34 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4377,6 +4377,28 @@ static bool x86_cpu_have_filtered_features(X86CPU *c= pu) return false; } =20 +static void mark_unavailable_multi_bit_default(X86CPU *cpu, FeatureWord w, + int index, + const char *verbose_prefix) +{ + FeatureWordInfo *f =3D &feature_word_info[w]; + g_autofree char *feat_word_str =3D feature_word_description(f); + uint64_t host_feat =3D x86_cpu_get_supported_feature_word(w, false); + MultiBitFeatureInfo mf =3D f->multi_bit_features[index]; + + if ((cpu->env.features[w] & mf.mask) && + ((cpu->env.features[w] ^ host_feat) & mf.mask)) { + if (!cpu->force_features) { + cpu->env.features[w] &=3D ~mf.mask; + } + cpu->filtered_features[w] |=3D mf.mask; + if (verbose_prefix) + warn_report("%s: %s.%s [%u:%u]", verbose_prefix, feat_word_str, + mf.feat_name, mf.high_bit_position, + mf.low_bit_position); + } +} + static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t= mask, const char *verbose_prefix) { @@ -6442,6 +6464,20 @@ static void x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features =3D env->features[w]; uint64_t unavailable_features =3D requested_features & ~host_feat; + FeatureWordInfo f =3D feature_word_info[w]; + int i; + + for (i =3D 0; i < f.num_multi_bit_features; i++) { + MultiBitFeatureInfo mf =3D f.multi_bit_features[i]; + if (mf.mark_unavailable_multi_bit) { + mf.mark_unavailable_multi_bit(cpu, w, i, prefix); + } else { + mark_unavailable_multi_bit_default(cpu, w, i, prefix); + } + + unavailable_features &=3D ~mf.mask; + } + mark_unavailable_features(cpu, w, unavailable_features, prefix); } =20 --=20 2.34.1