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Thu, 05 Jan 2023 17:38:39 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 611B85000B9; Thu, 5 Jan 2023 09:38:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=SXDlWr7L9SI6/pmLxVQzrJvBUGU89aqju+OfANznKZ0=; b=LCGG5BwyB917I16v+nhFSaYIXEJ6xK5c5yoF34N/pMqh2mR40irs+vcEwmyw6StFrk+5 HP/aVIAznyEi+uPvTXH972TIi6wC5taqU3Nhs97G5EXx2gT/zlHs7NYELFMNS1PeuC76 h5SXcAsjDwbaabEDakqmQAovgwgNM7o0w0epo+5o6Wvon2K7JD5ojRKz76YGVG2o39Xd Ekkc/yQes3hjPDuV1FIWdjsYTrcMNtP2doBS6OBYaqwAuyxazKJH6FIgMc+FvEtQjhzq Q8+gsgmASKuS6yJKEfKEwRo51m3sTxEM7b6vyKiSlI+Eb2ex9QYVnSZs/l2nPoXWN7/1 AQ== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, peter.maydell@linaro.org, bcain@quicinc.com, quic_mathbern@quicinc.com, stefanha@redhat.com, Marco Liebel Subject: [PULL 6/7] Hexagon (target/hexagon) implement mutability mask for GPRs Date: Thu, 5 Jan 2023 09:38:25 -0800 Message-Id: <20230105173826.21444-7-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230105173826.21444-1-tsimpson@quicinc.com> References: <20230105173826.21444-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672940503591100003 From: Marco Liebel Some registers are defined to have immutable bits, this commit will implement that behavior. Signed-off-by: Marco Liebel Reviewed-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com> --- target/hexagon/genptr.c | 44 ++++++++- tests/tcg/hexagon/reg_mut.c | 152 ++++++++++++++++++++++++++++++ tests/tcg/hexagon/Makefile.target | 1 + 3 files changed, 195 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/hexagon/reg_mut.c diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 66a968c884..90db99024f 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -43,6 +43,33 @@ TCGv gen_read_preg(TCGv pred, uint8_t num) return pred; } =20 +#define IMMUTABLE (~0) + +static const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS] =3D { + [HEX_REG_USR] =3D 0xc13000c0, + [HEX_REG_PC] =3D IMMUTABLE, + [HEX_REG_GP] =3D 0x3f, + [HEX_REG_UPCYCLELO] =3D IMMUTABLE, + [HEX_REG_UPCYCLEHI] =3D IMMUTABLE, + [HEX_REG_UTIMERLO] =3D IMMUTABLE, + [HEX_REG_UTIMERHI] =3D IMMUTABLE, +}; + +static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val, + target_ulong reg_mask) +{ + if (reg_mask) { + TCGv tmp =3D tcg_temp_new(); + + /* new_val =3D (new_val & ~reg_mask) | (cur_val & reg_mask) */ + tcg_gen_andi_tl(new_val, new_val, ~reg_mask); + tcg_gen_andi_tl(tmp, cur_val, reg_mask); + tcg_gen_or_tl(new_val, new_val, tmp); + + tcg_temp_free(tmp); + } +} + static inline void gen_log_predicated_reg_write(int rnum, TCGv val, uint32_t slot) { @@ -69,6 +96,9 @@ static inline void gen_log_predicated_reg_write(int rnum,= TCGv val, =20 void gen_log_reg_write(int rnum, TCGv val) { + const target_ulong reg_mask =3D reg_immut_masks[rnum]; + + gen_masked_reg_write(val, hex_gpr[rnum], reg_mask); tcg_gen_mov_tl(hex_new_value[rnum], val); if (HEX_DEBUG) { /* Do this so HELPER(debug_commit_end) will know */ @@ -114,19 +144,29 @@ static void gen_log_predicated_reg_write_pair(int rnu= m, TCGv_i64 val, =20 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val) { + const target_ulong reg_mask_low =3D reg_immut_masks[rnum]; + const target_ulong reg_mask_high =3D reg_immut_masks[rnum + 1]; + TCGv val32 =3D tcg_temp_new(); + /* Low word */ - tcg_gen_extrl_i64_i32(hex_new_value[rnum], val); + tcg_gen_extrl_i64_i32(val32, val); + gen_masked_reg_write(val32, hex_gpr[rnum], reg_mask_low); + tcg_gen_mov_tl(hex_new_value[rnum], val32); if (HEX_DEBUG) { /* Do this so HELPER(debug_commit_end) will know */ tcg_gen_movi_tl(hex_reg_written[rnum], 1); } =20 /* High word */ - tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val); + tcg_gen_extrh_i64_i32(val32, val); + gen_masked_reg_write(val32, hex_gpr[rnum + 1], reg_mask_high); + tcg_gen_mov_tl(hex_new_value[rnum + 1], val32); if (HEX_DEBUG) { /* Do this so HELPER(debug_commit_end) will know */ tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1); } + + tcg_temp_free(val32); } =20 void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) diff --git a/tests/tcg/hexagon/reg_mut.c b/tests/tcg/hexagon/reg_mut.c new file mode 100644 index 0000000000..910e663ace --- /dev/null +++ b/tests/tcg/hexagon/reg_mut.c @@ -0,0 +1,152 @@ + +/* + * Copyright(c) 2022 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include + +static int err; + +#define check(N, EXPECT) \ + do { \ + uint64_t value =3D N; \ + uint64_t expect =3D EXPECT; \ + if (value !=3D EXPECT) { \ + printf("ERROR: \"%s\" 0x%04llx !=3D 0x%04llx at %s:%d\n", #N, = value, \ + expect, __FILE__, __LINE__); \ + err++; \ + } \ + } while (0) + +#define check_ne(N, EXPECT) \ + do { \ + uint64_t value =3D N; \ + uint64_t expect =3D EXPECT; \ + if (value =3D=3D EXPECT) { \ + printf("ERROR: \"%s\" 0x%04llx =3D=3D 0x%04llx at %s:%d\n", #N= , value, \ + expect, __FILE__, __LINE__); \ + err++; \ + } \ + } while (0) + +#define WRITE_REG_NOCLOBBER(output, reg_name, input) \ + asm volatile(reg_name " =3D %1\n\t" \ + "%0 =3D " reg_name "\n\t" \ + : "=3Dr"(output) \ + : "r"(input) \ + : ); + +#define WRITE_REG_ENCODED(output, reg_name, input, encoding) \ + asm volatile("r0 =3D %1\n\t" \ + encoding "\n\t" \ + "%0 =3D " reg_name "\n\t" \ + : "=3Dr"(output) \ + : "r"(input) \ + : "r0"); + +#define WRITE_REG_PAIR_ENCODED(output, reg_name, input, encoding) \ + asm volatile("r1:0 =3D %1\n\t" \ + encoding "\n\t" \ + "%0 =3D " reg_name "\n\t" \ + : "=3Dr"(output) \ + : "r"(input) \ + : "r1:0"); + +/* + * Instruction word: { pc =3D r0 } + * + * This instruction is barred by the assembler. + * + * 3 2 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opc[A2_tfrrcr] | Src[R0] |P P| | C9/PC | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +#define PC_EQ_R0 ".word 0x6220c009" +#define C9_8_EQ_R1_0 ".word 0x6320c008" + +static inline void write_control_registers(void) +{ + uint32_t result =3D 0; + + WRITE_REG_NOCLOBBER(result, "usr", 0xffffffff); + check(result, 0x3ecfff3f); + + WRITE_REG_NOCLOBBER(result, "gp", 0xffffffff); + check(result, 0xffffffc0); + + WRITE_REG_NOCLOBBER(result, "upcyclelo", 0xffffffff); + check(result, 0x00000000); + + WRITE_REG_NOCLOBBER(result, "upcyclehi", 0xffffffff); + check(result, 0x00000000); + + WRITE_REG_NOCLOBBER(result, "utimerlo", 0xffffffff); + check(result, 0x00000000); + + WRITE_REG_NOCLOBBER(result, "utimerhi", 0xffffffff); + check(result, 0x00000000); + + /* + * PC is special. Setting it to these values + * should cause a catastrophic failure. + */ + WRITE_REG_ENCODED(result, "pc", 0x00000000, PC_EQ_R0); + check_ne(result, 0x00000000); + + WRITE_REG_ENCODED(result, "pc", 0x00000001, PC_EQ_R0); + check_ne(result, 0x00000001); + + WRITE_REG_ENCODED(result, "pc", 0xffffffff, PC_EQ_R0); + check_ne(result, 0xffffffff); +} + +static inline void write_control_register_pairs(void) +{ + uint64_t result =3D 0; + + WRITE_REG_NOCLOBBER(result, "c11:10", 0xffffffffffffffff); + check(result, 0xffffffc0ffffffff); + + WRITE_REG_NOCLOBBER(result, "c15:14", 0xffffffffffffffff); + check(result, 0x0000000000000000); + + WRITE_REG_NOCLOBBER(result, "c31:30", 0xffffffffffffffff); + check(result, 0x0000000000000000); + + WRITE_REG_PAIR_ENCODED(result, "c9:8", (uint64_t) 0x0000000000000000, + C9_8_EQ_R1_0); + check_ne(result, 0x000000000000000); + + WRITE_REG_PAIR_ENCODED(result, "c9:8", 0x0000000100000000, C9_8_EQ_R1_= 0); + check_ne(result, 0x0000000100000000); + + WRITE_REG_PAIR_ENCODED(result, "c9:8", 0xffffffffffffffff, C9_8_EQ_R1_= 0); + check_ne(result, 0xffffffffffffffff); +} + +int main() +{ + err =3D 0; + + write_control_registers(); + write_control_register_pairs(); + + puts(err ? "FAIL" : "PASS"); + return err; +} diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index f1378d86a9..18e6a5969e 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -44,6 +44,7 @@ HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff HEX_TESTS +=3D overflow HEX_TESTS +=3D signal_context +HEX_TESTS +=3D reg_mut =20 HEX_TESTS +=3D test_abs HEX_TESTS +=3D test_bitcnt --=20 2.17.1