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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/34] target/arm: Add PMSAv8r functionality
Date: Thu, 5 Jan 2023 16:43:50 +0000
Message-Id: <20230105164417.3994639-8-peter.maydell@linaro.org>
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From: Tobias R=C3=B6hmel <tobias.roehmel@rwth-aachen.de>
Add PMSAv8r translation.
Signed-off-by: Tobias R=C3=B6hmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++---------
1 file changed, 104 insertions(+), 22 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 1c7c9cb5e37..4bda0590c7c 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1758,9 +1758,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu=
, ARMMMUIdx mmu_idx,
=20
if (arm_feature(env, ARM_FEATURE_M)) {
return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MA=
SK;
- } else {
- return regime_sctlr(env, mmu_idx) & SCTLR_BR;
}
+
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
+ return false;
+ }
+
+ return regime_sctlr(env, mmu_idx) & SCTLR_BR;
}
=20
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
@@ -1952,6 +1956,26 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u=
int32_t address,
return !(result->f.prot & (1 << access_type));
}
=20
+static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
+ uint32_t secure)
+{
+ if (regime_el(env, mmu_idx) =3D=3D 2) {
+ return env->pmsav8.hprbar;
+ } else {
+ return env->pmsav8.rbar[secure];
+ }
+}
+
+static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
+ uint32_t secure)
+{
+ if (regime_el(env, mmu_idx) =3D=3D 2) {
+ return env->pmsav8.hprlar;
+ } else {
+ return env->pmsav8.rlar[secure];
+ }
+}
+
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool secure, GetPhysAddrResult *result,
@@ -1974,6 +1998,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad=
dress,
bool hit =3D false;
uint32_t addr_page_base =3D address & TARGET_PAGE_MASK;
uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1);
+ int region_counter;
+
+ if (regime_el(env, mmu_idx) =3D=3D 2) {
+ region_counter =3D cpu->pmsav8r_hdregion;
+ } else {
+ region_counter =3D cpu->pmsav7_dregion;
+ }
=20
result->f.lg_page_size =3D TARGET_PAGE_BITS;
result->f.phys_addr =3D address;
@@ -1982,6 +2013,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad=
dress,
*mregion =3D -1;
}
=20
+ if (mmu_idx =3D=3D ARMMMUIdx_Stage2) {
+ fi->stage2 =3D true;
+ }
+
/*
* Unlike the ARM ARM pseudocode, we don't need to check whether this
* was an exception vector read from the vector table (which is always
@@ -1998,17 +2033,26 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a=
ddress,
hit =3D true;
}
=20
- for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) {
+ uint32_t bitmask;
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ bitmask =3D 0x1f;
+ } else {
+ bitmask =3D 0x3f;
+ fi->level =3D 0;
+ }
+
+ for (n =3D region_counter - 1; n >=3D 0; n--) {
/* region search */
/*
- * Note that the base address is bits [31:5] from the register
- * with bits [4:0] all zeroes, but the limit address is bits
- * [31:5] from the register with bits [4:0] all ones.
+ * Note that the base address is bits [31:x] from the register
+ * with bits [x-1:0] all zeroes, but the limit address is bits
+ * [31:x] from the register with bits [x:0] all ones. Where x =
is
+ * 5 for Cortex-M and 6 for Cortex-R
*/
- uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f;
- uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f;
+ uint32_t base =3D regime_rbar(env, mmu_idx, secure)[n] & ~bitm=
ask;
+ uint32_t limit =3D regime_rlar(env, mmu_idx, secure)[n] | bitm=
ask;
=20
- if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
+ if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
/* Region disabled */
continue;
}
@@ -2042,7 +2086,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add=
ress,
* PMSAv7 where highest-numbered-region wins)
*/
fi->type =3D ARMFault_Permission;
- fi->level =3D 1;
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ fi->level =3D 1;
+ }
return true;
}
=20
@@ -2052,8 +2098,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad=
dress,
}
=20
if (!hit) {
- /* background fault */
- fi->type =3D ARMFault_Background;
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ fi->type =3D ARMFault_Background;
+ } else {
+ fi->type =3D ARMFault_Permission;
+ }
return true;
}
=20
@@ -2061,12 +2110,14 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a=
ddress,
/* hit using the background region */
get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro=
t);
} else {
- uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1=
, 2);
- uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0=
, 1);
+ uint32_t matched_rbar =3D regime_rbar(env, mmu_idx, secure)[matchr=
egion];
+ uint32_t matched_rlar =3D regime_rlar(env, mmu_idx, secure)[matchr=
egion];
+ uint32_t ap =3D extract32(matched_rbar, 1, 2);
+ uint32_t xn =3D extract32(matched_rbar, 0, 1);
bool pxn =3D false;
=20
if (arm_feature(env, ARM_FEATURE_V8_1M)) {
- pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
+ pxn =3D extract32(matched_rlar, 4, 1);
}
=20
if (m_is_system_region(env, address)) {
@@ -2074,21 +2125,46 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a=
ddress,
xn =3D 1;
}
=20
- result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap);
+ if (regime_el(env, mmu_idx) =3D=3D 2) {
+ result->f.prot =3D simple_ap_to_rw_prot_is_user(ap,
+ mmu_idx !=3D ARMMMUIdx_E2);
+ } else {
+ result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap);
+ }
+
+ if (!arm_feature(env, ARM_FEATURE_M)) {
+ uint8_t attrindx =3D extract32(matched_rlar, 1, 3);
+ uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)];
+ uint8_t sh =3D extract32(matched_rlar, 3, 2);
+
+ if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
+ result->f.prot & PAGE_WRITE && mmu_idx !=3D ARMMMUIdx_Stag=
e2) {
+ xn =3D 0x1;
+ }
+
+ if ((regime_el(env, mmu_idx) =3D=3D 1) &&
+ regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap =3D=3D 0x1) {
+ pxn =3D 0x1;
+ }
+
+ result->cacheattrs.is_s2_format =3D false;
+ result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8);
+ result->cacheattrs.shareability =3D sh;
+ }
+
if (result->f.prot && !xn && !(pxn && !is_user)) {
result->f.prot |=3D PAGE_EXEC;
}
- /*
- * We don't need to look the attribute up in the MAIR0/MAIR1
- * registers because that only tells us about cacheability.
- */
+
if (mregion) {
*mregion =3D matchregion;
}
}
=20
fi->type =3D ARMFault_Permission;
- fi->level =3D 1;
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ fi->level =3D 1;
+ }
return !(result->f.prot & (1 << access_type));
}
=20
@@ -2649,7 +2725,13 @@ static bool get_phys_addr_twostage(CPUARMState *env,=
S1Translate *ptw,
cacheattrs1 =3D result->cacheattrs;
memset(result, 0, sizeof(*result));
=20
- ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result,=
fi);
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
+ ret =3D get_phys_addr_pmsav8(env, ipa, access_type,
+ ptw->in_mmu_idx, is_secure, result, fi);
+ } else {
+ ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type,
+ is_el0, result, fi);
+ }
fi->s2addr =3D ipa;
=20
/* Combine the S1 and S2 perms. */
--=20
2.25.1