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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939695965100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 + target/arm/cpu.c | 28 +++- target/arm/helper.c | 302 +++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 28 ++++ 4 files changed, 360 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b4bd20f9d0..bf2bce046d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -309,6 +309,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ @@ -745,8 +746,11 @@ typedef struct CPUArchState { */ uint32_t *rbar[M_REG_NUM_BANKS]; uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t *hprbar; + uint32_t *hprlar; uint32_t mair0[M_REG_NUM_BANKS]; uint32_t mair1[M_REG_NUM_BANKS]; + uint32_t hprselr; } pmsav8; =20 /* v8M SAU */ @@ -906,6 +910,8 @@ struct ArchCPU { bool has_mpu; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; + /* PMSAv8 MPU number of supported hyp regions */ + uint32_t pmsav8r_hdregion; /* v8M SAU number of supported regions */ uint32_t sau_sregion; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c107cbd7574..f99f749b295 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -491,6 +491,14 @@ static void arm_cpu_reset_hold(Object *obj) sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } } + + if (cpu->pmsav8r_hdregion > 0) { + memset(env->pmsav8.hprbar, 0, + sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); + memset(env->pmsav8.hprlar, 0, + sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); + } + env->pmsav7.rnr[M_REG_NS] =3D 0; env->pmsav7.rnr[M_REG_S] =3D 0; env->pmsav8.mair0[M_REG_NS] =3D 0; @@ -2002,11 +2010,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) /* MPU can be configured out of a PMSA CPU either by setting has-mpu * to false or by setting pmsav7-dregion to 0. */ - if (!cpu->has_mpu) { - cpu->pmsav7_dregion =3D 0; - } - if (cpu->pmsav7_dregion =3D=3D 0) { + if (!cpu->has_mpu || cpu->pmsav7_dregion =3D=3D 0) { cpu->has_mpu =3D false; + cpu->pmsav7_dregion =3D 0; + cpu->pmsav8r_hdregion =3D 0; } =20 if (arm_feature(env, ARM_FEATURE_PMSA) && @@ -2033,6 +2040,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->pmsav7.dracr =3D g_new0(uint32_t, nr); } } + + if (cpu->pmsav8r_hdregion > 0xff) { + error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, + cpu->pmsav8r_hdregion); + return; + } + + if (cpu->pmsav8r_hdregion) { + env->pmsav8.hprbar =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + env->pmsav8.hprlar =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + } } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index d8066fe97d3..b13f6ff328c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3682,6 +3682,222 @@ static void pmsav7_rgnr_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* + * Ignore writes that would select not implemented region. + * This is architecturally UNPREDICTABLE. + */ + if (value >=3D cpu->pmsav7_dregion) { + return; + } + + env->pmsav7.rnr[M_REG_NS] =3D value; +} + +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprbar[env->pmsav8.hprselr] =3D value; +} + +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprbar[env->pmsav8.hprselr]; +} + +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprlar[env->pmsav8.hprselr] =3D value; +} + +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprlar[env->pmsav8.hprselr]; +} + +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t n; + uint32_t bit; + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes to unimplemented regions */ + int rmax =3D MIN(cpu->pmsav8r_hdregion, 32); + value &=3D MAKE_64BIT_MASK(0, rmax); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < rmax; ++n) { + bit =3D extract32(value, n, 1); + env->pmsav8.hprlar[n] =3D deposit32( + env->pmsav8.hprlar[n], 0, 1, bit); + } +} + +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t n; + uint32_t result =3D 0x0; + ARMCPU *cpu =3D env_archcpu(env); + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { + if (env->pmsav8.hprlar[n] & 0x1) { + result |=3D (0x1 << n); + } + } + return result; +} + +static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* + * Ignore writes that would select not implemented region. + * This is architecturally UNPREDICTABLE. + */ + if (value >=3D cpu->pmsav8r_hdregion) { + return; + } + + env->pmsav8.hprselr =3D value; +} + +static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (extract32(ri->opc0, 0, 1) << 4) | + (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, = 2, 1); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + if (ri->opc1 & 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.hprlar[index] =3D value; + } else { + env->pmsav8.hprbar[index] =3D value; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.rlar[M_REG_NS][index] =3D value; + } else { + env->pmsav8.rbar[M_REG_NS][index] =3D value; + } + } +} + +static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (extract32(ri->opc0, 0, 1) << 4) | + (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, = 2, 1); + + if (ri->opc1 & 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.hprlar[index]; + } else { + return env->pmsav8.hprbar[index]; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.rlar[M_REG_NS][index]; + } else { + return env->pmsav8.rbar[M_REG_NS][index]; + } + } +} + +static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { + { .name =3D "PRBAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tvm_trvm, + .readfn =3D prbar_read, .writefn =3D prbar_write }, + { .name =3D "PRLAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tvm_trvm, + .readfn =3D prlar_read, .writefn =3D prlar_write }, + { .name =3D "PRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D prselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) }, + { .name =3D "HPRBAR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D hprbar_read, .writefn =3D hprbar_write }, + { .name =3D "HPRLAR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D hprlar_read, .writefn =3D hprlar_write }, + { .name =3D "HPRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, + .writefn =3D hprselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprselr) }, + { .name =3D "HPRENR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D hprenr_read, .writefn =3D hprenr_write }, +}; + static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { /* Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do @@ -8207,6 +8423,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; + /* HMPUIR is specific to PMSA V8 */ + ARMCPRegInfo id_hmpuir_reginfo =3D { + .name =3D "HMPUIR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav8r_hdregion + }; static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, @@ -8249,6 +8472,74 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + uint32_t i =3D 0; + char *tmp_string; + + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); + define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { + uint8_t crm =3D 0b1000 | extract32(i, 1, 3); + uint8_t opc1 =3D extract32(i, 4, 1); + uint8_t opc2 =3D extract32(i, 0, 1) << 2; + + tmp_string =3D g_strdup_printf("PRBAR%u", i); + ARMCPRegInfo tmp_prbarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS | ARM_CP_= NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); + g_free(tmp_string); + + opc2 =3D extract32(i, 0, 1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("PRLAR%u", i); + ARMCPRegInfo tmp_prlarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS | ARM_CP_= NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); + g_free(tmp_string); + } + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { + uint8_t crm =3D 0b1000 | extract32(i, 1, 3); + uint8_t opc1 =3D 0b100 | extract32(i, 4, 1); + uint8_t opc2 =3D extract32(i, 0, 1) << 2; + + tmp_string =3D g_strdup_printf("HPRBAR%u", i); + ARMCPRegInfo tmp_hprbarn_reginfo =3D { + .name =3D tmp_string, + .type =3D ARM_CP_NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); + g_free(tmp_string); + + opc2 =3D extract32(i, 0, 1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("HPRLAR%u", i); + ARMCPRegInfo tmp_hprlarn_reginfo =3D { + .name =3D tmp_string, + .type =3D ARM_CP_NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); + g_free(tmp_string); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } @@ -8370,6 +8661,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; } define_one_arm_cp_reg(cpu, &sctlr); + + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + ARMCPRegInfo vsctlr =3D { + .name =3D "VSCTLR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D= 0, + .access =3D PL2_RW, .resetvalue =3D 0x0, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vsctlr), + }; + define_one_arm_cp_reg(cpu, &vsctlr); + } } =20 if (cpu_isar_feature(aa64_lor, cpu)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433d..5f261526525 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -487,6 +487,30 @@ static bool pmsav8_needed(void *opaque) arm_feature(env, ARM_FEATURE_V8); } =20 +static bool pmsav8r_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8) && + !arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav8r =3D { + .name =3D "cpu/pmsav8/pmsav8r", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav8r_needed, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_pmsav8 =3D { .name =3D "cpu/pmsav8", .version_id =3D 1, @@ -500,6 +524,10 @@ static const VMStateDescription vmstate_pmsav8 =3D { VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_pmsav8r, + NULL } }; =20 --=20 2.25.1