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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/34] target/arm: Make RVBAR available for all ARMv8 CPUs
Date: Thu, 5 Jan 2023 16:43:46 +0000
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From: Tobias R=C3=B6hmel <tobias.roehmel@rwth-aachen.de>
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias R=C3=B6hmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 6 +++++-
target/arm/helper.c | 21 ++++++++++++++-------
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2fa022f62ba..c107cbd7574 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -309,6 +309,10 @@ static void arm_cpu_reset_hold(Object *obj)
env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1,
CPACR, CP11, 3);
#endif
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ env->cp15.rvbar =3D cpu->rvbar_prop;
+ env->regs[15] =3D cpu->rvbar_prop;
+ }
}
=20
#if defined(CONFIG_USER_ONLY)
@@ -1345,7 +1349,7 @@ void arm_cpu_post_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_proper=
ty);
}
=20
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
object_property_add_uint64_ptr(obj, "rvbar",
&cpu->rvbar_prop,
OBJ_PROP_FLAG_READWRITE);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 090daf93c71..d8066fe97d3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7896,7 +7896,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (!arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2)) {
ARMCPRegInfo rvbar =3D {
- .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_BOTH,
.opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =
=3D 1,
.access =3D PL1_R,
.fieldoffset =3D offsetof(CPUARMState, cp15.rvbar),
@@ -7987,13 +7987,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3)) {
- ARMCPRegInfo rvbar =3D {
- .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =
=3D 1,
- .access =3D PL2_R,
- .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar),
+ ARMCPRegInfo rvbar[] =3D {
+ {
+ .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .op=
c2 =3D 1,
+ .access =3D PL2_R,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar),
+ },
+ { .name =3D "RVBAR", .type =3D ARM_CP_ALIAS,
+ .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc=
2 =3D 1,
+ .access =3D PL2_R,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar),
+ },
};
- define_one_arm_cp_reg(cpu, &rvbar);
+ define_arm_cp_regs(cpu, rvbar);
}
}
=20
--=20
2.25.1