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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/34] target/arm: Don't add all MIDR aliases for cores that
implement PMSA
Date: Thu, 5 Jan 2023 16:43:45 +0000
Message-Id: <20230105164417.3994639-3-peter.maydell@linaro.org>
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From: Tobias R=C3=B6hmel <tobias.roehmel@rwth-aachen.de>
Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=3D4. So we only
add that alias if we are not realizing a core that
implements PMSA.
Signed-off-by: Tobias R=C3=B6hmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bac2ea62c44..090daf93c71 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8153,10 +8153,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D =
cpu->midr,
.fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid),
.readfn =3D midr_read },
- /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases=
of MIDR */
- { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST,
- .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4,
- .access =3D PL1_R, .resetvalue =3D cpu->midr },
+ /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o=
f MIDR */
{ .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST,
.cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7,
.access =3D PL1_R, .resetvalue =3D cpu->midr },
@@ -8166,6 +8163,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn =3D access_aa64_tid1,
.type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr },
};
+ ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D {
+ .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST,
+ .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4,
+ .access =3D PL1_R, .resetvalue =3D cpu->midr
+ };
ARMCPRegInfo id_cp_reginfo[] =3D {
/* These are common to v8 and pre-v8 */
{ .name =3D "CTR",
@@ -8231,6 +8233,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
+ if (!arm_feature(env, ARM_FEATURE_PMSA)) {
+ define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
+ }
} else {
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
}
--=20
2.25.1