From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672939798; cv=none; d=zohomail.com; s=zohoarc; b=mHhDsoJcmAErfVIXwKR8U8kUK6y0hMcrHH9NG/DvFmwfIYf9+NBBzW/BSRbPmZ302aQGwJxYCemASQYje+w4EYlHmKHF5ZnucBQjtMb6NcE3AGz8TnzH792JAc8bnUuis9PL/XkEj3G56Cszu8ilPCR5XmtSnQNyQEgbb+VrRwQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672939798; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F/5EJBYFSRrAmo1vD4tU1WXQrdeBd0ZRx/qGyNKF6P8=; b=WPQRHFF94NHO+8csMfaZglmAoyWCWFWqZbP8MeUVM7yArGN4f00fM23ziMhmuXlR6tvU2imHb63WpTc1NekKCBOrBiPCyDTz4EPbv/jq9RL0zVKYRnj+GLebIJ+Pf8adXlI+Wkq8963Kou9GIe5SIDznSVJSvNBmbWuPZ9eyEGU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167293979890958.69469689151765; Thu, 5 Jan 2023 09:29:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTLt-0000KD-Kr; Thu, 05 Jan 2023 11:44:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLr-0000Bh-Md for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:23 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLp-0007Lb-Jk for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:23 -0500 Received: by mail-wm1-x334.google.com with SMTP id fm16-20020a05600c0c1000b003d96fb976efso1734007wmb.3 for ; Thu, 05 Jan 2023 08:44:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=F/5EJBYFSRrAmo1vD4tU1WXQrdeBd0ZRx/qGyNKF6P8=; b=qDZMeaYiYNDzYr3EONnabtzevfAdpv6S+k4rBuXC41YwVlTnkJTANjXikb3M3L+wOI WFaUyZ6hxX06bnzEYmld2oRyAmOOx53bqoKg9WL1GVAELNACUr4AGcp0Qau8ox6Z6o4A Cn/xSZ0l8PxgSoFuWXufjW+p24VoJ0rQNsd4X4dknoou8vBSck7l8sDpcjpC08G2ojpR MW7z+TmSK6sqP3e3/aCyuc188Y73X1Wd/MqcOxy0nlLJQC717QVTlrvUi+2pnE96FGhS pLAokyY+lgWjEUyPcn4VcGsJhx15pY97JmTSN3amPEbGRh1BEaMXRFRdZBY/iJ8KeHSK oocw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F/5EJBYFSRrAmo1vD4tU1WXQrdeBd0ZRx/qGyNKF6P8=; b=2CQxQ7keji9jyV1PTFHy5oCUEptIlwQqRgZaooE+FjOj2BFMMGt70aiLxp71F+/5Rb EERV1XA/IJDIPFYPQM2i1x8nJ9JnvIC78cJXlFsf9xLD0j7vw7dyyPPQyJ2lq1prek+f syWtRE64ZH1hbJGtSGh/ULKlCedqlXXDZDvjloeie3NCrUGfTTVJtyKtlDwBOEwz3X8T lg4U2asn6jFaCuZzeuiLytST04oa/mlym37ibUnHh+rG9ZUGN77XeXCyhgYA1UZdw3rr 4YzC4X55o0xDWD90Rsa+YSGu2UOmJq/tmwrQHYwdK5jwc92XXXYo4tKGR+0UcBbPS1SU iR5Q== X-Gm-Message-State: AFqh2krvTAG+z4Jk+eI9P/LkD5YtUic8bUVxScpJH9TEzs+SPviTlJ+f 4buPQM3XqUHD+CyQ9/OJVoRNBUmFwDviWipp X-Google-Smtp-Source: AMrXdXtWYdCSZp6LalDGiA0vcIb0PFFxNm9Tw6spVikQJKUCn+cXOpfs2RLilYdDk1X+UgkQZzeLZg== X-Received: by 2002:a05:600c:1e24:b0:3d3:5075:7526 with SMTP id ay36-20020a05600c1e2400b003d350757526mr38135203wmb.31.1672937060194; Thu, 05 Jan 2023 08:44:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/34] target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it Date: Thu, 5 Jan 2023 16:43:44 +0000 Message-Id: <20230105164417.3994639-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939800608100003 Content-Type: text/plain; charset="utf-8" In get_phys_addr_twostage() we set the lg_page_size of the result to the maximum of the stage 1 and stage 2 page sizes. This works for the case where we do want to create a TLB entry, because we know the common TLB code only creates entries of the TARGET_PAGE_SIZE and asking for a size larger than that only means that invalidations invalidate the whole larger area. However, if lg_page_size is smaller than TARGET_PAGE_SIZE this effectively means "don't create a TLB entry"; in this case if either S1 or S2 said "this covers less than a page and can't go in a TLB" then the final result also should be marked that way. Set the resulting page size to 0 if either stage asked for a less-than-a-page entry, and expand the comment to explain what's going on. This has no effect for VMSA because currently the VMSA lookup always returns results that cover at least TARGET_PAGE_SIZE; however when we add v8R support it will reuse this code path, and for v8R the S1 and S2 results can be smaller than TARGET_PAGE_SIZE. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20221212142708.610090-1-peter.maydell@linaro.org --- target/arm/ptw.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f812734bfb2..2e7826dc29b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2655,10 +2655,20 @@ static bool get_phys_addr_twostage(CPUARMState *env= , S1Translate *ptw, } =20 /* - * Use the maximum of the S1 & S2 page size, so that invalidation - * of pages > TARGET_PAGE_SIZE works correctly. + * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE, + * this means "don't put this in the TLB"; in this case, return a + * result with lg_page_size =3D=3D 0 to achieve that. Otherwise, + * use the maximum of the S1 & S2 page size, so that invalidation + * of pages > TARGET_PAGE_SIZE works correctly. (This works even though + * we know the combined result permissions etc only cover the minimum + * of the S1 and S2 page size, because we know that the common TLB code + * never actually creates TLB entries bigger than TARGET_PAGE_SIZE, + * and passing a larger page size value only affects invalidations.) */ - if (result->f.lg_page_size < s1_lgpgsz) { + if (result->f.lg_page_size < TARGET_PAGE_BITS || + s1_lgpgsz < TARGET_PAGE_BITS) { + result->f.lg_page_size =3D 0; + } else if (result->f.lg_page_size < s1_lgpgsz) { result->f.lg_page_size =3D s1_lgpgsz; } =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937149; cv=none; d=zohomail.com; s=zohoarc; b=OvCrO/qvheGb2VvcmtC8d5qJCJeJFShk1N0qn+Ryh2CLhciTW6PeFxhSM6ZvrBwv/B5IOj8+aITZj7+eLVptuLiw63yvNFOUbp+YAi8iu6J6QsRMSXk+cpgGbBG6oV2SmPU0aCrUp4T0z/BYjRqs/wHquIxWj1HhxtcbLBTLSwA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937149; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yuo7qK1mL55V9kttGcjYaiTtFdumRPFENl39UXW9mMo=; b=McNvWFgD1ZNASlP8f4U14fDktXSTdBTbUf93rIkIGgT78mD31ebQuY0+gMF4QG1JD0RKwNmOPLnzxruDVrLNPod/mC6NG8F3Zy8viGsufGhDVetVj6ib069L8KJnCCts7llli7NkskezHnvWAqASK81kUBQktdn/1PJ5XDtyELo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167293714936836.535518066045256; Thu, 5 Jan 2023 08:45:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTLu-0000LZ-5R; Thu, 05 Jan 2023 11:44:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLr-0000Bj-NU for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:23 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLp-00072G-Kc for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:23 -0500 Received: by mail-wm1-x32c.google.com with SMTP id ja17so28449479wmb.3 for ; Thu, 05 Jan 2023 08:44:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Yuo7qK1mL55V9kttGcjYaiTtFdumRPFENl39UXW9mMo=; b=CURm2aHYSLjNVaFu4jFPVh5GEmDEb99ahposk6Q2BYXcJ4uhzq4km8rjdJ2UWhqZde PvoqVRWcYp2vC+xfjc7PCqxlBCop6jA4GXII9UuneMGi6+Nvhj1aMCobAbDZu8vJPoR4 a9PTjEs1Zj8Bny5b8KQjo9QLd1g6y6JvV455u5XBIRThhWK/B+xYu1SrkSBmOtc708za F77v01D3DYvQyCq+ZJ8NNqgoYFMMf/cFqbkSe25E7KshFVCCQA+tKXS7bZZ/Z7mWc1S3 DTdiQ0DzQJun/T8QD3xfi7copPVSYe4jWFnl4BuGPsTKcFfV6FnzamLBFR3haP3gxPDj mP0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yuo7qK1mL55V9kttGcjYaiTtFdumRPFENl39UXW9mMo=; b=ixXsX24aGZ6EEAvpjnjzIQk31tCzNI0EKNxNZGNmzpvNCmG9n0yfq/QwQCMP2XNcp1 CZE03nPKDpuMJ3dU26Qm6PcB1YM2ooiHGA69BAn2m8Zsy6Fu7MyZbaN9s90AyuyLrAhL i+tYGyIFuBtsADuIkROE40BL9PMGNaW8QJwU6NsarslorZXD3szNz1bKk9O+PnRNATTp tQc2pByQB4/Bq/cEazLQn3K4eK+1wixLOcWWPY02bxlgvaz6nOVQNARx2bukODXqhWjO rcTeGmAuK2U4uTboYqBRltPSXrYhJ5Kw7iCSyVHkR9DGCF+N4RmSNNPjAe11Y3p31bN3 +DBA== X-Gm-Message-State: AFqh2kpO1SIFaF+KKEq2maZzL6qbVdiHPdosYChdyQHqa1SA+Pc9wNrx bFisS2x1O9T46UdJyWvpY3trHx/1jXj4q+GS X-Google-Smtp-Source: AMrXdXuX5D/gT7xQWofRKF/KgzyTd3w99Z9jZTGasX8Tsg94+tBIrEfE9D9V21MPubryb08IV/ijYw== X-Received: by 2002:a05:600c:4854:b0:3d3:5a4a:90ff with SMTP id j20-20020a05600c485400b003d35a4a90ffmr39115253wmo.23.1672937060960; Thu, 05 Jan 2023 08:44:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/34] target/arm: Don't add all MIDR aliases for cores that implement PMSA Date: Thu, 5 Jan 2023 16:43:45 +0000 Message-Id: <20230105164417.3994639-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937155791100001 From: Tobias R=C3=B6hmel Cores with PMSA have the MPUIR register which has the same encoding as the MIDR alias with opc2=3D4. So we only add that alias if we are not realizing a core that implements PMSA. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bac2ea62c44..090daf93c71 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8153,10 +8153,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), .readfn =3D midr_read }, - /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, + /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 7 : AArch32 aliases o= f MIDR */ { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, .access =3D PL1_R, .resetvalue =3D cpu->midr }, @@ -8166,6 +8163,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, }; + ARMCPRegInfo id_v8_midr_alias_cp_reginfo =3D { + .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr + }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ { .name =3D "CTR", @@ -8231,6 +8233,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_PMSA)) { + define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo); + } } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); } --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937643; cv=none; d=zohomail.com; s=zohoarc; b=IiOOzlL2JeEBIBlrAusrITfZoJbAKTImMYiQLOdoov/xov1Qgg1QUtc9t3XCznYceWcxypsgHaDBT0zDRztZvMHaQq6QLT66fg7z/vHyl8oNQTkHPFVbb9KR4PgneILJ26o8eVhIxdMUseRdUI+ftylFOfaMBT4qnW8sYKQOOgo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937643; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ucC6r0jcHK+UNQ8eQHcmxpwSVgcMH/k1pFOZLGUGlEY=; b=jvO8JWf7rKp6cVzfC968pEKA9lQ9YuaXaEngDMS3jed1dc1WwnPKiPCcijt4w9DUXRR8LBtlbhQWJOQNLKp/tCGBSlMXOh0P/rwgiNvo45RUj/rmadTQEMtRNXCTwFzUmiOSdYYaDjD8sdGNE0JFuA9zYZ/TIF+VWuvGK/o7LM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937643522873.1700773492391; Thu, 5 Jan 2023 08:54:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTLv-0000Qa-EH; Thu, 05 Jan 2023 11:44:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLt-0000Jl-6v for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:25 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLr-0007Lt-Di for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:24 -0500 Received: by mail-wm1-x334.google.com with SMTP id g10so14660734wmo.1 for ; Thu, 05 Jan 2023 08:44:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ucC6r0jcHK+UNQ8eQHcmxpwSVgcMH/k1pFOZLGUGlEY=; b=E8DRv8Nu4ixugWfK7FytBuxghTiwZxfIA8v2FkhXE8xQW7boVkVkF+ANXVyqrfEvS5 ubCGchzYN2aFeHm2tR8DMack6HoC4RTfYINzGn5FJbUIlsOgXpes59SFRZv8zLMu7r7M U/qGrPyF2LhtYeQpK0x8yey/snnryI4Zs+TGyyxvlV6OgaD3PHyO74AorODaxr+cwdZO 9pldvRk+3pujN/t0Bdaz0Uqx54ussUqGnGUAbaVhSJdWFcSd6oND7W6W6TX8AAUbXTra dqmmZd6URkVBFjRQW7ut8d64eXaLcogbiDEWfqeC1K7NM0O7rPzqfO7B8sSNHXNZN0jA GsFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ucC6r0jcHK+UNQ8eQHcmxpwSVgcMH/k1pFOZLGUGlEY=; b=k6IFLW31DlujVtfe5jGPfK14UTSYonEHLMIix3qn1i95baCleqeskSwxvc9MXGqo+v Ai3iGlez4gmZT3OTwRXg/R1kYBQsyCr3kyJLtoLl+EYC/bklUvfEGJFY0GJOuKmQOOAF +mV/SVKmJZBR87Cv7VPPV1qk1hKtN9EQB0DnClDIm106MPFEjUO24v8uyQJ0C0s1V5sm IjMx8JB9Akn733dhF3FM/978fleK9vrqJ71tDNKGh4dX0R0NwULbtNZoWD33CqsMm7Ao fjg2h/n3+6+jVhZ8gIOmx6FFgpG3zndJlnfnf2DAZqkTue1mfjjLXnbwtd2whpmjE+SX FMtA== X-Gm-Message-State: AFqh2kp+qdvxEA8NMNqYA1yPlOgzfgLjUL1JaSvxVyl5rob8VMlvPrEm SvJElAPs49Z5cm8LVBrLcq9TG5bIU9Gt55vi X-Google-Smtp-Source: AMrXdXto36llWOpExNMpE5Z+3GJjwOgXwv5gBQUwX+6BD5D8g8CnoApIoq342GBEd/LPNLhyi7L9Bw== X-Received: by 2002:a7b:ca4f:0:b0:3d3:56ce:5673 with SMTP id m15-20020a7bca4f000000b003d356ce5673mr39142433wml.6.1672937061813; Thu, 05 Jan 2023 08:44:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/34] target/arm: Make RVBAR available for all ARMv8 CPUs Date: Thu, 5 Jan 2023 16:43:46 +0000 Message-Id: <20230105164417.3994639-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937644891100003 From: Tobias R=C3=B6hmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address with the rvbar property. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/cpu.c | 6 +++++- target/arm/helper.c | 21 ++++++++++++++------- 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2fa022f62ba..c107cbd7574 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -309,6 +309,10 @@ static void arm_cpu_reset_hold(Object *obj) env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, CPACR, CP11, 3); #endif + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.rvbar =3D cpu->rvbar_prop; + env->regs[15] =3D cpu->rvbar_prop; + } } =20 #if defined(CONFIG_USER_ONLY) @@ -1345,7 +1349,7 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_proper= ty); } =20 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); diff --git a/target/arm/helper.c b/target/arm/helper.c index 090daf93c71..d8066fe97d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7896,7 +7896,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64, + .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, .access =3D PL1_R, .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), @@ -7987,13 +7987,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) } /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .access =3D PL2_R, - .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + ARMCPRegInfo rvbar[] =3D { + { + .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .op= c2 =3D 1, + .access =3D PL2_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + }, + { .name =3D "RVBAR", .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc= 2 =3D 1, + .access =3D PL2_R, + .fieldoffset =3D offsetof(CPUARMState, cp15.rvbar), + }, }; - define_one_arm_cp_reg(cpu, &rvbar); + define_arm_cp_regs(cpu, rvbar); } } =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937135; cv=none; d=zohomail.com; s=zohoarc; b=biXmde0ZlOx30SoNHVAObSdTAudXd4RAdrNm4no/WHSOYnBtBZ8K4W7jomz5z1x7wA0PlWmJlOfyE/3NpyhGcVLCQgw1RflmSrwQmi+wqoYdbCfCW0Tri3XTUMU+RhIj5D8+TQ/y1gCIpUz/HhmEbQ6+CBknwIasAhJ60TxUbV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937135; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SBtE1WaPGjXlOvM4v7lfDebcyZ7mACd7pg2snYYPi6M=; b=G/2G8W0EGI/Dxt+T6tY9Fejm0YNFWA6v3ebYpNP4NDcm4OfVWEPtmP00ALC7dlpm78dZ9gKdVrgbiieOh0e+lan2IRHii/FjOclBlJVmubO5qCT3jt0zoiRRCnlYDVwXZXdm1NMwL+6kPhSjyjDZGuE6CdJGR4OuwTmMW7MECWE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937135697205.65816997148022; Thu, 5 Jan 2023 08:45:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTLx-0000S5-32; Thu, 05 Jan 2023 11:44:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLt-0000Ke-QB for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:25 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLr-0007M4-VT for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:25 -0500 Received: by mail-wm1-x333.google.com with SMTP id p1-20020a05600c1d8100b003d8c9b191e0so1773915wms.4 for ; Thu, 05 Jan 2023 08:44:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SBtE1WaPGjXlOvM4v7lfDebcyZ7mACd7pg2snYYPi6M=; b=ihjQueGM9bP+CPvnaesnHe1pT6sp2QspjYleUq+tvbjnNECfiS4cGKTObPe6p9YVhU c0SuWf9NpD157Dj0PVrutwqFK8ZZuEmb6Hc9uEctTLWMUmgUtmwnagPtP/KIZin66GHO IzsKgDLCUQv2SSX26vulTvteNiEocTq4HHrlacpRL9o1tM6Zrf8cSD6uQuDzBP0oFDZq qook4FiSSzMMpfQboEOEcmXv30sQQCup0A92xTaxMGttAngfmxvkva6Q1bwM3eqh4aIN B85gr5j4sXMEx36P4/TEF+J+hPyu9pbH8jKCKWQoXH2vvuXru9O2yYB/Z7ViSaaU7Ums M3cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SBtE1WaPGjXlOvM4v7lfDebcyZ7mACd7pg2snYYPi6M=; b=ck6G1aPM92hLM2gbc4hVrnglQxc59WS7GLdhQKN2aVWMmInPoI+miWYfK0ZY2rVqZK 2hLzA9AU4jfBS7+OlBNd6qmIMTUO53JPFgVbF72ClHdVM1/2nGZpKEtiXffulRe+3Wk6 +9wE5V846zNQGzM4rQ9q3snDF4kTReVemBefIt8CKZcDuSuCN3JkBewubYxVqZ3Pzj4N d0/k5KraVc0sa4Uu43zcTWccb4StKUzOyCE/5p19gTADtopwlyrcs6IOHdRUYJ2df0DL etD5c9K6KgyVKCguEhUFuG5aGMJT8igGE48t23SGpxzbUOCiQWWMe+7THWzGefqdl5EF OGAQ== X-Gm-Message-State: AFqh2krdayY5EO0yQLsqukGBY/cf5RBL3v8tBtCG05Njk9p7y4kODlzd LT6sT2IESgRBteaQW+Y94Q++OzHRqSvByi3w X-Google-Smtp-Source: AMrXdXuSg2soUoTlQ2qC9iZEWEphZlLGy3Qpj1isxmJzV03VfWSQHDimU/uDwvDOXO2AEYuz6C71jA== X-Received: by 2002:a05:600c:43ca:b0:3d0:73f5:b2c0 with SMTP id f10-20020a05600c43ca00b003d073f5b2c0mr38841841wmn.20.1672937062671; Thu, 05 Jan 2023 08:44:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/34] target/arm: Make stage_2_format for cache attributes optional Date: Thu, 5 Jan 2023 16:43:47 +0000 Message-Id: <20230105164417.3994639-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937137284100001 From: Tobias R=C3=B6hmel The v8R PMSAv8 has a two-stage MPU translation process, but, unlike VMSAv8, the stage 2 attributes are in the same format as the stage 1 attributes (8-bit MAIR format). Rather than converting the MAIR format to the format used for VMSA stage 2 (bits [5:2] of a VMSA stage 2 descriptor) and then converting back to do the attribute combination, allow combined_attrs_nofwb() to accept s2 attributes that are already in the MAIR format. We move the assert() to combined_attrs_fwb(), because that function really does require a VMSA stage 2 attribute format. (We will never get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.) Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/ptw.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2e7826dc29b..1c7c9cb5e37 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2361,7 +2361,11 @@ static uint8_t combined_attrs_nofwb(uint64_t hcr, { uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; =20 - s2_mair_attrs =3D convert_stage2_attrs(hcr, s2.attrs); + if (s2.is_s2_format) { + s2_mair_attrs =3D convert_stage2_attrs(hcr, s2.attrs); + } else { + s2_mair_attrs =3D s2.attrs; + } =20 s1lo =3D extract32(s1.attrs, 0, 4); s2lo =3D extract32(s2_mair_attrs, 0, 4); @@ -2418,6 +2422,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr) */ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2) { + assert(s2.is_s2_format && !s1.is_s2_format); + switch (s2.attrs) { case 7: /* Use stage 1 attributes */ @@ -2467,7 +2473,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, ARMCacheAttrs ret; bool tagged =3D false; =20 - assert(s2.is_s2_format && !s1.is_s2_format); + assert(!s1.is_s2_format); ret.is_s2_format =3D false; =20 if (s1.attrs =3D=3D 0xf0) { --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938633; cv=none; d=zohomail.com; s=zohoarc; b=J0BwzqE2PGBeN9GAH54AIa1BI6aEio7SFn6NVjDIoAtkT7E8NQ17lSJWgUF6EMh54ky7dvgl7a3SU2g2P2ksAK5avNbWhN3s9R6VBlcNoPjyVlRSC/swRMF35RHUgXJKbtXKFsuPbd1OJW8Tq3QwWxOx69syO3eIocwSKM2aDGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672938633; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V04Q2CJZVVTmActVLx4PP0ERtalL12YnqZ2E3ccFR8A=; b=i+UWZ5gnq5HMe7Iz0VmAWExrFlYc6j60h0GzEUafFA/n/t2dEFVthWHVz5am+4/rXo3GR97z8Zxn21GN9Rx2iGN64lIOJWU4WxxAVYSU1flfhvcYipXkdk92tFabRV9S40ysIIdpQsManfvyxgMcl0JAD9HqltKNc5ge5cUGv80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672938633786254.4244313640387; Thu, 5 Jan 2023 09:10:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTLy-0000SN-AI; Thu, 05 Jan 2023 11:44:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLu-0000O9-OY for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:26 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLs-0007MR-VS for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:26 -0500 Received: by mail-wm1-x32b.google.com with SMTP id ay2-20020a05600c1e0200b003d22e3e796dso1803494wmb.0 for ; Thu, 05 Jan 2023 08:44:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V04Q2CJZVVTmActVLx4PP0ERtalL12YnqZ2E3ccFR8A=; b=T8mjqMBc9Ht3YjC0UpJ8/V4IBgXv8kOLjG3I6S7ydweegYUBloGCSV3Um/YyUlxeb8 feWmBvRJxf8M0EHR8mypWPxzQlxpn+zY3iqG8K6Yn7FIzFaFTL2Gh5oyjQAHxF8/Phle uvy7WWZ7hRy1MqOJBIKp11LUOSNMK1a5LX9HbQYU5Mko6wX3TGTTTq5S9Z564hide39H 2SAzMv6kICm+kQHhF/DvDzRvLV9HTrKQ193zTYH5brCA0ThKrXI9pQ4MelwZuho1CXLk S275ySYSOznboEohF6hOomvPZqgXEPNbzAFKW56GekmBcH3SwW8/79zlMUUSmVehaIXy CpzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V04Q2CJZVVTmActVLx4PP0ERtalL12YnqZ2E3ccFR8A=; b=5Ou3SghOxykaAMBjNzFA1AO6t6+ZUp5ORR6xO1NSqrwtbnU/RWz2EuaJUk+acAIwVo BPuB2h/+6q4DuTse3dkYNxQBwREHGFs7VmKITVE0apGiAJlSCo3DjK8JhHhk6VgYxvtb 9LaFsBQ+UCaombVs6IyAdEB7B+bCZI0BUq6wPkOz+j13tjihPhrlOWkvgPIwC6VqcOm5 rj44fnd3hbhSVJ5ocKFDTeWXuAJyW4UQmJVYuLw/9KNZ4M8PJTkc63Jw0b6HvL/ZuX3A UvLQ7z0pPRHIqM/S7XL64mmg3jEy8u+OkQUs7SlWSf6jCKFrthh+LLxba8iMUKUZMnqW 8Cbw== X-Gm-Message-State: AFqh2kppZHYYZs6h1KjJ6oSY/hH7G1+T7MibeeLT2VrDCLGtK5e4HPkc byj3oM9PSNUfr3KQIMFk2gb/hFWiJNfF8KYs X-Google-Smtp-Source: AMrXdXu9PxyepZfLFZxESJLBdbs4YrJHwKvEaAheQxQvIQgqM/dQ+E7BdVJS8UPP9FRIDrOf1b5PVA== X-Received: by 2002:a05:600c:4b1d:b0:3d3:3deb:d916 with SMTP id i29-20020a05600c4b1d00b003d33debd916mr37333688wmp.4.1672937063602; Thu, 05 Jan 2023 08:44:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 Date: Thu, 5 Jan 2023 16:43:48 +0000 Message-Id: <20230105164417.3994639-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938634261100001 From: Tobias R=C3=B6hmel ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even tough they don't have the TTBCR register. See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile Version:A.c section C1.2. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/internals.h | 4 ++++ target/arm/debug_helper.c | 3 +++ target/arm/tlb_helper.c | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 161e42d50f4..d9555309df0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -257,6 +257,10 @@ unsigned int arm_pamax(ARMCPU *cpu); static inline bool extended_addresses_enabled(CPUARMState *env) { uint64_t tcr =3D env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + return true; + } return arm_el_is_aa64(env, 1) || (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); } diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index c21739242c5..2f6ddc0da57 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -437,6 +437,9 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *en= v) =20 if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { using_lpae =3D true; + } else if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + using_lpae =3D true; } else { if (arm_feature(env, ARM_FEATURE_LPAE) && (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 0f4f4fc8094..60abcbebe64 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -19,6 +19,10 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUId= x mmu_idx) if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { return true; } + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + return true; + } if (arm_feature(env, ARM_FEATURE_LPAE) && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { return true; --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672939694; cv=none; d=zohomail.com; s=zohoarc; b=Kt5F+8YRUeogYow8yNUs+8uuxTE1KaMt5n07gG061gd4fUF7gXixRbkPCwhnI1wB3TSq7v7fUdhI36RKxmCGGKs7ZlGsZohdnI++oU2Cu9kxlLLpBmaIlWTxQaLqzfKwnoBcTVi4c5UHRBcWFyXn6ofFSD7mEgLF8U6eT2rfixU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672939694; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/+yy8hrXR7W8CC89aup3gLLcA2qa4yC8gAslmEHdnXE=; b=hcO9pk6LvxGPD0P9MJ57FEANcpw2HRMaXljCryS8gtCleu8OGtZvyBNqm0dpDJ/nmSVqKo78SbFqttMB+Zd7HxB48TnEcNzTYCPVJTRRQ5JXQssm/ynbaeR5gaLACK5zlJACY4tOFVCJbKnmD5zfgp+COiVcnF/jRIzA8ow9BOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672939694957290.229830375176; Thu, 5 Jan 2023 09:28:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTM1-0000Z3-FM; Thu, 05 Jan 2023 11:44:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLw-0000S8-E4 for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:28 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLt-0007Mj-QC for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:28 -0500 Received: by mail-wm1-x335.google.com with SMTP id g10so14660828wmo.1 for ; Thu, 05 Jan 2023 08:44:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/+yy8hrXR7W8CC89aup3gLLcA2qa4yC8gAslmEHdnXE=; b=k7pJT1ESY39CpKZyRqhHGTks/E2MNfgoE2q53HlzQ21hS2+KR+KL8hZgVPV+cqgSsh HprP8PAYEWZpCSYgtG0KWvQf1iCN/e1YU0mEiIYglErUuI340J3+hMkxn1QMti2oEfkF SswD6VsZV1AsL86ce6R/GNgshMhafi1ONQ+nUsbc/VXQQaue5BdUArZuYiRUT0JQUipD 3Sa/2nPhUaVE+4KQxDHPlgfdmCuYxvRJLmv6h1SCJhCWnqT7nXbXcY98Cl0Uq7Gf28eR bYNs3YKBIoNkPzz2+1bOA+YGbUnH3u7zLqEDeiafNnNo++9ZaP06T35XJdi0QhE9Vgv4 RRNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939695965100001 From: Tobias R=C3=B6hmel Signed-off-by: Tobias R=C3=B6hmel Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 + target/arm/cpu.c | 28 +++- target/arm/helper.c | 302 +++++++++++++++++++++++++++++++++++++++++++ target/arm/machine.c | 28 ++++ 4 files changed, 360 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2b4bd20f9d0..bf2bce046d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -309,6 +309,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ @@ -745,8 +746,11 @@ typedef struct CPUArchState { */ uint32_t *rbar[M_REG_NUM_BANKS]; uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t *hprbar; + uint32_t *hprlar; uint32_t mair0[M_REG_NUM_BANKS]; uint32_t mair1[M_REG_NUM_BANKS]; + uint32_t hprselr; } pmsav8; =20 /* v8M SAU */ @@ -906,6 +910,8 @@ struct ArchCPU { bool has_mpu; /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; + /* PMSAv8 MPU number of supported hyp regions */ + uint32_t pmsav8r_hdregion; /* v8M SAU number of supported regions */ uint32_t sau_sregion; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c107cbd7574..f99f749b295 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -491,6 +491,14 @@ static void arm_cpu_reset_hold(Object *obj) sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } } + + if (cpu->pmsav8r_hdregion > 0) { + memset(env->pmsav8.hprbar, 0, + sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); + memset(env->pmsav8.hprlar, 0, + sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); + } + env->pmsav7.rnr[M_REG_NS] =3D 0; env->pmsav7.rnr[M_REG_S] =3D 0; env->pmsav8.mair0[M_REG_NS] =3D 0; @@ -2002,11 +2010,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) /* MPU can be configured out of a PMSA CPU either by setting has-mpu * to false or by setting pmsav7-dregion to 0. */ - if (!cpu->has_mpu) { - cpu->pmsav7_dregion =3D 0; - } - if (cpu->pmsav7_dregion =3D=3D 0) { + if (!cpu->has_mpu || cpu->pmsav7_dregion =3D=3D 0) { cpu->has_mpu =3D false; + cpu->pmsav7_dregion =3D 0; + cpu->pmsav8r_hdregion =3D 0; } =20 if (arm_feature(env, ARM_FEATURE_PMSA) && @@ -2033,6 +2040,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->pmsav7.dracr =3D g_new0(uint32_t, nr); } } + + if (cpu->pmsav8r_hdregion > 0xff) { + error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, + cpu->pmsav8r_hdregion); + return; + } + + if (cpu->pmsav8r_hdregion) { + env->pmsav8.hprbar =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + env->pmsav8.hprlar =3D g_new0(uint32_t, + cpu->pmsav8r_hdregion); + } } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index d8066fe97d3..b13f6ff328c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3682,6 +3682,222 @@ static void pmsav7_rgnr_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] =3D value; +} + +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; +} + +static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* + * Ignore writes that would select not implemented region. + * This is architecturally UNPREDICTABLE. + */ + if (value >=3D cpu->pmsav7_dregion) { + return; + } + + env->pmsav7.rnr[M_REG_NS] =3D value; +} + +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprbar[env->pmsav8.hprselr] =3D value; +} + +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprbar[env->pmsav8.hprselr]; +} + +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + env->pmsav8.hprlar[env->pmsav8.hprselr] =3D value; +} + +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pmsav8.hprlar[env->pmsav8.hprselr]; +} + +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t n; + uint32_t bit; + ARMCPU *cpu =3D env_archcpu(env); + + /* Ignore writes to unimplemented regions */ + int rmax =3D MIN(cpu->pmsav8r_hdregion, 32); + value &=3D MAKE_64BIT_MASK(0, rmax); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < rmax; ++n) { + bit =3D extract32(value, n, 1); + env->pmsav8.hprlar[n] =3D deposit32( + env->pmsav8.hprlar[n], 0, 1, bit); + } +} + +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t n; + uint32_t result =3D 0x0; + ARMCPU *cpu =3D env_archcpu(env); + + /* Register alias is only valid for first 32 indexes */ + for (n =3D 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { + if (env->pmsav8.hprlar[n] & 0x1) { + result |=3D (0x1 << n); + } + } + return result; +} + +static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* + * Ignore writes that would select not implemented region. + * This is architecturally UNPREDICTABLE. + */ + if (value >=3D cpu->pmsav8r_hdregion) { + return; + } + + env->pmsav8.hprselr =3D value; +} + +static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (extract32(ri->opc0, 0, 1) << 4) | + (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, = 2, 1); + + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + + if (ri->opc1 & 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.hprlar[index] =3D value; + } else { + env->pmsav8.hprbar[index] =3D value; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return; + } + if (ri->opc2 & 0x1) { + env->pmsav8.rlar[M_REG_NS][index] =3D value; + } else { + env->pmsav8.rbar[M_REG_NS][index] =3D value; + } + } +} + +static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint8_t index =3D (extract32(ri->opc0, 0, 1) << 4) | + (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, = 2, 1); + + if (ri->opc1 & 4) { + if (index >=3D cpu->pmsav8r_hdregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.hprlar[index]; + } else { + return env->pmsav8.hprbar[index]; + } + } else { + if (index >=3D cpu->pmsav7_dregion) { + return 0x0; + } + if (ri->opc2 & 0x1) { + return env->pmsav8.rlar[M_REG_NS][index]; + } else { + return env->pmsav8.rbar[M_REG_NS][index]; + } + } +} + +static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { + { .name =3D "PRBAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tvm_trvm, + .readfn =3D prbar_read, .writefn =3D prbar_write }, + { .name =3D "PRLAR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tvm_trvm, + .readfn =3D prlar_read, .writefn =3D prlar_write }, + { .name =3D "PRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D prselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) }, + { .name =3D "HPRBAR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D hprbar_read, .writefn =3D hprbar_write }, + { .name =3D "HPRLAR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D hprlar_read, .writefn =3D hprlar_write }, + { .name =3D "HPRSELR", .resetvalue =3D 0, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, + .writefn =3D hprselr_write, + .fieldoffset =3D offsetof(CPUARMState, pmsav8.hprselr) }, + { .name =3D "HPRENR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_NO_RAW, + .readfn =3D hprenr_read, .writefn =3D hprenr_write }, +}; + static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { /* Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do @@ -8207,6 +8423,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; + /* HMPUIR is specific to PMSA V8 */ + ARMCPRegInfo id_hmpuir_reginfo =3D { + .name =3D "HMPUIR", + .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav8r_hdregion + }; static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, @@ -8249,6 +8472,74 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, id_cp_reginfo); if (!arm_feature(env, ARM_FEATURE_PMSA)) { define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + uint32_t i =3D 0; + char *tmp_string; + + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); + define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { + uint8_t crm =3D 0b1000 | extract32(i, 1, 3); + uint8_t opc1 =3D extract32(i, 4, 1); + uint8_t opc2 =3D extract32(i, 0, 1) << 2; + + tmp_string =3D g_strdup_printf("PRBAR%u", i); + ARMCPRegInfo tmp_prbarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS | ARM_CP_= NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); + g_free(tmp_string); + + opc2 =3D extract32(i, 0, 1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("PRLAR%u", i); + ARMCPRegInfo tmp_prlarn_reginfo =3D { + .name =3D tmp_string, .type =3D ARM_CP_ALIAS | ARM_CP_= NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL1_RW, .resetvalue =3D 0, + .accessfn =3D access_tvm_trvm, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); + g_free(tmp_string); + } + + /* Register alias is only valid for first 32 indexes */ + for (i =3D 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { + uint8_t crm =3D 0b1000 | extract32(i, 1, 3); + uint8_t opc1 =3D 0b100 | extract32(i, 4, 1); + uint8_t opc2 =3D extract32(i, 0, 1) << 2; + + tmp_string =3D g_strdup_printf("HPRBAR%u", i); + ARMCPRegInfo tmp_hprbarn_reginfo =3D { + .name =3D tmp_string, + .type =3D ARM_CP_NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); + g_free(tmp_string); + + opc2 =3D extract32(i, 0, 1) << 2 | 0x1; + tmp_string =3D g_strdup_printf("HPRLAR%u", i); + ARMCPRegInfo tmp_hprlarn_reginfo =3D { + .name =3D tmp_string, + .type =3D ARM_CP_NO_RAW, + .cp =3D 15, .opc1 =3D opc1, .crn =3D 6, .crm =3D crm, = .opc2 =3D opc2, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D pmsav8r_regn_write, .readfn =3D pmsav8r_r= egn_read + }; + define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); + g_free(tmp_string); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); } @@ -8370,6 +8661,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; } define_one_arm_cp_reg(cpu, &sctlr); + + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + ARMCPRegInfo vsctlr =3D { + .name =3D "VSCTLR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D= 0, + .access =3D PL2_RW, .resetvalue =3D 0x0, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vsctlr), + }; + define_one_arm_cp_reg(cpu, &vsctlr); + } } =20 if (cpu_isar_feature(aa64_lor, cpu)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433d..5f261526525 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -487,6 +487,30 @@ static bool pmsav8_needed(void *opaque) arm_feature(env, ARM_FEATURE_V8); } =20 +static bool pmsav8r_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8) && + !arm_feature(env, ARM_FEATURE_M); +} + +static const VMStateDescription vmstate_pmsav8r =3D { + .name =3D "cpu/pmsav8/pmsav8r", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav8r_needed, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU, + pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_pmsav8 =3D { .name =3D "cpu/pmsav8", .version_id =3D 1, @@ -500,6 +524,10 @@ static const VMStateDescription vmstate_pmsav8 =3D { VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_pmsav8r, + NULL } }; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2hpQCTC8nGWhTVif5Vc0Cni0nOiQ1N1H86BSl5lGHtY=; b=Vm33gnULgSEbiU7G7P3KP/PiqYRBgKnQpK4MGLC9BNviCe2V2H/olJUXsfnGUZK4tH 9jL5MX7rzZcxlnZG+0tOcODXdIZc5SpZb4211ewev17Tsl+clWPiMgvigRvEZfFdj/g3 54YfFkJLRlgfwTyhbc7OoUkdGBYh81/eNVbwBRViLKojQkxNmFLwLFt8s1lCapZZSGvx FbgjpaKqJFrdXC8X4MrHFp4I5ZTWrRjKibXfoz0ZHkMBhx087+J7eJXo7QAmfEOv0XS6 p5gP4zQS9DN+TSdo7NsUwjzyRfKLumHHEqSQ++wpz7DTjyRTB+HG2nMfe9eqos2PYG/S KqjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2hpQCTC8nGWhTVif5Vc0Cni0nOiQ1N1H86BSl5lGHtY=; b=YEKwgtQ90H/iTqxq/HkNPDhBwQE9cqVEIKOocFfDjkKGMIsz3aWCpfR9BTXd9out4Q l2iucxXQ6vY0zeQTHWgUZCLsTycdfhNPp6ep4pMFkHxcW14NYdNR58VDdbm5990esdYX w7+f1G54O4okRVAJIxUql3D6jsOi+HMFHViM1O+jRWzZuyyGJjHj2+xyeEgt2wy4c94l OaYJIWpOMiVxemNIoTuOnRUsees0Gsa9cBIWmB13TB+xUO1QS0FvRiJ1q2mMmrV5Bxc7 O2rV5a/us2ueRXS7s5z0JKy76ZckWVYANoGEtaLeH5w2wAC1JCfs9CF2SgEgOZ8bVyRw nGFA== X-Gm-Message-State: AFqh2krIyl40s9PK0GrtXLwJwbMO9pvGXyCTKSS8LYfZIdK7N5QX/mzy EvTGMjXFs1e1TyTVJrELBUVntYrnPppkIqxu X-Google-Smtp-Source: AMrXdXsQmRqcwlswN/gFuehVmKPz9hQmtvK8ID4BdtyXkvqFwG1bwTkx06hB/1kC0cBOBV1jZ9tVQA== X-Received: by 2002:a05:600c:c06:b0:3d9:7065:5b9c with SMTP id fm6-20020a05600c0c0600b003d970655b9cmr31602205wmb.6.1672937065188; Thu, 05 Jan 2023 08:44:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/34] target/arm: Add PMSAv8r functionality Date: Thu, 5 Jan 2023 16:43:50 +0000 Message-Id: <20230105164417.3994639-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938251367100003 From: Tobias R=C3=B6hmel Add PMSAv8r translation. Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 104 insertions(+), 22 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1c7c9cb5e37..4bda0590c7c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1758,9 +1758,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu= , ARMMMUIdx mmu_idx, =20 if (arm_feature(env, ARM_FEATURE_M)) { return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MA= SK; - } else { - return regime_sctlr(env, mmu_idx) & SCTLR_BR; } + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return false; + } + + return regime_sctlr(env, mmu_idx) & SCTLR_BR; } =20 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, @@ -1952,6 +1956,26 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, return !(result->f.prot & (1 << access_type)); } =20 +static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprbar; + } else { + return env->pmsav8.rbar[secure]; + } +} + +static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t secure) +{ + if (regime_el(env, mmu_idx) =3D=3D 2) { + return env->pmsav8.hprlar; + } else { + return env->pmsav8.rlar[secure]; + } +} + bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool secure, GetPhysAddrResult *result, @@ -1974,6 +1998,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, bool hit =3D false; uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); + int region_counter; + + if (regime_el(env, mmu_idx) =3D=3D 2) { + region_counter =3D cpu->pmsav8r_hdregion; + } else { + region_counter =3D cpu->pmsav7_dregion; + } =20 result->f.lg_page_size =3D TARGET_PAGE_BITS; result->f.phys_addr =3D address; @@ -1982,6 +2013,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, *mregion =3D -1; } =20 + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + fi->stage2 =3D true; + } + /* * Unlike the ARM ARM pseudocode, we don't need to check whether this * was an exception vector read from the vector table (which is always @@ -1998,17 +2033,26 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, hit =3D true; } =20 - for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + uint32_t bitmask; + if (arm_feature(env, ARM_FEATURE_M)) { + bitmask =3D 0x1f; + } else { + bitmask =3D 0x3f; + fi->level =3D 0; + } + + for (n =3D region_counter - 1; n >=3D 0; n--) { /* region search */ /* - * Note that the base address is bits [31:5] from the register - * with bits [4:0] all zeroes, but the limit address is bits - * [31:5] from the register with bits [4:0] all ones. + * Note that the base address is bits [31:x] from the register + * with bits [x-1:0] all zeroes, but the limit address is bits + * [31:x] from the register with bits [x:0] all ones. Where x = is + * 5 for Cortex-M and 6 for Cortex-R */ - uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; + uint32_t base =3D regime_rbar(env, mmu_idx, secure)[n] & ~bitm= ask; + uint32_t limit =3D regime_rlar(env, mmu_idx, secure)[n] | bitm= ask; =20 - if (!(env->pmsav8.rlar[secure][n] & 0x1)) { + if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) { /* Region disabled */ continue; } @@ -2042,7 +2086,9 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * PMSAv7 where highest-numbered-region wins) */ fi->type =3D ARMFault_Permission; - fi->level =3D 1; + if (arm_feature(env, ARM_FEATURE_M)) { + fi->level =3D 1; + } return true; } =20 @@ -2052,8 +2098,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, } =20 if (!hit) { - /* background fault */ - fi->type =3D ARMFault_Background; + if (arm_feature(env, ARM_FEATURE_M)) { + fi->type =3D ARMFault_Background; + } else { + fi->type =3D ARMFault_Permission; + } return true; } =20 @@ -2061,12 +2110,14 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, /* hit using the background region */ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.pro= t); } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + uint32_t matched_rbar =3D regime_rbar(env, mmu_idx, secure)[matchr= egion]; + uint32_t matched_rlar =3D regime_rlar(env, mmu_idx, secure)[matchr= egion]; + uint32_t ap =3D extract32(matched_rbar, 1, 2); + uint32_t xn =3D extract32(matched_rbar, 0, 1); bool pxn =3D false; =20 if (arm_feature(env, ARM_FEATURE_V8_1M)) { - pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + pxn =3D extract32(matched_rlar, 4, 1); } =20 if (m_is_system_region(env, address)) { @@ -2074,21 +2125,46 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, xn =3D 1; } =20 - result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (regime_el(env, mmu_idx) =3D=3D 2) { + result->f.prot =3D simple_ap_to_rw_prot_is_user(ap, + mmu_idx !=3D ARMMMUIdx_E2); + } else { + result->f.prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + } + + if (!arm_feature(env, ARM_FEATURE_M)) { + uint8_t attrindx =3D extract32(matched_rlar, 1, 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + uint8_t sh =3D extract32(matched_rlar, 3, 2); + + if (regime_sctlr(env, mmu_idx) & SCTLR_WXN && + result->f.prot & PAGE_WRITE && mmu_idx !=3D ARMMMUIdx_Stag= e2) { + xn =3D 0x1; + } + + if ((regime_el(env, mmu_idx) =3D=3D 1) && + regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap =3D=3D 0x1) { + pxn =3D 0x1; + } + + result->cacheattrs.is_s2_format =3D false; + result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); + result->cacheattrs.shareability =3D sh; + } + if (result->f.prot && !xn && !(pxn && !is_user)) { result->f.prot |=3D PAGE_EXEC; } - /* - * We don't need to look the attribute up in the MAIR0/MAIR1 - * registers because that only tells us about cacheability. - */ + if (mregion) { *mregion =3D matchregion; } } =20 fi->type =3D ARMFault_Permission; - fi->level =3D 1; + if (arm_feature(env, ARM_FEATURE_M)) { + fi->level =3D 1; + } return !(result->f.prot & (1 << access_type)); } =20 @@ -2649,7 +2725,13 @@ static bool get_phys_addr_twostage(CPUARMState *env,= S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result,= fi); + if (arm_feature(env, ARM_FEATURE_PMSA)) { + ret =3D get_phys_addr_pmsav8(env, ipa, access_type, + ptw->in_mmu_idx, is_secure, result, fi); + } else { + ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, + is_el0, result, fi); + } fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938982571100003 From: Tobias R=C3=B6hmel All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 Signed-off-by: Tobias R=C3=B6hmel Reviewed-by: Peter Maydell Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell --- target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 568cbcfc524..ccde5080eb7 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -854,6 +854,47 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 +static void cortex_r52_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + cpu->midr =3D 0x411fd133; /* r1p3 */ + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034023; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8144c004; + cpu->reset_sctlr =3D 0x30c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x10111001; + cpu->isar.id_dfr0 =3D 0x03010006; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00211040; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0xf0102211; + cpu->isar.id_mmfr4 =3D 0x00000010; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232142; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x00010001; + cpu->isar.dbgdidr =3D 0x77168000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + + cpu->pmsav7_dregion =3D 16; + cpu->pmsav8r_hdregion =3D 16; +} + static void cortex_r5f_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1163,6 +1204,7 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, + { .name =3D "cortex-r52", .initfn =3D cortex_r52_initfn }, { .name =3D "ti925t", .initfn =3D ti925t_initfn }, { .name =3D "sa1100", .initfn =3D sa1100_initfn }, { .name =3D "sa1110", .initfn =3D sa1110_initfn }, --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0ayPkdxL46XexnzpSXNyqqZUrm3nHdGW7BqfJTrIiyQ=; b=z7NRP06DQkj+cy/2LKOW04y6z2BTqgon7pm4YonyqyR8qjV9Pv6fg3cgtTRCPysfSe hbHojJxu+TXBON9CYQCYAvCfN0V7X/F6EXMfFsSrVBu9YDqZOTLzPI2fxqGn3sIAp8bC Y8ez7CHYnpRdvxykgdXkAAyhDVPndYXTWISWIk5gPdQLlQJnpozCTNPqih2deY9VN1nr wsfCAjqM4wZX3RsG9Prnfnnhpk/NhhQsojSub47qTF7fKT4oZB4M1CAZOdEcKFJzuOQY LhzTRDiE5a3TryyksOLWJSW5beRahy0Tr5LoEOQ7JFzD9tzbrQYMxQP2D5vXlR08s0hy WwRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0ayPkdxL46XexnzpSXNyqqZUrm3nHdGW7BqfJTrIiyQ=; b=IVo9hbUtBv8jF8CgFtTqt7NGT+ZfeWg84L2LzI6NMRVQZ0rqRofMGhuwoDhqJa5nE3 vyisCCefo3Khe3TsWdXAu00RvaETrrWiLOr1NHZWpWwqW+DBKOW42q4kJlahPAyRxvQq y+ZnIXsSfSwKAfE2haKoDc4aj4KTa45hXkhjERTzTou06TWgUvvdq7o1dMDiicMLwn1I amUiJv3KhLXwWdthyjTqHMay8t1CHwVJSKjQA0FwgFAsMW/rm0U0WkFqUGHqJ+oyN5LU 9Rw6rpiTa8pEvn97yvpSahv4DcgJ7B0yl8ABhzs3Oseg9ysyv1z5IvQB1T/wEfFMf2zH GLCg== X-Gm-Message-State: AFqh2kqUULFb2/FOUdbAYnUz6OPvXQY+xy/B77kukrHpxvWH+aT7/u0l p75Wh0QHmpj0cP4ipPAQN1ivoNalqwa6EvZX X-Google-Smtp-Source: AMrXdXvvPVEheLzfwifwAcLAgEQOfHc5qN4Gzmicn5KitdQeFwbdLrHlmGiNLym6i9NvQMvU+rIJ5g== X-Received: by 2002:a05:600c:a51:b0:3cf:6f4d:c259 with SMTP id c17-20020a05600c0a5100b003cf6f4dc259mr35900013wmq.39.1672937066800; Thu, 05 Jan 2023 08:44:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/34] target/arm: fix handling of HLT semihosting in system mode Date: Thu, 5 Jan 2023 16:43:52 +0000 Message-Id: <20230105164417.3994639-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939840965100003 From: Alex Benn=C3=A9e The check semihosting_enabled() wants to know if the guest is currently in user mode. Unlike the other cases the test was inverted causing us to block semihosting calls in non-EL0 modes. Cc: qemu-stable@nongnu.org Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=3Don) Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 74a903072fe..1dcaefb8e75 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1184,7 +1184,7 @@ static inline void gen_hlt(DisasContext *s, int imm) * semihosting, to provide some semblance of security * (and for consistency with our 32-bit semihosting). */ - if (semihosting_enabled(s->current_el !=3D 0) && + if (semihosting_enabled(s->current_el =3D=3D 0) && (imm =3D=3D (s->thumb ? 0x3c : 0xf000))) { gen_exception_internal_insn(s, EXCP_SEMIHOST); return; --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937203; cv=none; d=zohomail.com; s=zohoarc; b=OFEGjiYSIAJbI8WzHC4JhsHQlMGfJ9qa0rwp+4GfsHrr2C9iVGvnPxvyg0HdBvl26mWEeX6N4vxqjoau5KpfDMR09Ppl+v4iK9Za7pTRmOfqcC2g8Y+eszd9Vq0kCgdr6uvTvhrum1RawjcrTephnQb0sfLXYwnPbn3otn2xhN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937203; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5SjlNN0Q6eegKF4lgc+ItSkFv4TSnZq46y/byWdrbtE=; b=YzbtOHrqUzyIU34Q+BthhKcV4NDAcuBQq9Ub/e4rrMHqxAH+ajfJ/Okm70NnBIrpumaeSgR3omH1ootqO5BblNtAmsteDhJBEiRRGGf05YuoxcNRkKF27PFUYgUzLfQUsPXhm7OTiGuK04BuFYmRbg2tv6TVFCCPE/fLQeLAWsQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937203469146.02144768442213; Thu, 5 Jan 2023 08:46:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMJ-0000oi-OK; Thu, 05 Jan 2023 11:44:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM1-0000Yu-8l for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:33 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLy-0007Nx-8k for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:32 -0500 Received: by mail-wm1-x32e.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso1776511wms.5 for ; Thu, 05 Jan 2023 08:44:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5SjlNN0Q6eegKF4lgc+ItSkFv4TSnZq46y/byWdrbtE=; b=tQr6otgFj0AWru8PBTY4y30StmfEOHh96EWjLbCDssCaBlDpgRZYu/JCj3QO/BSL/u m14DlXT/5cJU6f8mq+inVy+u+RJPzOitktj9v3xv0JDVw/CZLYqpH8JAz2wlBxMYJmAn 1t0TvSojs8Nyxqi2xMRWhljFip/fOE42KhhRWBtCsUAS8BKYMUzrEj4Wh2sQKRb3o2tN Ixm8AgfaBXzqlXRol/MnHM7eWDkRyOPaWv+V8SZPYp5nCuYOQaaT5KHHOAgqITH5N8WR ehNaGObHYkZ2ETPNXzLSUhpbu+jOZrwRUwiV2aQ+2kjvZVtUDtkCgVL9kIibSy0oWIY/ KUrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5SjlNN0Q6eegKF4lgc+ItSkFv4TSnZq46y/byWdrbtE=; b=6wwQgSNe9tvrdidPdVb9zxVkQuw+WV4g3p3cmmU2KSvjLrqqENYQmWeEVRyLyUsgGW tGF0p58sgjvAKBtugAdFSvK3WVDFXMZnGcARWN3ijSHvyXAdxvF4XlIct+9iy8l9al+R /dblCRPNILpQ/jl3S1RoieHWV3rmQ/3fCgNlH9AfL6EAZGDNZplHrZzAQg3cj5uOUbE1 VHjUeaGdqKbmc2k10acXqBbPZOGbctMp06ykhzpF3ZYXX9+ZPq5s51IIQSd3ijhJUrYo oduf4BiwSpqMML7qcCNVzRUZuQumqraXQ+YtYlyAgkJgrfXOJUzNXgOAFpnadUmJX8/L W/fw== X-Gm-Message-State: AFqh2koQ0WcgNgCx4a7hubUtLKKlHH8c5PYjO6GldUP95a58rt8L2vpd VW25ECc6JZxIuY0lUmklJsSLiGK+gRJBkXYA X-Google-Smtp-Source: AMrXdXuTnkdG20D4/3ZRToiAkRDWHs3KNtvcQIuWx6yCf/+YZSUmqXnOIJGQnWXLUMmvdn5ted78tw== X-Received: by 2002:a05:600c:3493:b0:3d2:370b:97f4 with SMTP id a19-20020a05600c349300b003d2370b97f4mr41176082wmq.16.1672937067542; Thu, 05 Jan 2023 08:44:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/34] hw/timer/imx_epit: improve comments Date: Thu, 5 Jan 2023 16:43:53 +0000 Message-Id: <20230105164417.3994639-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937203835100001 Content-Type: text/plain; charset="utf-8" From: Axel Heider Fix typos, add background information Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index ec0fa440d72..2841fbaa1c8 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -96,13 +96,14 @@ static void imx_epit_set_freq(IMXEPITState *s) } } =20 +/* + * This is called both on hardware (device) reset and software reset. + */ static void imx_epit_reset(DeviceState *dev) { IMXEPITState *s =3D IMX_EPIT(dev); =20 - /* - * Soft reset doesn't touch some bits; hard reset clears them - */ + /* Soft reset doesn't touch some bits; hard reset clears them */ s->cr &=3D (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); s->sr =3D 0; s->lr =3D EPIT_TIMER_MAX; @@ -214,6 +215,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); =20 + /* Update the frequency. Has been done already in case of a reset.= */ if (!(s->cr & CR_SWR)) { imx_epit_set_freq(s); } @@ -254,7 +256,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, break; =20 case 1: /* SR - ACK*/ - /* writing 1 to OCIF clear the OCIF bit */ + /* writing 1 to OCIF clears the OCIF bit */ if (value & 0x01) { s->sr =3D 0; imx_epit_update_int(s); @@ -352,8 +354,18 @@ static void imx_epit_realize(DeviceState *dev, Error *= *errp) 0x00001000); sysbus_init_mmio(sbd, &s->iomem); =20 + /* + * The reload timer keeps running when the peripheral is enabled. It i= s a + * kind of wall clock that does not generate any interrupts. The callb= ack + * needs to be provided, but it does nothing as the ptimer already sup= ports + * all necessary reloading functionality. + */ s->timer_reload =3D ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGA= CY); =20 + /* + * The compare timer is running only when the peripheral configuration= is + * in a state that will generate compare interrupts. + */ s->timer_cmp =3D ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); } =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672939564; cv=none; d=zohomail.com; s=zohoarc; b=czV/l3QgfSxqcdyKX30lXK5SCsTHSwT0elGZl7kuiYWEg7Dn7taTmp1e1/3npsfflBcLkJ43oEKfI44qT4HH9YZKpYaaI25O/h8LZ+/EIhduPq3SnXtCclIYMBFn78AXFqFv6LrAA6D6RGdPRxSCrtQ5LX+JNYeygdikrvGtF7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672939564; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4lYj5lfrX23EEPpJVAljAbbuQWpQ9S1qrdtCZ8SVOo0=; b=KUogfVsr/kpDreXj6nTLFd4RDWVUDlMuhBE9tGOb8ep0khg+NoKMgj+2hLQ8Rg2ucUnb2s+h0UNoPTusdIYQeQt63FB7zZcQ70IepaoIl7IIURP4LSmvxM9TedA8UCgF6t1JI49QBkRWEQWKtRlfDn0KTaygMwI6wjTO8iNF0H0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672939564109210.97894717456336; Thu, 5 Jan 2023 09:26:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMO-0000uA-8X; Thu, 05 Jan 2023 11:44:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM1-0000Yw-A0 for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:33 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTLy-0007M4-9M for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:33 -0500 Received: by mail-wm1-x333.google.com with SMTP id p1-20020a05600c1d8100b003d8c9b191e0so1774091wms.4 for ; Thu, 05 Jan 2023 08:44:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4lYj5lfrX23EEPpJVAljAbbuQWpQ9S1qrdtCZ8SVOo0=; b=naDdzj0PBXlEs8HQw9FMQFoKAI5aUqssiWIBKtRjf6B1faIsU7Tasp15JKEfQiMKZ1 Q9ptHA9WjYYKsPOGyUUKw0Mo9RVbQNYSKmwjudxcYOnZPO5KkC6GRVeRU9NXbi40DFyd P00khDvPCjPRlFKF3WOgLuebcd0MkMPOaXec8hQTBVwnT0piaHz1AN+1gk2+qvzCEO26 nXYVxiw0yP0dBiCDeSgf5oH1ByzbCiuubuV//NwxykSdHUAjMWWeZe4f4ebIQtBZqgk1 DT+5bN1xfcnCxuZ4Xyc2Bb6AcTuDEYbUuqMGoQauUVcgrl1KTHMHxW4Rh9P/3V1RHvRh QtBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4lYj5lfrX23EEPpJVAljAbbuQWpQ9S1qrdtCZ8SVOo0=; b=3/6/h0IJIMTflepoNRTP76NRcB31khx/jUNBVwk3HYS6eUfTd5QNxDGtNjxfUP5G9M CQO8jVLqTcnUQBnFfQ0hm49K9Zo0R48TUqKw9UrAV+q+1tiLwk/0lR2NigjljAsCnSfa Fpnef0MfxyfrqS7R+K95nIMOE/+gi6R6VnZq4g0V8UIFwbcxthNPHCkh5emBubI5loeQ Cfza+zs1iaZG+vzqnPVBksZiPkUNL+szkJb6xfilCEYY5Q3cruatKKNhN/huD63S+96U dNO7Eqygt6awd8jJT3wfdfUSHuPpo7hrb5lNZgMhmLgLW9Aur0Jrxqjxuqj5qz94nynB 0vEQ== X-Gm-Message-State: AFqh2kqkEIal/MjQ0pK3pfMl5pBsq7EapU2TVtF/iojQOVNkxWP/K5CZ oXYKBGZaxK8210Mj2HwfXx7zkwG2HYD1mWAw X-Google-Smtp-Source: AMrXdXv2mxu+kcol/Jeh5EphJpCWNal2k3yAGKFkupAPlgBUqsuNxb3E2+We/erBShE2ycJn+FVpbQ== X-Received: by 2002:a05:600c:3d1b:b0:3d0:6a57:66a5 with SMTP id bh27-20020a05600c3d1b00b003d06a5766a5mr36113770wmb.0.1672937068350; Thu, 05 Jan 2023 08:44:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/34] hw/timer/imx_epit: cleanup CR defines Date: Thu, 5 Jan 2023 16:43:54 +0000 Message-Id: <20230105164417.3994639-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939565390100001 Content-Type: text/plain; charset="utf-8" From: Axel Heider remove unused defines, add needed defines Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 4 ++-- hw/timer/imx_epit.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 2acc41e9822..e2cb96229be 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -43,7 +43,7 @@ #define CR_OCIEN (1 << 2) #define CR_RLD (1 << 3) #define CR_PRESCALE_SHIFT (4) -#define CR_PRESCALE_MASK (0xfff) +#define CR_PRESCALE_BITS (12) #define CR_SWR (1 << 16) #define CR_IOVW (1 << 17) #define CR_DBGEN (1 << 18) @@ -51,7 +51,7 @@ #define CR_DOZEN (1 << 20) #define CR_STOPEN (1 << 21) #define CR_CLKSRC_SHIFT (24) -#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT) +#define CR_CLKSRC_BITS (2) =20 #define EPIT_TIMER_MAX 0XFFFFFFFFUL =20 diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 2841fbaa1c8..661e9158e3b 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -82,8 +82,8 @@ static void imx_epit_set_freq(IMXEPITState *s) uint32_t clksrc; uint32_t prescaler; =20 - clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, 2); - prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12); + clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); + prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS= ); =20 s->freq =3D imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]) / prescaler; --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937735; cv=none; d=zohomail.com; s=zohoarc; b=UvUM4RR9bPyqnHy2j0TpW7LstP01tmZtks0+cOXgHzxvMMyGMEjcm2o9eMCXvixY2/TV83Ev1LnQG+vbM9HcJRtmIknAUV23V5e52omNsodM7Ie+LrJ44i6bfFk02X9BD+HeSlyCfiWW4QTi+MqlTuGSaklFyLSCyJqAs4oXVxQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937735435100007 Content-Type: text/plain; charset="utf-8" From: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 2 ++ hw/timer/imx_epit.c | 12 ++++++------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index e2cb96229be..783eaf0c3a6 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -53,6 +53,8 @@ #define CR_CLKSRC_SHIFT (24) #define CR_CLKSRC_BITS (2) =20 +#define SR_OCIF (1 << 0) + #define EPIT_TIMER_MAX 0XFFFFFFFFUL =20 #define TYPE_IMX_EPIT "imx.epit" diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 661e9158e3b..f148868b8cb 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -66,7 +66,7 @@ static const IMXClk imx_epit_clocks[] =3D { */ static void imx_epit_update_int(IMXEPITState *s) { - if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { + if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { qemu_irq_raise(s->irq); } else { qemu_irq_lower(s->irq); @@ -256,9 +256,9 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, break; =20 case 1: /* SR - ACK*/ - /* writing 1 to OCIF clears the OCIF bit */ - if (value & 0x01) { - s->sr =3D 0; + /* writing 1 to SR.OCIF clears this bit and turns the interrupt of= f */ + if (value & SR_OCIF) { + s->sr =3D 0; /* SR.OCIF is the only bit in this register anywa= y */ imx_epit_update_int(s); } break; @@ -309,8 +309,8 @@ static void imx_epit_cmp(void *opaque) IMXEPITState *s =3D IMX_EPIT(opaque); =20 DPRINTF("sr was %d\n", s->sr); - - s->sr =3D 1; + /* Set interrupt status bit SR.OCIF and update the interrupt state */ + s->sr |=3D SR_OCIF; imx_epit_update_int(s); } =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2FLbsaEjrO+mfvP9azEL7lq/R52dHqN0L8IGeRLVJ0o=; b=jP+hA+y0EWKOILuYbI6CaDIEVAXZl4N/unlllakrSk5WmOGEl+nAOKOVBoeP4Tlreo LJAUHEhZ2kRsX1ppg+bkuk84CWwuYUAAJt5a95WjN1Nk39zJxSfwp7yF202lpqSDAG9O udImk0oHOG9MofnR1n3ZVcsozqGhTjWD8M6suJSwxImSmqpdZFCUJdaFYKvrGdNRS6GY Ltgr8O9ejjVPjxaZShs2MxnGyPWCfWxquR5BfiId7ujG63R4VnQpRU+bqQ1LjiRz29gI PNJd07DKupiDb5CcJX5cifs0UBV43qcl7fags6mX/xf3loQdPrFGnGunDH8sQOcbai4J NWvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2FLbsaEjrO+mfvP9azEL7lq/R52dHqN0L8IGeRLVJ0o=; b=vsfU94aKuwu2FFRJOm3pXsUZcBSw3s2QfgZDk3R6DbQpvgZDpkutBNy+VIgqJYzPVk Zcsisio/39hJIEy0X48iYosGnBtBuP0cNYVo2Z8klWPvn7iLADgeK/2hUNjhH7l0UuH+ BlDbvwmbwtoZttGUF2/wzm4qK/W51fqKg57/z+glXN4Qe773Kn4inonBjGUymTGQbF35 5ERKRtLXnA1VClSWUeM1BVX4on91wwSZTxVjAIyOg54O/ocZ+eQS1VBZ5CUjGby+Crt3 +22FvAcbb2EeHYqvkzOFBWd3i8K0ITH+Lkt9KDgcRFIY4g5zpXdjwE3hiQBMbrcDXYKv cG2A== X-Gm-Message-State: AFqh2kpgU01ZyBjGl+hhCKghAxAlp9J+McjaVDILkgHfM2G2+Q1vtonM 0irfsLdVUZwUZEXcuco27FB3BpXesH6sVCMs X-Google-Smtp-Source: AMrXdXvimhApqQ/IWVmRV81/FsuRZiBES4FAMDYlRbQ4eWr8lYJ9vtnaXkN7GliDtNSIL1BHssiVIw== X-Received: by 2002:a05:600c:5022:b0:3c6:e61e:ae8c with SMTP id n34-20020a05600c502200b003c6e61eae8cmr45127208wmr.28.1672937069943; Thu, 05 Jan 2023 08:44:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/34] hw/timer/imx_epit: update interrupt state on CR write access Date: Thu, 5 Jan 2023 16:43:56 +0000 Message-Id: <20230105164417.3994639-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937986938100003 Content-Type: text/plain; charset="utf-8" From: Axel Heider The interrupt state can change due to: - reset clears both SR.OCIF and CR.OCIE - write to CR.EN or CR.OCIE Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index f148868b8cb..7af3a8b10e8 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -206,12 +206,20 @@ static void imx_epit_write(void *opaque, hwaddr offse= t, uint64_t value, if (s->cr & CR_SWR) { /* handle the reset */ imx_epit_reset(DEVICE(s)); - /* - * TODO: could we 'break' here? following operations appear - * to duplicate the work imx_epit_reset() already did. - */ } =20 + /* + * The interrupt state can change due to: + * - reset clears both SR.OCIF and CR.OCIE + * - write to CR.EN or CR.OCIE + */ + imx_epit_update_int(s); + + /* + * TODO: could we 'break' here for reset? following operations app= ear + * to duplicate the work imx_epit_reset() already did. + */ + ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672940193; cv=none; d=zohomail.com; s=zohoarc; b=CAplLzD247RuQGloq1tS3SMf3X9JP2foXcf2pg2T9sU7IzCoMJt9kzc5malIUAc/TIg3lQgqoi4VFU7YhWKqtMx1wC+eEB+2UrVGERR3SrWrX93LB5FNJMSs5HSKuA5nlTykLCfr9fhJ7pfAL4VAhfejR0sK3BJN8Lr6Q2NfE3c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672940193; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P2vsUh1KZZjl1KJb8eEAjrnadXinJSPoXxKJHFfBzmE=; b=HJiCHWNeTyKihDqEbrCxxhK3jgW7OrsLJVQSRqsa4vgLF2gOa89r3b5FiVOLurDt892XZ/PpcHAi40dwkkJIUzg0kjPs9+gI8j80kob0c2jISveaHNaUy7fM/mv78uz2tcE6QjY9ZXlQAS4njv5XvgEZw4jTMl8VMQ28BtkS30k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672940193873385.63049739461655; Thu, 5 Jan 2023 09:36:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMO-0000uC-8Z; Thu, 05 Jan 2023 11:44:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM1-0000a0-K3 for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:33 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM0-0007Ov-0u for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:33 -0500 Received: by mail-wm1-x32d.google.com with SMTP id m8-20020a05600c3b0800b003d96f801c48so1759183wms.0 for ; Thu, 05 Jan 2023 08:44:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=P2vsUh1KZZjl1KJb8eEAjrnadXinJSPoXxKJHFfBzmE=; b=U3kcW9JRoPNBIJ+pD9iACicumyH+81stmcE1sYz6Um0fAJXfwYpCAkAIB7E443GdjL m12TtsG3IWQkFad/4UiWgYFMOa+dC/dG/06X5DRHnVPCdTixrhsXYKruk5CA0RIf7Pr3 1aScrl1bVyY+1UPzDbJfaRAztI4+eq5FtVBy5T5VYRMfz8BdjgnuNP+2SwBiUaE0kiNN fKF5/4NTCmTwFEYL5a9FI/DyCwU+9iqEL1KCNZEBwe3Ld/l6EuWWlRoT3q69UUYEezaw jGIqdtYDOi2HPSNmFIiSJ12aFlyiKxLLdOa6xVf4bienRfVh+Mvy3hhIXNh0zhtbRpoA cv4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672940195758100001 Content-Type: text/plain; charset="utf-8" From: Axel Heider Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 7af3a8b10e8..39f47222d05 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -99,12 +99,14 @@ static void imx_epit_set_freq(IMXEPITState *s) /* * This is called both on hardware (device) reset and software reset. */ -static void imx_epit_reset(DeviceState *dev) +static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset) { - IMXEPITState *s =3D IMX_EPIT(dev); - /* Soft reset doesn't touch some bits; hard reset clears them */ - s->cr &=3D (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); + if (is_hard_reset) { + s->cr =3D 0; + } else { + s->cr &=3D (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); + } s->sr =3D 0; s->lr =3D EPIT_TIMER_MAX; s->cmp =3D 0; @@ -205,7 +207,7 @@ static void imx_epit_write(void *opaque, hwaddr offset,= uint64_t value, s->cr =3D value & 0x03ffffff; if (s->cr & CR_SWR) { /* handle the reset */ - imx_epit_reset(DEVICE(s)); + imx_epit_reset(s, false); } =20 /* @@ -377,12 +379,18 @@ static void imx_epit_realize(DeviceState *dev, Error = **errp) s->timer_cmp =3D ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); } =20 +static void imx_epit_dev_reset(DeviceState *dev) +{ + IMXEPITState *s =3D IMX_EPIT(dev); + imx_epit_reset(s, true); +} + static void imx_epit_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D imx_epit_realize; - dc->reset =3D imx_epit_reset; + dc->reset =3D imx_epit_dev_reset; dc->vmsd =3D &vmstate_imx_timer_epit; dc->desc =3D "i.MX periodic timer"; } --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937416; cv=none; d=zohomail.com; s=zohoarc; b=U6TIcc9exNTDMFSaTYNndq15wfHjQZQ9x5CGsfcOvunYKLIRdx27yLRx+YOBVCQLDxyohgpzniCuA5PrWt62DbQpkmwvtpvSjEbjsWAPdAaOpbTaG7Us1/I7GptloRHkP3a5fzix4J1syEN72MZPgu8C0N4SRerIHKZTZGlN4X8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937416; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8xqm51ez6F8zTWVDgAKbMhiEiLQ8CI6XG2qRGoTrIzY=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8xqm51ez6F8zTWVDgAKbMhiEiLQ8CI6XG2qRGoTrIzY=; b=j7Mu7TqoMZf1Y2rF8XQ2qf/CO0xUezfljd2jk/1Z4jtW4HiGRzf9+BJry361mc3sdP 5JJn8yz24wSPLEhmtSJs+Gdp9nvGWWgmIrrBv6OAuSTzgtP0Ijw1vjd8FwPOV4tVf8M5 QDDu61nS2+J4hfqepkcbkW1eXZMizVjrOLJFvV9jQv5jkpo9OdsAYlJSgwOB4Z1KR+Zt YIj+eKDwKcOxwjLGFsww8KnucdEQs8GZzNXJJWF9m63e2AH/jIN8rUerBrYs9wAiWhZk TBfh8kQXs/ZBIGhQRo+2LwBDbn1JwBviV0Uttjv1KTmei6ASfwmcfejWpfWrCW9DesqF SZRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8xqm51ez6F8zTWVDgAKbMhiEiLQ8CI6XG2qRGoTrIzY=; b=HfGvN3KjrSGl0dIQxnzG+ZDtVa7w1BJQpeYQIglV7xj8P4qhhXfXVy2M+wPgDY6cJx UOoRm/ww7bvlTS90kKIuAE9gHM12buIOF4agWVb83TAFJVM2rSw3hovyadkQ0A2MX6tw ZKN1a/Yf46lR9bJdSnEN2K+LN1SfQXyGfkuLYMPbMY+tjCQmNp7nHUGI0st2f4a6Gdn/ siDTH+Bk4xK7GO0UUBEV8gOrz39RY1CieOjJCgN07Z7Zf05eEsgupXq4L604n4qtFvqP c7i43X8mTugYF0oc+QIHylmTf96EeuREm6nUU4FRcqob3vS47RRCCl+HvmeHDz0mQWGz qjIw== X-Gm-Message-State: AFqh2kouKsbZHLEBnt9nyaiTgBo6QP1ZPYGOCep0u81FcAjxugNvnIQ+ pS2/64N2vfdD6ZPhFA/apdyY+ZY5ps+QSUCt X-Google-Smtp-Source: AMrXdXu0Zeoh8kVad/3wTx6F107rgM9KrX6/geBkflC7d/RQ43rRWkjLKjn+EztDLQ8XH72tzGZpBg== X-Received: by 2002:a05:600c:5399:b0:3d9:c6f5:c63d with SMTP id hg25-20020a05600c539900b003d9c6f5c63dmr5659371wmb.28.1672937071474; Thu, 05 Jan 2023 08:44:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/34] hw/timer/imx_epit: factor out register write handlers Date: Thu, 5 Jan 2023 16:43:58 +0000 Message-Id: <20230105164417.3994639-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937417379100001 Content-Type: text/plain; charset="utf-8" From: Axel Heider Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 215 ++++++++++++++++++++++++-------------------- 1 file changed, 117 insertions(+), 98 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 39f47222d05..e04427542ff 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -191,129 +191,148 @@ static void imx_epit_reload_compare_timer(IMXEPITSt= ate *s) } } =20 +static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) +{ + uint32_t oldcr =3D s->cr; + + s->cr =3D value & 0x03ffffff; + + if (s->cr & CR_SWR) { + /* handle the reset */ + imx_epit_reset(s, false); + } + + /* + * The interrupt state can change due to: + * - reset clears both SR.OCIF and CR.OCIE + * - write to CR.EN or CR.OCIE + */ + imx_epit_update_int(s); + + /* + * TODO: could we 'break' here for reset? following operations appear + * to duplicate the work imx_epit_reset() already did. + */ + + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + + /* Update the frequency. Has been done already in case of a reset. */ + if (!(s->cr & CR_SWR)) { + imx_epit_set_freq(s); + } + + if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { + if (s->cr & CR_ENMOD) { + if (s->cr & CR_RLD) { + ptimer_set_limit(s->timer_reload, s->lr, 1); + ptimer_set_limit(s->timer_cmp, s->lr, 1); + } else { + ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); + ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); + } + } + + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_reload, 0); + if (s->cr & CR_OCIEN) { + ptimer_run(s->timer_cmp, 0); + } else { + ptimer_stop(s->timer_cmp); + } + } else if (!(s->cr & CR_EN)) { + /* stop both timers */ + ptimer_stop(s->timer_reload); + ptimer_stop(s->timer_cmp); + } else if (s->cr & CR_OCIEN) { + if (!(oldcr & CR_OCIEN)) { + imx_epit_reload_compare_timer(s); + ptimer_run(s->timer_cmp, 0); + } + } else { + ptimer_stop(s->timer_cmp); + } + + ptimer_transaction_commit(s->timer_cmp); + ptimer_transaction_commit(s->timer_reload); +} + +static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) +{ + /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ + if (value & SR_OCIF) { + s->sr =3D 0; /* SR.OCIF is the only bit in this register anyway */ + imx_epit_update_int(s); + } +} + +static void imx_epit_write_lr(IMXEPITState *s, uint32_t value) +{ + s->lr =3D value; + + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + if (s->cr & CR_RLD) { + /* Also set the limit if the LRD bit is set */ + /* If IOVW bit is set then set the timer value */ + ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); + ptimer_set_limit(s->timer_cmp, s->lr, 0); + } else if (s->cr & CR_IOVW) { + /* If IOVW bit is set then set the timer value */ + ptimer_set_count(s->timer_reload, s->lr); + } + /* + * Commit the change to s->timer_reload, so it can propagate. Otherwise + * the timer interrupt may not fire properly. The commit must happen + * before calling imx_epit_reload_compare_timer(), which reads + * s->timer_reload internally again. + */ + ptimer_transaction_commit(s->timer_reload); + imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); +} + +static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value) +{ + s->cmp =3D value; + + ptimer_transaction_begin(s->timer_cmp); + imx_epit_reload_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); +} + static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { IMXEPITState *s =3D IMX_EPIT(opaque); - uint64_t oldcr; =20 DPRINTF("(%s, value =3D 0x%08x)\n", imx_epit_reg_name(offset >> 2), (uint32_t)value); =20 switch (offset >> 2) { case 0: /* CR */ - - oldcr =3D s->cr; - s->cr =3D value & 0x03ffffff; - if (s->cr & CR_SWR) { - /* handle the reset */ - imx_epit_reset(s, false); - } - - /* - * The interrupt state can change due to: - * - reset clears both SR.OCIF and CR.OCIE - * - write to CR.EN or CR.OCIE - */ - imx_epit_update_int(s); - - /* - * TODO: could we 'break' here for reset? following operations app= ear - * to duplicate the work imx_epit_reset() already did. - */ - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - - /* Update the frequency. Has been done already in case of a reset.= */ - if (!(s->cr & CR_SWR)) { - imx_epit_set_freq(s); - } - - if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { - if (s->cr & CR_ENMOD) { - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - ptimer_set_limit(s->timer_cmp, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - } - } - - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_reload, 0); - if (s->cr & CR_OCIEN) { - ptimer_run(s->timer_cmp, 0); - } else { - ptimer_stop(s->timer_cmp); - } - } else if (!(s->cr & CR_EN)) { - /* stop both timers */ - ptimer_stop(s->timer_reload); - ptimer_stop(s->timer_cmp); - } else if (s->cr & CR_OCIEN) { - if (!(oldcr & CR_OCIEN)) { - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_cmp, 0); - } - } else { - ptimer_stop(s->timer_cmp); - } - - ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); + imx_epit_write_cr(s, (uint32_t)value); break; =20 - case 1: /* SR - ACK*/ - /* writing 1 to SR.OCIF clears this bit and turns the interrupt of= f */ - if (value & SR_OCIF) { - s->sr =3D 0; /* SR.OCIF is the only bit in this register anywa= y */ - imx_epit_update_int(s); - } + case 1: /* SR */ + imx_epit_write_sr(s, (uint32_t)value); break; =20 - case 2: /* LR - set ticks */ - s->lr =3D value; - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - if (s->cr & CR_RLD) { - /* Also set the limit if the LRD bit is set */ - /* If IOVW bit is set then set the timer value */ - ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); - ptimer_set_limit(s->timer_cmp, s->lr, 0); - } else if (s->cr & CR_IOVW) { - /* If IOVW bit is set then set the timer value */ - ptimer_set_count(s->timer_reload, s->lr); - } - /* - * Commit the change to s->timer_reload, so it can propagate. Othe= rwise - * the timer interrupt may not fire properly. The commit must happ= en - * before calling imx_epit_reload_compare_timer(), which reads - * s->timer_reload internally again. - */ - ptimer_transaction_commit(s->timer_reload); - imx_epit_reload_compare_timer(s); - ptimer_transaction_commit(s->timer_cmp); + case 2: /* LR */ + imx_epit_write_lr(s, (uint32_t)value); break; =20 case 3: /* CMP */ - s->cmp =3D value; - - ptimer_transaction_begin(s->timer_cmp); - imx_epit_reload_compare_timer(s); - ptimer_transaction_commit(s->timer_cmp); - + imx_epit_write_cmp(s, (uint32_t)value); break; =20 default: qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); - break; } } + static void imx_epit_cmp(void *opaque) { IMXEPITState *s =3D IMX_EPIT(opaque); --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937997; cv=none; d=zohomail.com; s=zohoarc; b=Gop1YBTf68sIqcfXELUnlkhgG8AmqV+XkB/cWn8emrnDFwafX8Hlmk0hj8ddiUb4bDuIpWSSytvdzOfMp96TTRbNDS9gbX5jBmO1a4jm8Za+O0n1YCcDXTb4wjKp7KydcQJbCXmV5hb0xY2hhFwEadabFmQJnpTEx9oFGsa6ZpY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937997; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ew4ZuCC9yg58vS2TrdlpWSuLYwEQS/rH4g7G61S6lm4=; b=R4eOEFg/HmwzEAgeS7N1DcQzXHIUM7TLGr07LngVNYJT6b6bNDnR1cZrM/FR9BtByQCCbwwc4dvpmPlA3ThiwL2d0AIqEIgkMgnQ7moC2vlKzCsNdRIY8osP1MRYACzc0fFKEnHlgiIoneCTnLuRQz5YftN8NVlZPbo3yzczpSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937997118396.08861421232416; Thu, 5 Jan 2023 08:59:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTML-0000qn-Du; Thu, 05 Jan 2023 11:44:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM3-0000bw-Ck for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:36 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM1-0007Pb-Kk for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:35 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m3so19555663wmq.0 for ; Thu, 05 Jan 2023 08:44:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ew4ZuCC9yg58vS2TrdlpWSuLYwEQS/rH4g7G61S6lm4=; b=cRVGz2tlUd6kSkrs0sSHiv7DF2yujPfDZvZo+ICl0qxrd6bpJacTaeW6oai9+OxR8r r7GRqo8zbZJ4M3waK8elRZoFIxraEeqFn383Wnrlm69/4pqHMZBR0lUXPryDPCo1Zx4B TSk2QFCo5lM7DQPr4Mwj+Rw4XeXyfRa4SU852/vKI/IUsucCndhIer0+jr8nDl6y4Qn/ sNxUxIH/Dc/N5ZRLqnMLUjNFzS8YBXd/zhqjMWklBvQMFXToWqGcaIUFW8UykZvPrrmZ uOwK8i1WzY8cIXaReOt5QV8O75EI2N5kPysvfBlGz1ALikFtvcvUkO7tao5LqKS5M/cH 6LQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ew4ZuCC9yg58vS2TrdlpWSuLYwEQS/rH4g7G61S6lm4=; b=6KdIpAFLdVUWWnxjJUeW5xZvjB275UJy7OaDuG71wfXwec+864YkP7BonSYH8bJXFO e9BAzX2KcU5Va5hHcdlzfK5PpzVZmObJmJwuYweiGuc8HZZ4/Eai2aABT/4tMmtO9rPx gFiwIk3UtleGN7uhCqx4gxRIkE5DvDflEQgDsCzCwwKVKNdj64O3YJhh6gEQHqutFYbL BM4TK6qziHlBLB0G+JxWsqHm7Q0P50SVImIoy0CYEKkgxGnv3cITDvQeVlFWRZzI63jj 44dLzyAOejjAArErU/71tGgprBMgmmCsPBGuy1yNQlrSWXBoVapue/0wzQIqp7O7bPh+ vocA== X-Gm-Message-State: AFqh2kpbW9EETFlZEQR1kaaUy91NEd8V2INgmJHTe2jjyKODb1QZcUCi TMjt3en8NhCvSUbn1kYQ5I49u54AjUdZNk/J X-Google-Smtp-Source: AMrXdXuPeHJxHeCx8vG0uz/js9DCUhK0L5chzd2qQcJrMKfJXdeSxTdkZcXVqj3Q+x4DoM4kPo27lw== X-Received: by 2002:a05:600c:1d0e:b0:3cf:7c8b:a7c7 with SMTP id l14-20020a05600c1d0e00b003cf7c8ba7c7mr36564875wms.39.1672937072403; Thu, 05 Jan 2023 08:44:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/34] hw/timer/imx_epit: remove explicit fields cnt and freq Date: Thu, 5 Jan 2023 16:43:59 +0000 Message-Id: <20230105164417.3994639-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937999055100003 Content-Type: text/plain; charset="utf-8" From: Axel Heider The CNT register is a read-only register. There is no need to store it's value, it can be calculated on demand. The calculated frequency is needed temporarily only. Note that this is a migration compatibility break for all boards types that use the EPIT peripheral. Signed-off-by: Axel Heider Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_epit.h | 2 - hw/timer/imx_epit.c | 73 ++++++++++++++----------------------- 2 files changed, 28 insertions(+), 47 deletions(-) diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h index 783eaf0c3a6..79aff0cec20 100644 --- a/include/hw/timer/imx_epit.h +++ b/include/hw/timer/imx_epit.h @@ -74,9 +74,7 @@ struct IMXEPITState { uint32_t sr; uint32_t lr; uint32_t cmp; - uint32_t cnt; =20 - uint32_t freq; qemu_irq irq; }; =20 diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index e04427542ff..cf134961650 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -73,27 +73,14 @@ static void imx_epit_update_int(IMXEPITState *s) } } =20 -/* - * Must be called from within a ptimer_transaction_begin/commit block - * for both s->timer_cmp and s->timer_reload. - */ -static void imx_epit_set_freq(IMXEPITState *s) +static uint32_t imx_epit_get_freq(IMXEPITState *s) { - uint32_t clksrc; - uint32_t prescaler; - - clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); - prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS= ); - - s->freq =3D imx_ccm_get_clock_frequency(s->ccm, - imx_epit_clocks[clksrc]) / prescaler; - - DPRINTF("Setting ptimer frequency to %u\n", s->freq); - - if (s->freq) { - ptimer_set_freq(s->timer_reload, s->freq); - ptimer_set_freq(s->timer_cmp, s->freq); - } + uint32_t clksrc =3D extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); + uint32_t prescaler =3D 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRES= CALE_BITS); + uint32_t f_in =3D imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[= clksrc]); + uint32_t freq =3D f_in / prescaler; + DPRINTF("ptimer frequency is %u\n", freq); + return freq; } =20 /* @@ -110,32 +97,23 @@ static void imx_epit_reset(IMXEPITState *s, bool is_ha= rd_reset) s->sr =3D 0; s->lr =3D EPIT_TIMER_MAX; s->cmp =3D 0; - s->cnt =3D 0; ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); - /* stop both timers */ + + /* + * The reset switches off the input clock, so even if the CR.EN is sti= ll + * set, the timers are no longer running. + */ + assert(imx_epit_get_freq(s) =3D=3D 0); ptimer_stop(s->timer_cmp); ptimer_stop(s->timer_reload); - /* compute new frequency */ - imx_epit_set_freq(s); /* init both timers to EPIT_TIMER_MAX */ ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - if (s->freq && (s->cr & CR_EN)) { - /* if the timer is still enabled, restart it */ - ptimer_run(s->timer_reload, 0); - } ptimer_transaction_commit(s->timer_cmp); ptimer_transaction_commit(s->timer_reload); } =20 -static uint32_t imx_epit_update_count(IMXEPITState *s) -{ - s->cnt =3D ptimer_get_count(s->timer_reload); - - return s->cnt; -} - static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) { IMXEPITState *s =3D IMX_EPIT(opaque); @@ -159,8 +137,7 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offs= et, unsigned size) break; =20 case 4: /* CNT */ - imx_epit_update_count(s); - reg_value =3D s->cnt; + reg_value =3D ptimer_get_count(s->timer_reload); break; =20 default: @@ -179,7 +156,7 @@ static void imx_epit_reload_compare_timer(IMXEPITState = *s) { if ((s->cr & (CR_EN | CR_OCIEN)) =3D=3D (CR_EN | CR_OCIEN)) { /* if the compare feature is on and timers are running */ - uint32_t tmp =3D imx_epit_update_count(s); + uint32_t tmp =3D ptimer_get_count(s->timer_reload); uint64_t next; if (tmp > s->cmp) { /* It'll fire in this round of the timer */ @@ -193,6 +170,7 @@ static void imx_epit_reload_compare_timer(IMXEPITState = *s) =20 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { + uint32_t freq =3D 0; uint32_t oldcr =3D s->cr; =20 s->cr =3D value & 0x03ffffff; @@ -217,12 +195,19 @@ static void imx_epit_write_cr(IMXEPITState *s, uint32= _t value) ptimer_transaction_begin(s->timer_cmp); ptimer_transaction_begin(s->timer_reload); =20 - /* Update the frequency. Has been done already in case of a reset. */ + /* + * Update the frequency. In case of a reset the input clock was + * switched off, so this can be skipped. + */ if (!(s->cr & CR_SWR)) { - imx_epit_set_freq(s); + freq =3D imx_epit_get_freq(s); + if (freq) { + ptimer_set_freq(s->timer_reload, freq); + ptimer_set_freq(s->timer_cmp, freq); + } } =20 - if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { + if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { if (s->cr & CR_ENMOD) { if (s->cr & CR_RLD) { ptimer_set_limit(s->timer_reload, s->lr, 1); @@ -356,15 +341,13 @@ static const MemoryRegionOps imx_epit_ops =3D { =20 static const VMStateDescription vmstate_imx_timer_epit =3D { .name =3D TYPE_IMX_EPIT, - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (VMStateField[]) { VMSTATE_UINT32(cr, IMXEPITState), VMSTATE_UINT32(sr, IMXEPITState), VMSTATE_UINT32(lr, IMXEPITState), VMSTATE_UINT32(cmp, IMXEPITState), - VMSTATE_UINT32(cnt, IMXEPITState), - VMSTATE_UINT32(freq, IMXEPITState), VMSTATE_PTIMER(timer_reload, IMXEPITState), VMSTATE_PTIMER(timer_cmp, IMXEPITState), VMSTATE_END_OF_LIST() --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937932; cv=none; d=zohomail.com; s=zohoarc; b=Nm7tKdGePEyp6jcauHAPo+o29XpFl7eqzGVQhk37SbKUUax0onfIkZEFgaUKucsJRAws7LCWhnrAjIFoHbfy0dPKNtvAEtdAVMi0DEUtiocs1e92jqTDxvevn+rLy61/iHd/ZJhEOJQljMlnSd2Ta8RFNEpGc9K0/vaDce9NoU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937932; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v5vPLrOJerSouBci4jbMD3472GqmuD+aNRfNrDgOb8Y=; b=EgBHCcwnB4xq0je0A/N5kGlHeNEscdKlrbbDZT4r3LpRKjNYikFJH+4WMNkuHYU02Zergow6T8F7g/+ZKz5gamlkL5QEpq9JjfTh9quVnRC1R0/i2T9PF6uMGLXVnoaykuPXmAMAgY/vKIAS9cnqP1qw/C+RZIBMYThb2p04vj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937932780328.6810140697046; Thu, 5 Jan 2023 08:58:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTML-0000qm-F3; Thu, 05 Jan 2023 11:44:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM4-0000c3-H7 for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:36 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM2-0007Q6-Go for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:36 -0500 Received: by mail-wm1-x32c.google.com with SMTP id o15so28448996wmr.4 for ; Thu, 05 Jan 2023 08:44:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=v5vPLrOJerSouBci4jbMD3472GqmuD+aNRfNrDgOb8Y=; b=y3Sh5nuyHPjFBGOU7+t84fL56vXA61w2dFp8rLYnQVA82R2JGKbMzVlIW4oZlU+Ew3 j5f2L4Q7mnjZH61YA5OC67Fdu5ULBsvkS5TYhhyfgY9HcrEOVOP+d6PGxB+zue4EBAeP iKj4S+pvAyRWLGLgglGtwbt00IOaRLs++Dt/xtnfh7Uskv0HAVMJEC4FHAQHKHHorE// wojRxMsAVheRozIrpI3FFPYiN3kT0A8lmk2cQShZCJ1xqTp6oUlHM9mv6S6DiGyAt0VJ S7G80++Q4Pi+YogyHFMkknDhE9AbayBXBoIwV59MvL8iiZ0vpLLBK5huyEXzfpT6ZtHt BnyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v5vPLrOJerSouBci4jbMD3472GqmuD+aNRfNrDgOb8Y=; b=oZYPwT34qyXWBfUHzDqoFAkZJhzumrme/kR7THIX7xlGjP0nUSkafq6KjQhlBXyr+7 mqdF/GxRZ28hIHVlOEpC6xRlIXMNu/C4EJZwR8CA/xFI5u2JVnHzS7Vkftl3pZLSm8pB EElh4xVU0tPcYsg5I6X7vmYciI69X9kmYBzSAKUi6tUN9mr5UPE1N3BAiC8CbKbuPJDU y+54yRnsV3sNvIW1qX1nfmeIVNTxwzkHNNEej+bH0/1SiurUgsL7g5OyRi2DMLbQoF2O OFU0aZ3yX35t1+ZYkehxA7zDfadM21v8TQlJDTz2vvHSlm9oRMep5mG0hZxUJXgswh+N 0ZSQ== X-Gm-Message-State: AFqh2kqR2u4fpnRBmQoJ31JRMewAuFQZ/ISc+2paFZzdJ4GwNh7/ANKI kfpM13B0+mVlOYQ8gfgdDfsrJVmsqWLUH2kZ X-Google-Smtp-Source: AMrXdXvAtkhHK52id369by/Z9ibwYLZo00Hf8MegVkOoxTDZFR0erdcnmLiewGwd517nown6RLDXfw== X-Received: by 2002:a1c:790a:0:b0:3d6:b691:b814 with SMTP id l10-20020a1c790a000000b003d6b691b814mr36437655wme.1.1672937073171; Thu, 05 Jan 2023 08:44:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/34] hw/timer/imx_epit: fix compare timer handling Date: Thu, 5 Jan 2023 16:44:00 +0000 Message-Id: <20230105164417.3994639-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937934667100003 Content-Type: text/plain; charset="utf-8" From: Axel Heider - fix #1263 for CR writes - rework compare time handling - The compare timer has to run even if CR.OCIEN is not set, as SR.OCIF must be updated. - The compare timer fires exactly once when the compare value is less than the current value, but the reload values is less than the compare value. - The compare timer will never fire if the reload value is less than the compare value. Disable it in this case. Signed-off-by: Axel Heider [PMM: fixed minor style nits] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/imx_epit.c | 192 ++++++++++++++++++++++++++------------------ 1 file changed, 116 insertions(+), 76 deletions(-) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index cf134961650..3a869782bcd 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -6,6 +6,7 @@ * Originally written by Hans Jiang * Updated by Peter Chubb * Updated by Jean-Christophe Dubois + * Updated by Axel Heider * * This code is licensed under GPL version 2 or later. See * the COPYING file in the top-level directory. @@ -151,33 +152,126 @@ static uint64_t imx_epit_read(void *opaque, hwaddr o= ffset, unsigned size) return reg_value; } =20 -/* Must be called from ptimer_transaction_begin/commit block for s->timer_= cmp */ -static void imx_epit_reload_compare_timer(IMXEPITState *s) +/* + * Must be called from a ptimer_transaction_begin/commit block for + * s->timer_cmp, but outside of a transaction block of s->timer_reload, + * so the proper counter value is read. + */ +static void imx_epit_update_compare_timer(IMXEPITState *s) { - if ((s->cr & (CR_EN | CR_OCIEN)) =3D=3D (CR_EN | CR_OCIEN)) { - /* if the compare feature is on and timers are running */ - uint32_t tmp =3D ptimer_get_count(s->timer_reload); - uint64_t next; - if (tmp > s->cmp) { - /* It'll fire in this round of the timer */ - next =3D tmp - s->cmp; - } else { /* catch it next time around */ - next =3D tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s= ->lr); + uint64_t counter =3D 0; + bool is_oneshot =3D false; + /* + * The compare timer only has to run if the timer peripheral is active + * and there is an input clock, Otherwise it can be switched off. + */ + bool is_active =3D (s->cr & CR_EN) && imx_epit_get_freq(s); + if (is_active) { + /* + * Calculate next timeout for compare timer. Reading the reload + * counter returns proper results only if pending transactions + * on it are committed here. Otherwise stale values are be read. + */ + counter =3D ptimer_get_count(s->timer_reload); + uint64_t limit =3D ptimer_get_limit(s->timer_cmp); + /* + * The compare timer is a periodic timer if the limit is at least + * the compare value. Otherwise it may fire at most once in the + * current round. + */ + bool is_oneshot =3D (limit >=3D s->cmp); + if (counter >=3D s->cmp) { + /* The compare timer fires in the current round. */ + counter -=3D s->cmp; + } else if (!is_oneshot) { + /* + * The compare timer fires after a reload, as it is below the + * compare value already in this round. Note that the counter + * value calculated below can be above the 32-bit limit, which + * is legal here because the compare timer is an internal + * helper ptimer only. + */ + counter +=3D limit - s->cmp; + } else { + /* + * The compare timer won't fire in this round, and the limit is + * set to a value below the compare value. This practically me= ans + * it will never fire, so it can be switched off. + */ + is_active =3D false; } - ptimer_set_count(s->timer_cmp, next); } + + /* + * Set the compare timer and let it run, or stop it. This is agnostic + * of CR.OCIEN bit, as this bit affects interrupt generation only. The + * compare timer needs to run even if no interrupts are to be generate= d, + * because the SR.OCIF bit must be updated also. + * Note that the timer might already be stopped or be running with + * counter values. However, finding out when an update is needed and + * when not is not trivial. It's much easier applying the setting agai= n, + * as this does not harm either and the overhead is negligible. + */ + if (is_active) { + ptimer_set_count(s->timer_cmp, counter); + ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0); + } else { + ptimer_stop(s->timer_cmp); + } + } =20 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) { - uint32_t freq =3D 0; uint32_t oldcr =3D s->cr; =20 s->cr =3D value & 0x03ffffff; =20 if (s->cr & CR_SWR) { - /* handle the reset */ + /* + * Reset clears CR.SWR again. It does not touch CR.EN, but the tim= ers + * are still stopped because the input clock is disabled. + */ imx_epit_reset(s, false); + } else { + uint32_t freq; + uint32_t toggled_cr_bits =3D oldcr ^ s->cr; + /* re-initialize the limits if CR.RLD has changed */ + bool set_limit =3D toggled_cr_bits & CR_RLD; + /* set the counter if the timer got just enabled and CR.ENMOD is s= et */ + bool is_switched_on =3D (toggled_cr_bits & s->cr) & CR_EN; + bool set_counter =3D is_switched_on && (s->cr & CR_ENMOD); + + ptimer_transaction_begin(s->timer_cmp); + ptimer_transaction_begin(s->timer_reload); + freq =3D imx_epit_get_freq(s); + if (freq) { + ptimer_set_freq(s->timer_reload, freq); + ptimer_set_freq(s->timer_cmp, freq); + } + + if (set_limit || set_counter) { + uint64_t limit =3D (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX; + ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0); + if (set_limit) { + ptimer_set_limit(s->timer_cmp, limit, 0); + } + } + /* + * If there is an input clock and the peripheral is enabled, then + * ensure the wall clock timer is ticking. Otherwise stop the time= rs. + * The compare timer will be updated later. + */ + if (freq && (s->cr & CR_EN)) { + ptimer_run(s->timer_reload, 0); + } else { + ptimer_stop(s->timer_reload); + } + /* Commit changes to reload timer, so they can propagate. */ + ptimer_transaction_commit(s->timer_reload); + /* Update compare timer based on the committed reload timer value.= */ + imx_epit_update_compare_timer(s); + ptimer_transaction_commit(s->timer_cmp); } =20 /* @@ -186,60 +280,6 @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_= t value) * - write to CR.EN or CR.OCIE */ imx_epit_update_int(s); - - /* - * TODO: could we 'break' here for reset? following operations appear - * to duplicate the work imx_epit_reset() already did. - */ - - ptimer_transaction_begin(s->timer_cmp); - ptimer_transaction_begin(s->timer_reload); - - /* - * Update the frequency. In case of a reset the input clock was - * switched off, so this can be skipped. - */ - if (!(s->cr & CR_SWR)) { - freq =3D imx_epit_get_freq(s); - if (freq) { - ptimer_set_freq(s->timer_reload, freq); - ptimer_set_freq(s->timer_cmp, freq); - } - } - - if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { - if (s->cr & CR_ENMOD) { - if (s->cr & CR_RLD) { - ptimer_set_limit(s->timer_reload, s->lr, 1); - ptimer_set_limit(s->timer_cmp, s->lr, 1); - } else { - ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); - ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); - } - } - - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_reload, 0); - if (s->cr & CR_OCIEN) { - ptimer_run(s->timer_cmp, 0); - } else { - ptimer_stop(s->timer_cmp); - } - } else if (!(s->cr & CR_EN)) { - /* stop both timers */ - ptimer_stop(s->timer_reload); - ptimer_stop(s->timer_cmp); - } else if (s->cr & CR_OCIEN) { - if (!(oldcr & CR_OCIEN)) { - imx_epit_reload_compare_timer(s); - ptimer_run(s->timer_cmp, 0); - } - } else { - ptimer_stop(s->timer_cmp); - } - - ptimer_transaction_commit(s->timer_cmp); - ptimer_transaction_commit(s->timer_reload); } =20 static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) @@ -266,14 +306,10 @@ static void imx_epit_write_lr(IMXEPITState *s, uint32= _t value) /* If IOVW bit is set then set the timer value */ ptimer_set_count(s->timer_reload, s->lr); } - /* - * Commit the change to s->timer_reload, so it can propagate. Otherwise - * the timer interrupt may not fire properly. The commit must happen - * before calling imx_epit_reload_compare_timer(), which reads - * s->timer_reload internally again. - */ + /* Commit the changes to s->timer_reload, so they can propagate. */ ptimer_transaction_commit(s->timer_reload); - imx_epit_reload_compare_timer(s); + /* Update the compare timer based on the committed reload timer value.= */ + imx_epit_update_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); } =20 @@ -281,8 +317,9 @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_= t value) { s->cmp =3D value; =20 + /* Update the compare timer based on the committed reload timer value.= */ ptimer_transaction_begin(s->timer_cmp); - imx_epit_reload_compare_timer(s); + imx_epit_update_compare_timer(s); ptimer_transaction_commit(s->timer_cmp); } =20 @@ -322,6 +359,9 @@ static void imx_epit_cmp(void *opaque) { IMXEPITState *s =3D IMX_EPIT(opaque); =20 + /* The cmp ptimer can't be running when the peripheral is disabled */ + assert(s->cr & CR_EN); + DPRINTF("sr was %d\n", s->sr); /* Set interrupt status bit SR.OCIF and update the interrupt state */ s->sr |=3D SR_OCIF; --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937839; cv=none; d=zohomail.com; s=zohoarc; b=c/HEDW1HqXOTXN9MG0L9/kWsyyymrbztzOLmj3o907iUlvSvhabCzPIjlUWnjX5HQy0EB6/bJXZGV2TPgyHaVPrC8LwCRM9Znmj9zNByvaW/Ah8S0e7KnMyzNQRpiFrtRFATvmLY0sxmk2FeVKEa1+YnZ1pAJYtIA4V+UJuxAQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937839; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Iv7iewiQXPKui2BoDF1siilf+8tNwWAMXxG4GDV6wp8=; b=Fu4jCf8eFkKMqdhE8RbhVVkwAKcikJGYl30YSPuC6fLwoyScPTwE4eWtwtssk2BKhxH6V0T2SfgywoBl+M1VyhXf+klEviKHkRXEv/acMo/xlwcFECPvD/ioQW8gf5EEBtudnFOPR9RyZ/CYJvubmmQvcdMjguZtbAIEABum7cA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937839185332.18554610616445; Thu, 5 Jan 2023 08:57:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTNp-00021R-NJ; Thu, 05 Jan 2023 11:46:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM7-0000gw-SV for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:41 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM3-0007NS-8U for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:39 -0500 Received: by mail-wm1-x32a.google.com with SMTP id ay40so28487158wmb.2 for ; Thu, 05 Jan 2023 08:44:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937841578100007 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Fix these: WARNING: Block comments use a leading /* on a separate line WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck Message-id: 20221213190537.511-2-farosas@suse.de Signed-off-by: Peter Maydell --- target/arm/helper.c | 323 +++++++++++++++++++++++++++++--------------- 1 file changed, 215 insertions(+), 108 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b13f6ff328c..a5f96ab77dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -83,7 +83,8 @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPReg= Info *ri) static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v) { - /* Raw write of a coprocessor register (as needed for migration, etc). + /* + * Raw write of a coprocessor register (as needed for migration, etc). * Note that constant registers are treated as write-ignored; the * caller should check for success by whether a readback gives the * value written. @@ -101,7 +102,8 @@ static void write_raw_cp_reg(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { - /* Return true if the regdef would cause an assertion if you called + /* + * Return true if the regdef would cause an assertion if you called * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a * program bug for it not to have the NO_RAW flag). * NB that returning false here doesn't necessarily mean that calling @@ -184,7 +186,8 @@ bool write_list_to_cpustate(ARMCPU *cpu) if (ri->type & ARM_CP_NO_RAW) { continue; } - /* Write value and confirm it reads back as written + /* + * Write value and confirm it reads back as written * (to catch read-only registers and partially read-only * registers where the incoming migration value doesn't match) */ @@ -237,7 +240,8 @@ static gint cpreg_key_compare(gconstpointer a, gconstpo= inter b) =20 void init_cpreg_list(ARMCPU *cpu) { - /* Initialise the cpreg_tuples[] array based on the cp_regs hash. + /* + * Initialise the cpreg_tuples[] array based on the cp_regs hash. * Note that we require cpreg_tuples[] to be sorted by key ID. */ GList *keys; @@ -279,7 +283,8 @@ static CPAccessResult access_el3_aa32ns(CPUARMState *en= v, return CP_ACCESS_OK; } =20 -/* Some secure-only AArch32 registers trap to EL3 if used from +/* + * Some secure-only AArch32 registers trap to EL3 if used from * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). * Note that an access from Secure EL1 can only happen if EL3 is AArch64. * We assume that the .access field is set to PL1_RW. @@ -301,7 +306,8 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState= *env, return CP_ACCESS_TRAP_UNCATEGORIZED; } =20 -/* Check for traps to performance monitor registers, which are controlled +/* + * Check for traps to performance monitor registers, which are controlled * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. */ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, @@ -399,7 +405,8 @@ static void fcse_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value) { - /* Unlike real hardware the qemu TLB uses virtual addresses, + /* + * Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ tlb_flush(CPU(cpu)); @@ -414,7 +421,8 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, =20 if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table + /* + * For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ @@ -606,7 +614,8 @@ static void tlbiipas2is_hyp_write(CPUARMState *env, con= st ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo cp_reginfo[] =3D { - /* Define the secure and non-secure FCSE identifier CP registers + /* + * Define the secure and non-secure FCSE identifier CP registers * separately because there is no secure bank in V8 (no _EL3). This a= llows * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. @@ -621,7 +630,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - /* Define the secure and non-secure context identifier CP registers + /* + * Define the secure and non-secure context identifier CP registers * separately because there is no secure bank in V8 (no _EL3). This a= llows * the secure register to be properly reset and migrated. In the * non-secure case, the 32-bit register will have reset and migration @@ -642,7 +652,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { - /* NB: Some of these registers exist in v8 but with more precise + /* + * NB: Some of these registers exist in v8 but with more precise * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). */ /* MMU Domain access control / MPU write buffer control */ @@ -652,7 +663,8 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. + /* + * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. * For v6 and v5, these mappings are overly broad. */ { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, @@ -670,7 +682,8 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { - /* Not all pre-v6 cores implemented this WFI, so this is slightly + /* + * Not all pre-v6 cores implemented this WFI, so this is slightly * over-broad. */ { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, @@ -678,12 +691,14 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { - /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which + /* + * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which * is UNPREDICTABLE; we choose to NOP as most implementations do). */ { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, .access =3D PL1_W, .type =3D ARM_CP_WFI }, - /* L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice + /* + * L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd * OMAPCP will override this space. */ @@ -697,14 +712,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D 0 }, - /* We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; + /* + * We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; * implementing it as RAZ means the "debug architecture version" bits * will read as a reserved value, which should cause Linux to not try * to use the debug hardware. */ { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MMU TLB control. Note that the wildcarding means we cover not just + /* + * MMU TLB control. Note that the wildcarding means we cover not just * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. */ { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, @@ -732,7 +749,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, =20 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ if (!arm_feature(env, ARM_FEATURE_V8)) { - /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. + /* + * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ @@ -748,7 +766,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, value |=3D R_CPACR_ASEDIS_MASK; } =20 - /* VFPv3 and upwards with NEON implement 32 double precision + /* + * VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { @@ -790,7 +809,8 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMC= PRegInfo *ri) =20 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - /* Call cpacr_write() so that we reset with the correct RAO bits set + /* + * Call cpacr_write() so that we reset with the correct RAO bits set * for our CPU features. */ cpacr_write(env, ri, 0); @@ -831,7 +851,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "MVA_prefetch", .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* We need to break the TB after ISB to execute self-modifying code + /* + * We need to break the TB after ISB to execute self-modifying code * correctly and also to take any pending interrupts immediately. * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. */ @@ -846,7 +867,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue =3D 0, }, - /* Watchpoint Fault Address Register : should actually only be present + /* + * Watchpoint Fault Address Register : should actually only be present * for 1136, 1176, 11MPCore. */ { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, @@ -1051,7 +1073,8 @@ static bool event_supported(uint16_t number) static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { - /* Performance monitor registers user accessibility is controlled + /* + * Performance monitor registers user accessibility is controlled * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable * trapping to EL2 or EL3 for other accesses. */ @@ -1139,7 +1162,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) =20 -/* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing +/* + * Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing * the current EL, security state, and register configuration. */ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) @@ -1503,7 +1527,8 @@ static uint64_t pmccntr_read(CPUARMState *env, const = ARMCPRegInfo *ri) static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and + /* + * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are * accessed. @@ -1614,7 +1639,8 @@ static void pmevtyper_write(CPUARMState *env, const A= RMCPRegInfo *ri, env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; pmevcntr_op_finish(env, counter); } - /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when + /* + * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when * PMSELR value is equal to or greater than the number of implemented * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. */ @@ -1715,8 +1741,10 @@ static uint64_t pmevcntr_read(CPUARMState *env, cons= t ARMCPRegInfo *ri, } return ret; } else { - /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR - * are CONSTRAINED UNPREDICTABLE. */ + /* + * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. + */ return 0; } } @@ -1791,7 +1819,8 @@ static void pmintenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Note that even though the AArch64 view of this register has bits + /* + * Note that even though the AArch64 view of this register has bits * [10:0] all RES0 we can only mask the bottom 5, to comply with the * architectural requirements for bits which are RES0 only in some * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 @@ -1854,7 +1883,8 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (!arm_feature(env, ARM_FEATURE_EL2)) { valid_mask &=3D ~SCR_HCE; =20 - /* On ARMv7, SMD (or SCD as it is called in v7) is only + /* + * On ARMv7, SMD (or SCD as it is called in v7) is only * supported if EL2 exists. The bit is UNK/SBZP when * EL2 is unavailable. In QEMU ARMv7, we force it to always zero * when EL2 is unavailable. @@ -1911,7 +1941,8 @@ static uint64_t ccsidr_read(CPUARMState *env, const A= RMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 - /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + /* + * Acquire the CSSELR index from the bank corresponding to the CCSIDR * bank */ uint32_t index =3D A32_BANKED_REG_GET(env, csselr, @@ -1986,7 +2017,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* Performance monitors are implementation defined in v7, + /* + * Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we * follow. * @@ -2140,7 +2172,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, - /* Auxiliary ID register: this actually has an IMPDEF value but for now + /* + * Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */ { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, @@ -2148,7 +2181,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid1, .resetvalue =3D 0 }, - /* Auxiliary fault status registers: these also are IMPDEF, and we + /* + * Auxiliary fault status registers: these also are IMPDEF, and we * choose to RAZ/WI for all cores. */ { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -2159,7 +2193,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MAIR can just read-as-written because we don't implement caches + /* + * MAIR can just read-as-written because we don't implement caches * and so don't need to care about memory attributes. */ { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -2171,10 +2206,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), .resetvalue =3D 0 }, - /* For non-long-descriptor page tables these are PRRR and NMRR; + /* + * For non-long-descriptor page tables these are PRRR and NMRR; * regardless they still act as reads-as-written for QEMU. */ - /* MAIR0/1 are defined separately from their 64-bit counterpart which + /* + * MAIR0/1 are defined separately from their 64-bit counterpart which * allows them to assign the correct fieldoffset based on the endiann= ess * handled in the field definitions. */ @@ -2337,7 +2374,8 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { - /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. + /* + * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. * Writable only at the highest implemented exception level. */ int el =3D arm_current_el(env); @@ -2496,7 +2534,8 @@ static CPAccessResult gt_stimer_access(CPUARMState *e= nv, const ARMCPRegInfo *ri, bool isread) { - /* The AArch64 register view of the secure physical timer is + /* + * The AArch64 register view of the secure physical timer is * always accessible from EL3, and configurably accessible from * Secure EL1. */ @@ -2531,7 +2570,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; =20 if (gt->ctl & 1) { - /* Timer enabled: calculate and set current ISTATUS, irq, and + /* + * Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? @@ -2554,7 +2594,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) /* Next transition is when we hit cval */ nexttick =3D gt->cval + offset; } - /* Note that the desired next expiry time might be beyond the + /* + * Note that the desired next expiry time might be beyond the * signed-64-bit range of a QEMUTimer -- in this case we just * set the timer for as far in the future as possible. When the * timer expires we will reset the timer for any remaining period. @@ -2671,7 +2712,8 @@ static void gt_ctl_write(CPUARMState *env, const ARMC= PRegInfo *ri, /* Enable toggled */ gt_recalc_timer(cpu, timeridx); } else if ((oldval ^ value) & 2) { - /* IMASK toggled: don't need to recalculate, + /* + * IMASK toggled: don't need to recalculate, * just set the interrupt line based on ISTATUS */ int irqstate =3D (oldval & 4) && !(value & 2); @@ -2982,7 +3024,8 @@ static void arm_gt_cntfrq_reset(CPUARMState *env, con= st ARMCPRegInfo *opaque) } =20 static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - /* Note that CNTFRQ is purely reads-as-written for the benefit + /* + * Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. * Our reset value matches the fixed frequency we implement the timer = at. */ @@ -3145,7 +3188,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, - /* Secure timer -- this is actually restricted to only EL3 + /* + * Secure timer -- this is actually restricted to only EL3 * and configurably Secure-EL1 via the accessfn. */ { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3184,7 +3228,8 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #else =20 -/* In user-mode most of the generic timer registers are inaccessible +/* + * In user-mode most of the generic timer registers are inaccessible * however modern kernels (4.12+) allow access to cntvct_el0 */ =20 @@ -3192,7 +3237,8 @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 - /* Currently we have no support for QEMUTimer in linux-user so we + /* + * Currently we have no support for QEMUTimer in linux-user so we * can't call gt_get_countervalue(env), instead we directly * call the lower level functions. */ @@ -3233,7 +3279,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, bool isread) { if (ri->opc2 & 4) { - /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in + /* + * The ATS12NSO* operations must trap to EL3 or EL2 if executed in * Secure EL1 (which can only happen if EL3 is AArch64). * They are simply UNDEF if executed from NS EL1. * They function normally from EL2 or EL3. @@ -3394,7 +3441,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, } } } else { - /* fsr is a DFSR/IFSR value for the short descriptor + /* + * fsr is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). * Convert it to a 32-bit PAR. */ @@ -3899,7 +3947,8 @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { - /* Reset for all these registers is handled in arm_cpu_reset(), + /* + * Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do * not register cpregs but still need the state to be reset. */ @@ -4000,7 +4049,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, } =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID + /* + * With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); @@ -4117,7 +4167,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, }; =20 -/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing +/* + * Note that unlike TTBCR, writing to TTBCR2 does not require flushing * qemu tlbs nor adjusting cached masks. */ static const ARMCPRegInfo ttbcr2_reginfo =3D { @@ -4155,7 +4206,8 @@ static void omap_wfi_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* On OMAP there are registers indicating the max/min index of dcache = lines + /* + * On OMAP there are registers indicating the max/min index of dcache = lines * containing a dirty line; cache flush operations have to reset these. */ env->cp15.c15_i_max =3D 0x000; @@ -4187,7 +4239,8 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, - /* TODO: Peripheral port remap register: + /* + * TODO: Peripheral port remap register: * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), * when MMU is off. @@ -4216,7 +4269,8 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), .resetvalue =3D 0, }, - /* XScale specific cache-lockdown: since we have no cache we NOP these + /* + * XScale specific cache-lockdown: since we have no cache we NOP these * and hope the guest does not really rely on cache behaviour. */ { .name =3D "XSCALE_LOCK_ICACHE_LINE", @@ -4234,7 +4288,8 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { - /* RAZ/WI the whole crn=3D15 space, when we don't have a more specific + /* + * RAZ/WI the whole crn=3D15 space, when we don't have a more specific * implementation of this implementation-defined space. * Ideally this should eventually disappear in favour of actually * implementing the correct behaviour for all cores. @@ -4274,7 +4329,8 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[= ] =3D { }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { - /* The cache test-and-clean instructions always return (1 << 30) + /* + * The cache test-and-clean instructions always return (1 << 30) * to indicate that there are no dirty cache lines. */ { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, @@ -4310,7 +4366,8 @@ static uint64_t mpidr_read_val(CPUARMState *env) =20 if (arm_feature(env, ARM_FEATURE_V7MP)) { mpidr |=3D (1U << 31); - /* Cores which are uniprocessor (non-coherent) + /* + * Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set * bit 30. (For instance, Cortex-R5). */ @@ -4522,7 +4579,8 @@ static CPAccessResult access_tocu(CPUARMState *env, c= onst ARMCPRegInfo *ri, return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); } =20 -/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions +/* + * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ =20 @@ -4655,7 +4713,8 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL2 + /* + * Invalidate by VA, EL2 * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ @@ -4669,7 +4728,8 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL3 + /* + * Invalidate by VA, EL3 * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ @@ -4694,7 +4754,8 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL1&0 (AArch64 version). + /* + * Invalidate by VA, EL1&0 (AArch64 version). * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. @@ -5015,7 +5076,8 @@ static CPAccessResult sp_el0_access(CPUARMState *env,= const ARMCPRegInfo *ri, bool isread) { if (!(env->pstate & PSTATE_SP)) { - /* Access to SP_EL0 is undefined if it's being used as + /* + * Access to SP_EL0 is undefined if it's being used as * the stack pointer. */ return CP_ACCESS_TRAP_UNCATEGORIZED; @@ -5055,7 +5117,8 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } =20 if (raw_read(env, ri) =3D=3D value) { - /* Skip the TLB flush if nothing actually changed; Linux likes + /* + * Skip the TLB flush if nothing actually changed; Linux likes * to do a lot of pointless SCTLR writes. */ return; @@ -5123,7 +5186,8 @@ static void mdcr_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, } =20 static const ARMCPRegInfo v8_cp_reginfo[] =3D { - /* Minimal set of EL0-visible registers. This will need to be expanded + /* + * Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. */ { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, @@ -5406,7 +5470,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, - /* We rely on the access checks not allowing the guest to write to the + /* + * We rely on the access checks not allowing the guest to write to the * state field when SPSel indicates that it's being used as the stack * pointer. */ @@ -5484,7 +5549,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; } else if (cpu->psci_conduit !=3D QEMU_PSCI_CONDUIT_SMC) { - /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. + /* + * Architecturally HCR.TSC is RES0 if EL3 is not implemented. * However, if we're using the SMC PSCI conduit then QEMU is * effectively acting like EL3 firmware and so the guest at * EL2 should retain the ability to prevent EL1 from being @@ -5914,7 +5980,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY - /* Unlike the other EL2-related AT operations, these must + /* + * Unlike the other EL2-related AT operations, these must * UNDEF from EL3 if EL2 is not implemented, which is why we * define them here rather than with the rest of the AT ops. */ @@ -5928,7 +5995,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_W, .accessfn =3D at_s1e2_access, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, .writefn =3D ats_write64 }, - /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + /* + * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se * to behave as if SCR.NS was 1. @@ -5941,7 +6009,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the + /* + * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the * reset values as IMPDEF. We choose to reset to 3 to comply with * both ARMv7 and ARMv8. */ @@ -6024,7 +6093,8 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { - /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. + /* + * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. * At Secure EL1 it traps to EL3 or EL2. */ if (arm_current_el(env) =3D=3D 3) { @@ -6828,7 +6898,8 @@ static void define_pmu_regs(ARMCPU *cpu) } } =20 -/* We don't know until after realize whether there's a GICv3 +/* + * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 * at runtime. @@ -6857,7 +6928,8 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) } #endif =20 -/* Shared logic between LORID and the rest of the LOR* registers. +/* + * Shared logic between LORID and the rest of the LOR* registers. * Secure state exclusion has already been dealt with. */ static CPAccessResult access_lor_ns(CPUARMState *env, @@ -7684,7 +7756,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 define_arm_cp_regs(cpu, cp_reginfo); if (!arm_feature(env, ARM_FEATURE_V8)) { - /* Must go early as it is full of wildcards that may be + /* + * Must go early as it is full of wildcards that may be * overridden by later definitions. */ define_arm_cp_regs(cpu, not_v8_cp_reginfo); @@ -7698,7 +7771,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_pfr0 }, - /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know + /* + * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. */ { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, @@ -8239,7 +8313,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 define_arm_cp_regs(cpu, el3_regs); } - /* The behaviour of NSACR is sufficiently various that we don't + /* + * The behaviour of NSACR is sufficiently various that we don't * try to describe it in a single reginfo: * if EL3 is 64 bit, then trap to EL3 from S EL1, * reads as constant 0xc00 from NS EL1 and NS EL2 @@ -8331,13 +8406,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } - /* Slightly awkwardly, the OMAP and StrongARM cores need all of + /* + * Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld * be read-only (ie write causes UNDEF exception). */ { ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { - /* Pre-v8 MIDR space. + /* + * Pre-v8 MIDR space. * Note that the MIDR isn't a simple constant register because * of the TI925 behaviour where writes to another register can * cause the MIDR value to change. @@ -8446,7 +8523,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { size_t i; - /* Register the blanket "writes ignored" value first to cover = the + /* + * Register the blanket "writes ignored" value first to cover = the * whole space. Then update the specific ID registers to allow= write * access, so that they ignore writes rather than causing them= to * UNDEF. @@ -8654,7 +8732,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .raw_writefn =3D raw_write, }; if (arm_feature(env, ARM_FEATURE_XSCALE)) { - /* Normally we would always end the TB on an SCTLR write, but = Linux + /* + * Normally we would always end the TB on an SCTLR write, but = Linux * arch/arm/mach-pxa/sleep.S expects two instructions following * an MMU enable to execute from cache. Imitate this behaviou= r. */ @@ -9060,7 +9139,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque) { - /* Define implementations of coprocessor registers. + /* + * Define implementations of coprocessor registers. * We store these in a hashtable because typically * there are less than 150 registers in a space which * is 16*16*16*8*8 =3D 262144 in size. @@ -9127,7 +9207,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, default: g_assert_not_reached(); } - /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 + /* + * The AArch64 pseudocode CheckSystemAccess() specifies that op1 * encodes a minimum access level for the register. We roll this * runtime check into our general permission check code, so check * here that the reginfo's specified permissions are strict enough @@ -9169,7 +9250,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, assert((r->access & ~mask) =3D=3D 0); } =20 - /* Check that the register definition has enough info to handle + /* + * Check that the register definition has enough info to handle * reads and writes if they are permitted. */ if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { @@ -9194,7 +9276,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, continue; } if (state =3D=3D ARM_CP_STATE_AA32) { - /* Under AArch32 CP registers can be common + /* + * Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ char *name; @@ -9220,8 +9303,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, g_assert_not_reached(); } } else { - /* AArch64 registers get mapped to non-secure inst= ance - * of AArch32 */ + /* + * AArch64 registers get mapped to non-secure inst= ance + * of AArch32 + */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); @@ -9307,7 +9392,8 @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMC= PRegInfo *opaque) =20 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) { - /* Return true if it is not valid for us to switch to + /* + * Return true if it is not valid for us to switch to * this CPU mode (ie all the UNPREDICTABLE cases in * the ARM ARM CPSRWriteByInstr pseudocode). */ @@ -9328,10 +9414,12 @@ static int bad_mode_switch(CPUARMState *env, int mo= de, CPSRWriteType write_type) case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: case ARM_CPU_MODE_FIQ: - /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + /* + * Note that we don't implement the IMPDEF NSACR.RFR which in v7 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) */ - /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR + /* + * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR * and CPS are treated as illegal mode changes. */ if (write_type =3D=3D CPSRWriteByInstr && @@ -9389,7 +9477,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, env->GE =3D (val >> 16) & 0xf; } =20 - /* In a V7 implementation that includes the security extensions but do= es + /* + * In a V7 implementation that includes the security extensions but do= es * not include Virtualization Extensions the SCR.FW and SCR.AW bits co= ntrol * whether non-secure software is allowed to change the CPSR_F and CPS= R_A * bits respectively. @@ -9405,7 +9494,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, changed_daif =3D (env->daif ^ val) & mask; =20 if (changed_daif & CPSR_A) { - /* Check to see if we are allowed to change the masking of asy= nc + /* + * Check to see if we are allowed to change the masking of asy= nc * abort exceptions from a non-secure state. */ if (!(env->cp15.scr_el3 & SCR_AW)) { @@ -9417,7 +9507,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, } =20 if (changed_daif & CPSR_F) { - /* Check to see if we are allowed to change the masking of FIQ + /* + * Check to see if we are allowed to change the masking of FIQ * exceptions from a non-secure state. */ if (!(env->cp15.scr_el3 & SCR_FW)) { @@ -9427,7 +9518,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, mask &=3D ~CPSR_F; } =20 - /* Check whether non-maskable FIQ (NMFI) support is enabled. + /* + * Check whether non-maskable FIQ (NMFI) support is enabled. * If this bit is set software is not allowed to mask * FIQs, but is allowed to set CPSR_F to 0. */ @@ -9447,7 +9539,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, if (write_type !=3D CPSRWriteRaw && ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR) { - /* Note that we can only get here in USR mode if this is a + /* + * Note that we can only get here in USR mode if this is a * gdb stub write; for this case we follow the architectural * behaviour for guest writes in USR mode of ignoring an attem= pt * to switch mode. (Those are caught by translate.c for writes @@ -9455,7 +9548,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, */ mask &=3D ~CPSR_M; } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { - /* Attempt to switch to an invalid mode: this is UNPREDICTABLE= in + /* + * Attempt to switch to an invalid mode: this is UNPREDICTABLE= in * v7, and has defined behaviour in v8: * + leave CPSR.M untouched * + allow changes to the other CPSR fields @@ -9598,7 +9692,8 @@ static void switch_mode(CPUARMState *env, int mode) env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; } =20 -/* Physical Interrupt Target EL Lookup Table +/* + * Physical Interrupt Target EL Lookup Table * * [ From ARM ARM section G1.13.4 (Table G1-15) ] * @@ -9672,7 +9767,8 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32= _t excp_idx, if (arm_feature(env, ARM_FEATURE_EL3)) { rw =3D ((env->cp15.scr_el3 & SCR_RW) =3D=3D SCR_RW); } else { - /* Either EL2 is the highest EL (and so the EL2 register width + /* + * Either EL2 is the highest EL (and so the EL2 register width * is given by is64); or there is no EL2 or EL3, in which case * the value of 'rw' does not affect the table lookup anyway. */ @@ -9947,7 +10043,8 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; } =20 - /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ * mode, then we can copy to r8-r14. Otherwise, we copy to the * FIQ bank for r8-r14. */ @@ -10293,7 +10390,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *= cs) /* High vectors. When enabled, base address cannot be remapped. */ addr +=3D 0xffff0000; } else { - /* ARM v7 architectures provide a vector base address register to = remap + /* + * ARM v7 architectures provide a vector base address register to = remap * the interrupt vector table. * This register is only followed in non-monitor mode, and is bank= ed. * Note: only bits 31:5 are valid. @@ -10427,7 +10525,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { - /* Entry vector offset depends on whether the implemented EL + /* + * Entry vector offset depends on whether the implemented EL * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; @@ -10628,7 +10727,8 @@ static void handle_semihosting(CPUState *cs) } #endif =20 -/* Handle a CPU exception for A and R profile CPUs. +/* + * Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. @@ -10673,7 +10773,8 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif =20 - /* Hooks may change global state so BQL should be held, also the + /* + * Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of * cs->interrupt_request. */ @@ -10954,9 +11055,11 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, }; } =20 -/* Note that signed overflow is undefined in C. The following routines are - careful to use unsigned types where modulo arithmetic is required. - Failure to do so _will_ break on newer gcc. */ +/* + * Note that signed overflow is undefined in C. The following routines are + * careful to use unsigned types where modulo arithmetic is required. + * Failure to do so _will_ break on newer gcc. + */ =20 /* Signed saturating arithmetic. */ =20 @@ -11198,7 +11301,8 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t= a, uint32_t b) return (a & mask) | (b & ~mask); } =20 -/* CRC helpers. +/* + * CRC helpers. * The upper bytes of val (above the number specified by 'bytes') must have * been zeroed out by the caller. */ @@ -11222,7 +11326,8 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Return the exception level to which FP-disabled exceptions should +/* + * Return the exception level to which FP-disabled exceptions should * be taken, or 0 if FP is enabled. */ int fp_exception_el(CPUARMState *env, int cur_el) @@ -11230,7 +11335,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) #ifndef CONFIG_USER_ONLY uint64_t hcr_el2; =20 - /* CPACR and the CPTR registers don't exist before v6, so FP is + /* + * CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ if (!arm_feature(env, ARM_FEATURE_V6)) { @@ -11255,7 +11361,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) =20 hcr_el2 =3D arm_hcr_el2_eff(env); =20 - /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: + /* + * The CPACR controls traps to EL1, or PL1 if we're 32 bit: * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937600; cv=none; d=zohomail.com; s=zohoarc; b=d+qg00L8NFsvo8AaDPHnDirdcnmupk13/NQ5zIaJfPnnfNL/piJao2bSuqdYWJ0J2MNABN7bQSd55Gjsz+dq+MgWmvGNz0kd0iBN8Imde8tFiWlCi06qLjjGxHyXfKykhwcSwQX6ceSGWmCl92yS/i8GkTXFmHeGOsGuKi/sI6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937600; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=byMM6iVgc74/+OKbtKS09cRKP886+lRaecSbts9EjCY=; b=Dtt3/XxD6CjczdJnJWVkk5Nxs1S1HwAZgwgvXj7JJ6BcLrvZi8spIuJA3dESfg+hUoK5dW9IHiZYcl0D+0sorFThNnv0hj3WBzXorHH0jdvFxk71YRuRcJn1sgWcfx/jV6+DCbb8SrSPrw5cRNb+eoqrdOP51w4RfLGsVLUrGbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167293760070143.109832772361074; Thu, 5 Jan 2023 08:53:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMa-0001C9-4a; Thu, 05 Jan 2023 11:45:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTM6-0000do-0I for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:41 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM4-0007Qa-7C for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:37 -0500 Received: by mail-wm1-x333.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so1747897wmb.2 for ; Thu, 05 Jan 2023 08:44:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937602372100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Fix the following: ERROR: spaces required around that '|' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '+' (ctx:VxB) ERROR: space prohibited between function name and open parenthesis '(' (the last two still have some occurrences in macros which I left behind because it might impact readability) Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck Message-id: 20221213190537.511-3-farosas@suse.de Signed-off-by: Peter Maydell --- target/arm/helper.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a5f96ab77dd..8f1cc2d7cfb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -205,7 +205,7 @@ static void add_cpreg_to_list(gpointer key, gpointer op= aque) uint32_t regidx =3D (uintptr_t)key; const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); /* The value array need not be initialized at this point */ cpu->cpreg_array_len++; @@ -219,7 +219,7 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 ri =3D g_hash_table_lookup(cpu->cp_regs, key); =20 - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_array_len++; } } @@ -2350,11 +2350,11 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, - .access =3D PL0_R|PL1_W, + .access =3D PL0_R | PL1_W, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), .resetvalue =3D 0}, { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, - .access =3D PL0_R|PL1_W, + .access =3D PL0_R | PL1_W, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, .resetfn =3D arm_cp_reset_ignore }, @@ -4315,17 +4315,17 @@ static const ARMCPRegInfo cache_block_ops_cp_reginf= o[] =3D { .resetvalue =3D 0 }, /* The cache ops themselves: these all NOP for QEMU */ { .name =3D "IICR", .cp =3D 15, .crm =3D 5, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "IDCR", .cp =3D 15, .crm =3D 6, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "CDCR", .cp =3D 15, .crm =3D 12, .opc1 =3D 0, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL0_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "PIR", .cp =3D 15, .crm =3D 12, .opc1 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL0_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "PDR", .cp =3D 15, .crm =3D 12, .opc1 =3D 2, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL0_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { @@ -8695,7 +8695,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo cbar =3D { .name =3D "CBAR", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, - .access =3D PL1_R|PL3_W, .resetvalue =3D cpu->reset_cbar, + .access =3D PL1_R | PL3_W, .resetvalue =3D cpu->reset_cbar, .fieldoffset =3D offsetof(CPUARMState, cp15.c15_config_base_address) }; @@ -9673,11 +9673,11 @@ static void switch_mode(CPUARMState *env, int mode) return; =20 if (old_mode =3D=3D ARM_CPU_MODE_FIQ) { - memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); - memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); + memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); + memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); } else if (mode =3D=3D ARM_CPU_MODE_FIQ) { - memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); - memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); + memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); + memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); } =20 i =3D bank_number(old_mode); @@ -11181,7 +11181,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 16); \ if (sum >=3D 0) \ ge |=3D 3 << (n * 2); \ - } while(0) + } while (0) =20 #define SARITH8(a, b, n, op) do { \ int32_t sum; \ @@ -11189,7 +11189,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 8); \ if (sum >=3D 0) \ ge |=3D 1 << n; \ - } while(0) + } while (0) =20 =20 #define ADD16(a, b, n) SARITH16(a, b, n, +) @@ -11208,7 +11208,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 16); \ if ((sum >> 16) =3D=3D 1) \ ge |=3D 3 << (n * 2); \ - } while(0) + } while (0) =20 #define ADD8(a, b, n) do { \ uint32_t sum; \ @@ -11216,7 +11216,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 8); \ if ((sum >> 8) =3D=3D 1) \ ge |=3D 1 << n; \ - } while(0) + } while (0) =20 #define SUB16(a, b, n) do { \ uint32_t sum; \ @@ -11224,7 +11224,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 16); \ if ((sum >> 16) =3D=3D 0) \ ge |=3D 3 << (n * 2); \ - } while(0) + } while (0) =20 #define SUB8(a, b, n) do { \ uint32_t sum; \ @@ -11232,7 +11232,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 8); \ if ((sum >> 8) =3D=3D 0) \ ge |=3D 1 << n; \ - } while(0) + } while (0) =20 #define PFX u #define ARITH_GE --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938158; cv=none; d=zohomail.com; s=zohoarc; b=J9jjfNmSFhRx8lJlM/pB9Ci7+16UYl5K4yRhmhcZuB7+el/RWhdlCxacl/5zrgUNpPxJFqzd94USkBW+BCeY/Wa6N4t6cHsJq/xN3NVgCp4SFL8YSCvI485r3P8hWT3vVNGUfGm//luHCaVu1dHfD3Ut/gnp1bmvzhI2dEFr4+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938160579100001 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Fix this: ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck Message-id: 20221213190537.511-4-farosas@suse.de Signed-off-by: Peter Maydell --- target/arm/helper.c | 67 ++++++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8f1cc2d7cfb..5d8971aa51e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9461,10 +9461,12 @@ void cpsr_write(CPUARMState *env, uint32_t val, uin= t32_t mask, env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; } - if (mask & CPSR_Q) + if (mask & CPSR_Q) { env->QF =3D ((val & CPSR_Q) !=3D 0); - if (mask & CPSR_T) + } + if (mask & CPSR_T) { env->thumb =3D ((val & CPSR_T) !=3D 0); + } if (mask & CPSR_IT_0_1) { env->condexec_bits &=3D ~3; env->condexec_bits |=3D (val >> 25) & 3; @@ -9669,8 +9671,9 @@ static void switch_mode(CPUARMState *env, int mode) int i; =20 old_mode =3D env->uncached_cpsr & CPSR_M; - if (mode =3D=3D old_mode) + if (mode =3D=3D old_mode) { return; + } =20 if (old_mode =3D=3D ARM_CPU_MODE_FIQ) { memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); @@ -10276,10 +10279,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState= *cs) new_mode =3D ARM_CPU_MODE_UND; addr =3D 0x04; mask =3D CPSR_I; - if (env->thumb) + if (env->thumb) { offset =3D 2; - else + } else { offset =3D 4; + } break; case EXCP_SWI: new_mode =3D ARM_CPU_MODE_SVC; @@ -11070,10 +11074,11 @@ static inline uint16_t add16_sat(uint16_t a, uint= 16_t b) =20 res =3D a + b; if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { - if (a & 0x8000) + if (a & 0x8000) { res =3D 0x8000; - else + } else { res =3D 0x7fff; + } } return res; } @@ -11085,10 +11090,11 @@ static inline uint8_t add8_sat(uint8_t a, uint8_t= b) =20 res =3D a + b; if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { - if (a & 0x80) + if (a & 0x80) { res =3D 0x80; - else + } else { res =3D 0x7f; + } } return res; } @@ -11100,10 +11106,11 @@ static inline uint16_t sub16_sat(uint16_t a, uint= 16_t b) =20 res =3D a - b; if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { - if (a & 0x8000) + if (a & 0x8000) { res =3D 0x8000; - else + } else { res =3D 0x7fff; + } } return res; } @@ -11115,10 +11122,11 @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t= b) =20 res =3D a - b; if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { - if (a & 0x80) + if (a & 0x80) { res =3D 0x80; - else + } else { res =3D 0x7f; + } } return res; } @@ -11136,34 +11144,38 @@ static inline uint16_t add16_usat(uint16_t a, uin= t16_t b) { uint16_t res; res =3D a + b; - if (res < a) + if (res < a) { res =3D 0xffff; + } return res; } =20 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) { - if (a > b) + if (a > b) { return a - b; - else + } else { return 0; + } } =20 static inline uint8_t add8_usat(uint8_t a, uint8_t b) { uint8_t res; res =3D a + b; - if (res < a) + if (res < a) { res =3D 0xff; + } return res; } =20 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) { - if (a > b) + if (a > b) { return a - b; - else + } else { return 0; + } } =20 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); @@ -11267,10 +11279,11 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_= t b) =20 static inline uint8_t do_usad(uint8_t a, uint8_t b) { - if (a > b) + if (a > b) { return a - b; - else + } else { return b - a; + } } =20 /* Unsigned sum of absolute byte differences. */ @@ -11290,14 +11303,18 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32= _t a, uint32_t b) uint32_t mask; =20 mask =3D 0; - if (flags & 1) + if (flags & 1) { mask |=3D 0xff; - if (flags & 2) + } + if (flags & 2) { mask |=3D 0xff00; - if (flags & 4) + } + if (flags & 4) { mask |=3D 0xff0000; - if (flags & 8) + } + if (flags & 8) { mask |=3D 0xff000000; + } return (a & mask) | (b & ~mask); } =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672939512; cv=none; d=zohomail.com; s=zohoarc; b=X7jFQnnqhwqz7SNGJuGIuDkf9EZ9Jhgf0r4OZY+EHOzWc7yqzPV/0pXgXabsqaH5ri3V0VjfpMIr10WansVbPHqxr0MVZTLfXl+T9CszrxXHiRtZTibfcz4Cic/QNdW7KCLlhLi6Bw2ZJtLlZ7pbY2XnIZ7kB5yyB5rOPSRj7bc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672939512; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sztR4J95IadKOvZP/cP3UWW/HHhoPYqwE6deb2jD44g=; b=m9wcfDfUTqMQtdNb0k5sx0pps1h/hXE6fL5OovCM7tDq+74RKbpum/Z7tWFvyuCPJIqfO7BymI+Ur44TKo3Ji7+SsXKU/oO0mciVU5NV5/VMQ21RG3/aCUkVI1uoggMMWe3EZNewk5TcdpqvpiSaJwP6hS+iMub0VzBpmu9R7Js= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939514085100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck Message-id: 20221213190537.511-5-farosas@suse.de Signed-off-by: Peter Maydell --- target/arm/m_helper.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 355cd4d60a7..033a4d92614 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -7,30 +7,14 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" -#include "target/arm/idau.h" -#include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" -#include "qemu/crc32c.h" -#include "qemu/qemu-print.h" #include "qemu/log.h" #include "exec/exec-all.h" -#include /* For crc32 */ -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" -#include "sysemu/kvm.h" -#include "qemu/range.h" -#include "qapi/qapi-commands-machine-target.h" -#include "qapi/error.h" -#include "qemu/guest-random.h" #ifdef CONFIG_TCG -#include "arm_ldst.h" #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939750263100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck Message-id: 20221213190537.511-6-farosas@suse.de Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d8971aa51e..d3e8e606475 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7,13 +7,11 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" #include "qemu/log.h" #include "trace.h" #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "qemu/timer.h" #include "qemu/bitops.h" @@ -22,17 +20,12 @@ #include "exec/exec-all.h" #include /* For crc32 */ #include "hw/irq.h" -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" -#include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" #include "qemu/guest-random.h" #ifdef CONFIG_TCG -#include "arm_ldst.h" -#include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5phcJn3+aOzp5t3SfXhX01zMS188rkd4iS8jVPL2LkE=; b=cme+eRrfbRSg4csUk3Lp05wb4dzOo1sKBE0qYX+J4WSopS3IXVUP7+pvOnBAq7hJQC h1rx/wZMoO9xdCsAuRujK5T9sGvpcGPRPfe1P1ImLpeXxN2mtUO8hFJL+if7HXGBgtfj 1VrqzYrB5Lga9Pz2YJu5fEUoc1Cv9/jXeL5XaZVFf+ufPBe8uoilk6feZmPQ24xEcWMt 2/D7QdfiAbqA9JFJy/OpjBCvTzc7xF9XbaYsptU1wUDyqKxQ+s/3r4bpajIc7jg/8CaI uG+cWPW6iOsLiP+HOLEOty6f8EWp1IpP7nBt84vdpf/5hmw3Z42RJFuOXy0Tev3nO8Lz pF9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5phcJn3+aOzp5t3SfXhX01zMS188rkd4iS8jVPL2LkE=; b=UsfsSKYsx/ZD/YQXtVGhvabYBoFmidNdGTdbKhSuKym/IraqOZg8bQHc3ED8S+IpFo OY/Kt3nh48ixlFXN7GCWfQwjyCHE//0KpKs+Ec+KTohuRQPRm7lRJE6aEnYUDZ8xRnk0 CRzOl752o314yPvrd35XffYFW6td+tpW7F8RltzxLA8kO1liPF1ITSja4qM8/84QWyA8 tKO8qsOTrKO0qByBVuIx+adGyxmzWzCxBAj1bJWsRb8TkPpsTgNg0Hv2QGV+fTMkr9s7 dq2T+bPBbw4gS5ja7XtGbTySh1ZgiR2/UgqzF1gzelicmn09fB1TqPu+AzSR6Td1LgMU vG9A== X-Gm-Message-State: AFqh2kr2m70jq5F0Lfi7cicdFxGb+Zd25hH/30KRqpZLcPdlwGbAEPOR eCEfBRXONNERP9PgH/u3kHu4uQtulAt/0yRf X-Google-Smtp-Source: AMrXdXvEO/DW+Brz6skmMD1v0ol5DK45vEhqw7BvAmb28JltJE0HUifENmP5V2nsfTVlLgQxMXMNdg== X-Received: by 2002:a05:600c:18a1:b0:3d2:3ec4:7eed with SMTP id x33-20020a05600c18a100b003d23ec47eedmr40233937wmp.10.1672937078665; Thu, 05 Jan 2023 08:44:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/34] target/arm: cleanup cpu includes Date: Thu, 5 Jan 2023 16:44:06 +0000 Message-Id: <20230105164417.3994639-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938469488100001 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana Remove some unused headers. Signed-off-by: Claudio Fontana Acked-by: Richard Henderson Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck Signed-off-by: Fabiano Rosas Message-id: 20221213190537.511-7-farosas@suse.de [added back some includes that are still needed at this point] Signed-off-by: Fabiano Rosas Signed-off-by: Peter Maydell --- target/arm/cpu.c | 1 - target/arm/cpu64.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f99f749b295..5f63316dbf2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -26,7 +26,6 @@ #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" -#include "qapi/visitor.h" #include "cpu.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2cf2ca4ce5a..0e021960fb5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,13 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" -#ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" -#endif /* CONFIG_TCG */ #include "qemu/module.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#endif #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "kvm_arm.h" --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937669; cv=none; d=zohomail.com; s=zohoarc; b=kHx0BbLJiF2KVDuZ5SniNxqVma/C8Mhq6KrvtDELrNA1fD7nns7en3PsSPoBU8x0xGSEHLFHAmF2nyja0j4l1VIjReczGCRji8UyUCiyaVht1INUct9e5HXCuaHfmUROdzkXdXvwnN5csa9ry/Que35pv7A3iEr8k7tRU6+gPdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937669; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wEthfbGdCK5i2mFV7wWA7GB9Fv4cHI0iBUrT8VSFqks=; b=MTYAHkcgd/s67pX9aWhKkX2WbgPH4fXni6DkLnHQ55Sma2CH8WH0HZcCqXPgE5JkkY6C3eMq9M23XIOif8jmx/tkIMqhHD+bJKC+J749kIh8TrMLsHIzUdWhuxn2VMc9E6PaAYJ3d0BvCTcmi2EFM5wa6mYI2zsPbbRAzhRcb/A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937669523788.3075083597959; Thu, 5 Jan 2023 08:54:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMh-0001Re-Bi; Thu, 05 Jan 2023 11:45:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMC-0000kl-TS for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:47 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM8-0007Nx-By for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:42 -0500 Received: by mail-wm1-x32e.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso1776908wms.5 for ; Thu, 05 Jan 2023 08:44:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wEthfbGdCK5i2mFV7wWA7GB9Fv4cHI0iBUrT8VSFqks=; b=P5SxrGVPYakve0Z64GTVRAvRKHsNZntW+zp326XIOsACeeyVYhifz8loRDHRJ3psog BxN1vUoDDqoRI0AsejtpGIwn/hVXYXJfvfqSXLGf1ExXeozCc2bWvdIfGZz00kLnOF0i /O3KStwRb8nslegMDUZ7YorFUNkwxJr4omJVSquTYzGOo3qLYIrrDZcIfmDAmq5xXNXm GKcFJ96MxhMT6r2382al4cBxo3U6txwXzbuolxdC4KQZh1UjAQt4DT+5EhWZBjKfCYAF LlJdsrSIjcLQczHfxjnWzwM6SlkOEiScJ5QRWWv3bTReSEhfIw4y0+lpHRRNCnK3tfyY yaWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wEthfbGdCK5i2mFV7wWA7GB9Fv4cHI0iBUrT8VSFqks=; b=GKpLHy0zq1sdsJ1DjsKJrTc82OqAWpoIpFVOaEpvjxC7NwlKvK+nYZ/lNWVHRxPj/6 EWHidG0Cp2a2ocgGPRaziLOvhYmMzvfZ9cSOQ7e4N675QM3BOcAKgviIN/ZtTzJya5zC Q0URrp158JrrWWBdaoBEUeHlRT1oZXV6uXaoVo49b7BIDU+7kgWncrngQsw/KhkKFLw3 JcU+bSaMEc96ICH5IUcn48TqfWifYJ2zMacxXRlTbgaQO2KtcfvJiY2Q2EE3c2IiPuNN MenIBaPUA2kqcKNxHWsPP2qJlwATo4kz3B06mTdhLU7kA9eZ8QRRmwmtgpX3H8yq5hQm ukdQ== X-Gm-Message-State: AFqh2kp6MG08KCwu3rdYcXq+qU5m4AuEZ1+i35d+7bgNQ+4nfF4ZLC8D A7oUL85NxJksl20+QKHRNktkq1SxWLagVN0v X-Google-Smtp-Source: AMrXdXuKUeOmYMW3EV1ZXth0DBYtOikmE9SXOy4pVerOwLyw3GXjbnx/AobzO0HOtfe2pt/6X1JHlA== X-Received: by 2002:a05:600c:1d89:b0:3d3:58cb:f6a6 with SMTP id p9-20020a05600c1d8900b003d358cbf6a6mr36664684wms.41.1672937079413; Thu, 05 Jan 2023 08:44:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/34] hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg Date: Thu, 5 Jan 2023 16:44:07 +0000 Message-Id: <20230105164417.3994639-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937671127100001 From: Philippe Mathieu-Daud=C3=A9 The pointed MouseTransformInfo structure is accessed read-only. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20221220142520.24094-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/input/tsc2xxx.h | 4 ++-- hw/input/tsc2005.c | 2 +- hw/input/tsc210x.c | 3 +-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h index 5b76ebc1776..00eca17674e 100644 --- a/include/hw/input/tsc2xxx.h +++ b/include/hw/input/tsc2xxx.h @@ -30,12 +30,12 @@ uWireSlave *tsc2102_init(qemu_irq pint); uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav); I2SCodec *tsc210x_codec(uWireSlave *chip); uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len); -void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info); +void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *inf= o); void tsc210x_key_event(uWireSlave *chip, int key, int down); =20 /* tsc2005.c */ void *tsc2005_init(qemu_irq pintdav); uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len); -void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); +void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info); =20 #endif diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c index 14698ce1097..555b6771738 100644 --- a/hw/input/tsc2005.c +++ b/hw/input/tsc2005.c @@ -523,7 +523,7 @@ void *tsc2005_init(qemu_irq pintdav) * from the touchscreen. Assuming 12-bit precision was used during * tslib calibration. */ -void tsc2005_set_transform(void *opaque, MouseTransformInfo *info) +void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info) { TSC2005State *s =3D (TSC2005State *) opaque; =20 diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c index df7313db5d7..fdd5ff87d94 100644 --- a/hw/input/tsc210x.c +++ b/hw/input/tsc210x.c @@ -1176,8 +1176,7 @@ I2SCodec *tsc210x_codec(uWireSlave *chip) * from the touchscreen. Assuming 12-bit precision was used during * tslib calibration. */ -void tsc210x_set_transform(uWireSlave *chip, - MouseTransformInfo *info) +void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *inf= o) { TSC210xState *s =3D (TSC210xState *) chip->opaque; #if 0 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937765; cv=none; d=zohomail.com; s=zohoarc; b=hdPqEW0Y3bxiQe0z0hm9oRUHTxklBCp2moFwyWj2DR51KfdaWd/p9L7Mea2LcOG8SvvubV4sIZhULqxFByyvJZS7mAmbY51aK9MSeUlQOd9ntQAIm2t3OXLJVe7c/BZM/ScfUknhj1GBV+WYYNpYda9BogKtXUtcoZ2iVin31+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937765; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2P8f8Xydl4tMqTJeKBieZcm7XuJfXk+zzcjb3vTLYAA=; b=IkboEG7b/80qokfEvUdN84KDBeMuX4SMcPfpRL27udN3D8zWqjeE6wekrgHTWYP1kaSCUOX514k9ltppWcrrZHcXkQhhg/VWGwmLG52Jx/QtIqlg+UDdkFzpe2uuJsf58Y0lExmFAoXzIGJgX2JbUN6h6cZpFRA7cmI21qhMjhE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937765459766.1698001478047; Thu, 5 Jan 2023 08:56:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMU-00017U-N1; Thu, 05 Jan 2023 11:45:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMF-0000lJ-FX for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:49 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTM9-0007Ov-6n for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:45 -0500 Received: by mail-wm1-x32d.google.com with SMTP id m8-20020a05600c3b0800b003d96f801c48so1759513wms.0 for ; Thu, 05 Jan 2023 08:44:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2P8f8Xydl4tMqTJeKBieZcm7XuJfXk+zzcjb3vTLYAA=; b=WF7p91kgVmszzdRqUJPNybNM342/MLauVvN5Fp9f7OTN2alPX7UQKQTtMpg1wnHxQU nuBj8DpScU5gZuoHPEZXxobzgq0/e4pANBTbohwjzL7XpUR4BirersBMB9S/VpiUdQcp /AS9iKyb8S7M6JVyniPHqTpHjHpIgYyNmjD59NMCvJnYrcrXTkheLb0SlDgCQXbGtCCm dpmAiCVoEDvGl11n+6QPgBRjWDGkh+OchecK2RWtncXUlPS3Le2vQ1ckTyHYL/oSIf55 A4iFHYqXL7CfmZztB/sIkPZsFVcTdVYVnQBqkZ7xCLC5rNWB52oslpnENdCPDx0CtktN z/zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2P8f8Xydl4tMqTJeKBieZcm7XuJfXk+zzcjb3vTLYAA=; b=ng+VkTyi4eP31/YL9Q2TRHVwJLFALxNRwRBqe/bfj1f5t7dGwp8oVInDNiR+vMqGEg gtZC3Q2MsKR/lTqaNn+23li0sze+0LgmW1nZ3rh4QZEw8J29oTmfOFjz1RFx4Lvjbu3J MuVS/Ck2yY+iETBH9Kt0wDxM3CcsmLlMwfxthhLVzzdYxkRthIgoiKsHfMCXiHRHAbZC t+5J5uoAvI01trANuqbK75WP52jIEu1VnHPNtc7hx4WCfUOKDX+DFpIBYPtmsqaJK9j5 OWIJihbTngg+FnejZwChhzP54mklGDf2niBPmPGYLKx9hCesPalbNzCKnUDPFnLbMp6T agrg== X-Gm-Message-State: AFqh2kpCZjsh6E2XVqW0w6RsSu/xR5RW9TTMBO4ZuKaC3yQGTfSoSl2L yroZ8JiGbG71jVE+Fu72U2ddwKrf17+Efpvf X-Google-Smtp-Source: AMrXdXukms6IFFecOnPM6LN6RSWyiXQ+auUYEbKdy2g6qmwdGoIrck4XXnl7BMe5hBIM+74gnrK/jQ== X-Received: by 2002:a05:600c:3485:b0:3d0:761b:f86 with SMTP id a5-20020a05600c348500b003d0761b0f86mr36267396wmq.28.1672937080158; Thu, 05 Jan 2023 08:44:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/34] hw/arm/nseries: Constify various read-only arrays Date: Thu, 5 Jan 2023 16:44:08 +0000 Message-Id: <20230105164417.3994639-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937765787100001 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20221220142520.24094-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/nseries.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index b151113c275..2ff29f52e2d 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -230,13 +230,13 @@ static void n8x0_i2c_setup(struct n800_s *s) } =20 /* Touchscreen and keypad controller */ -static MouseTransformInfo n800_pointercal =3D { +static const MouseTransformInfo n800_pointercal =3D { .x =3D 800, .y =3D 480, .a =3D { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, }; =20 -static MouseTransformInfo n810_pointercal =3D { +static const MouseTransformInfo n810_pointercal =3D { .x =3D 800, .y =3D 480, .a =3D { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, @@ -334,7 +334,7 @@ static void n810_key_event(void *opaque, int keycode) =20 #define M 0 =20 -static int n810_keys[0x80] =3D { +static const int n810_keys[0x80] =3D { [0x01] =3D 16, /* Q */ [0x02] =3D 37, /* K */ [0x03] =3D 24, /* O */ @@ -810,7 +810,7 @@ static void n8x0_usb_setup(struct n800_s *s) /* Setup done before the main bootloader starts by some early setup code * - used when we want to run the main bootloader in emulation. This * isn't documented. */ -static uint32_t n800_pinout[104] =3D { +static const uint32_t n800_pinout[104] =3D { 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, 0x08080808, 0x180800c4, 0x00b80000, 0x08080808, @@ -1060,7 +1060,7 @@ static void n8x0_boot_init(void *opaque) #define OMAP_TAG_CBUS 0x4e03 #define OMAP_TAG_EM_ASIC_BB5 0x4e04 =20 -static struct omap_gpiosw_info_s { +static const struct omap_gpiosw_info_s { const char *name; int line; int type; @@ -1102,7 +1102,7 @@ static struct omap_gpiosw_info_s { { NULL } }; =20 -static struct omap_partition_info_s { +static const struct omap_partition_info_s { uint32_t offset; uint32_t size; int mask; @@ -1125,15 +1125,15 @@ static struct omap_partition_info_s { { 0, 0, 0, NULL } }; =20 -static uint8_t n8x0_bd_addr[6] =3D { N8X0_BD_ADDR }; +static const uint8_t n8x0_bd_addr[6] =3D { N8X0_BD_ADDR }; =20 static int n8x0_atag_setup(void *p, int model) { uint8_t *b; uint16_t *w; uint32_t *l; - struct omap_gpiosw_info_s *gpiosw; - struct omap_partition_info_s *partition; + const struct omap_gpiosw_info_s *gpiosw; + const struct omap_partition_info_s *partition; const char *tag; =20 w =3D p; --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672939727; cv=none; d=zohomail.com; s=zohoarc; b=N+72N6P5Qiy1Q7vkwtEm9UsU0OvKdSaeJwUoFmDagGJTzE7i3o04K96U8SGlGypxjwgzgwGLbGwtFZ0UeiYSJADUtddcT+2Zk1N6UMabl8TxROaH0XpzF8lIcbCskR1hgMzK8ynO2GrssUCVVo9zA6BlTftcDrbvGjuGXad1il0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672939727; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sMnAfCWZCLNwdcWgdCth6k3nhxTM77vAKQFc00HifCI=; b=JII8nRNmnUjuPrf2KQ3r6eO7pKkdKgmAqGWlU4QYHXWrimshQ2xj302e87M5mU9xFwXzvs79FTMhRe/EadhEDIo63KEJT0NSVekxQCchL0KuC00cyoCtelp5OZRJVq8m0rl9vMbmhSPnOfYsRlKTiiMq4pq0BNFxliukW1tm2No= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16729397270771020.6248182470857; Thu, 5 Jan 2023 09:28:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTN2-0001gZ-GA; Thu, 05 Jan 2023 11:45:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMG-0000lm-Vh for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:50 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTMA-0007Lt-Cw for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:45 -0500 Received: by mail-wm1-x334.google.com with SMTP id g10so14661381wmo.1 for ; Thu, 05 Jan 2023 08:44:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=sMnAfCWZCLNwdcWgdCth6k3nhxTM77vAKQFc00HifCI=; b=w7VsZh2YUNU4Wq1EFuQTzpyVpJPsB61JAmd++c74Z31nGpzj114JqAdtbtA86UoQd8 RkwfzZHS/U2VnD+tJgfOjXOcxBRG04i3QH7pZ9iWzGCX8e7Ha+Ky3Y6wVIcVCX5I74Lu ox5HDg9tjJZqPYoRqtWhTitl9VmpWbaC+xJ4J2kgVJ39FC1gLAnH79UiEhXDA00I50uy JiU8fxk1Uzf48mmu9j8TepfGnvKK3gckvFETGRcqDj1ebjC9gwKFQ8SncaqdD7K8nQuD 3bWCf8JyCXWbmzrR6RvxaXvrIEs6wmsCGC6hZ2mY6dfM5E9Ib7Ssc/dZ3KCh7t6RXb8K CMTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMnAfCWZCLNwdcWgdCth6k3nhxTM77vAKQFc00HifCI=; b=0s3HM4J2YB3IEbr9A9JJLVGF9FJvTouataV6CNW7RHJDAjdRtkkhzaXJSNPiJAIkpL ikA+UpAwaLvtZ1hli9NYmmj7tqXOY3SWHqZmvryTsjF7D87s02Toho8Ehy2KtXThpSaT X1fyy1oi1fqw7/IRN+cdcgnYPBsSqbfZimVjec4HMeYAs9txYXqDTNiWxI57ea+7fR0w 2nz7eM+EW6/oSHRJGeEVIBdO2xlCzFfRLDpjHNc97eDFtqemdexcNa0wGgDwzinOSJTn f56RT3WYSnZUjr14S7iktYBeYLwH+forjh+2A9l4GMWvUrQjNFZtxdFQs99Nyyjotdp9 qSLA== X-Gm-Message-State: AFqh2kr+oUgG+XgigPye7PHA4r7r/lpsKkOdfdKYWHf32iEzEaaOPKGh qWGEBNugm5RODI08o+6H5zgK72ygkwx6LsvH X-Google-Smtp-Source: AMrXdXuk0xfhs6wbDaw+bTiIPDk7k0RGsgNsjQZ80wIS4mGofs2n+GUMy1nrfIwEwdVpo9cfBD1lZg== X-Received: by 2002:a05:600c:c8a:b0:3d9:7062:e0b7 with SMTP id fj10-20020a05600c0c8a00b003d97062e0b7mr31050441wmb.33.1672937080962; Thu, 05 Jan 2023 08:44:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/34] hw/arm/nseries: Silent -Wmissing-field-initializers warning Date: Thu, 5 Jan 2023 16:44:09 +0000 Message-Id: <20230105164417.3994639-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939728130100003 From: Philippe Mathieu-Daud=C3=A9 Silent when compiling with -Wextra: ../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-= Wmissing-field-initializers] { NULL } ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20221220142520.24094-4-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/nseries.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 2ff29f52e2d..c9df063a082 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1078,7 +1078,7 @@ static const struct omap_gpiosw_info_s { "headphone", N8X0_HEADPHONE_GPIO, OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, }, - { NULL } + { /* end of list */ } }, n810_gpiosw_info[] =3D { { "gps_reset", N810_GPS_RESET_GPIO, @@ -1099,7 +1099,7 @@ static const struct omap_gpiosw_info_s { "slide", N810_SLIDE_GPIO, OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, }, - { NULL } + { /* end of list */ } }; =20 static const struct omap_partition_info_s { @@ -1113,16 +1113,14 @@ static const struct omap_partition_info_s { { 0x00080000, 0x00200000, 0x0, "kernel" }, { 0x00280000, 0x00200000, 0x3, "initfs" }, { 0x00480000, 0x0fb80000, 0x3, "rootfs" }, - - { 0, 0, 0, NULL } + { /* end of list */ } }, n810_part_info[] =3D { { 0x00000000, 0x00020000, 0x3, "bootloader" }, { 0x00020000, 0x00060000, 0x0, "config" }, { 0x00080000, 0x00220000, 0x0, "kernel" }, { 0x002a0000, 0x00400000, 0x0, "initfs" }, { 0x006a0000, 0x0f960000, 0x0, "rootfs" }, - - { 0, 0, 0, NULL } + { /* end of list */ } }; =20 static const uint8_t n8x0_bd_addr[6] =3D { N8X0_BD_ADDR }; --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TUUrqVHsbshf4grGNc3KmU3/yCcgNu5T7lT/XacC1ek=; b=AUSt5NdRIfWyeM+k6mlIP8S6Diq2f+6rbMTkhATVjpzIR+CW5motElZtGZziyFJVJv W39V5a6vitu9aamVWZ6dEaiB6JL9Le/WlD9x+aVR5wxF6bWDYT68X+BxK3+WlqP0UOnQ aVR/7AjnlrjRLgFMQuSNdvpf3cuyJsrcaRY1mdkbD4/yLtFqEYRDhOJpyq1WH1HB8vX7 VAp5HIYt66qe+Np7tMEmmCMRqPUeyxB5I+6M9jD3Qz7mHXkN5Kdsp/x6DloKx7ZZUXGs v3LvNLuVloBNpM/hVafIhg6ClI5CCNLd6mGjK69BiiffZof02O1BHDujVjQrfoXuPguH Isaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TUUrqVHsbshf4grGNc3KmU3/yCcgNu5T7lT/XacC1ek=; b=L2A4PeYvk9BF2rXSXUnaj1BJIcvH5btvHsvOSlk+XmyF3fs0AGq3IMxbzag48u4mx5 /v+8dgntUyzl4yr+Zo7u6ZFtVJmDXZD8B3B1Z9543+VS87OStR1gtEd8GUtJ3R+Vm4rO Juuw8dWCOfmBqoTdN11thhnKocGARG/lbtXbYjRv9j97l1M8iP+0Ifdg+jRofb+OJP9O LLvMsJkH33SeB4wXFCI3bg+PyDe1B/iKWZKDeYDQY0HunWKGKJeCLkHOYtRw8uL0znCu urX5K5CqzmcP9QWVSl6we+oEa7zolilUsJwIJYPNJ5JpiUAxKieGZy3pLSSp37OxnAOJ 6G4Q== X-Gm-Message-State: AFqh2krWYg2jLdiPkobdxQFIStpUptuvS3nekVtMe5TawPB3tVT5G8Ab SAu2Aq++xR8GDyVnaxexrQr5r4Xke0wl6oiS X-Google-Smtp-Source: AMrXdXteFpxt5FHXdumQ0ghr6rfdyul409sG6rS+QqrUFQlplBcYz4FK+ft7P5aUCcoajFwIcwmi7w== X-Received: by 2002:a05:600c:358f:b0:3d1:cdf7:debf with SMTP id p15-20020a05600c358f00b003d1cdf7debfmr38009170wmq.26.1672937081747; Thu, 05 Jan 2023 08:44:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/34] target/arm: align exposed ID registers with Linux Date: Thu, 5 Jan 2023 16:44:10 +0000 Message-Id: <20230105164417.3994639-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672940090594100003 Content-Type: text/plain; charset="utf-8" From: Zhuojia Shen In CPUID registers exposed to userspace, some registers were missing and some fields were not exposed. This patch aligns exposed ID registers and their fields with what the upstream kernel currently exposes. Specifically, the following new ID registers/fields are exposed to userspace: ID_AA64PFR1_EL1.BT: bits 3-0 ID_AA64PFR1_EL1.MTE: bits 11-8 ID_AA64PFR1_EL1.SME: bits 27-24 ID_AA64ZFR0_EL1.SVEver: bits 3-0 ID_AA64ZFR0_EL1.AES: bits 7-4 ID_AA64ZFR0_EL1.BitPerm: bits 19-16 ID_AA64ZFR0_EL1.BF16: bits 23-20 ID_AA64ZFR0_EL1.SHA3: bits 35-32 ID_AA64ZFR0_EL1.SM4: bits 43-40 ID_AA64ZFR0_EL1.I8MM: bits 47-44 ID_AA64ZFR0_EL1.F32MM: bits 55-52 ID_AA64ZFR0_EL1.F64MM: bits 59-56 ID_AA64SMFR0_EL1.F32F32: bit 32 ID_AA64SMFR0_EL1.B16F32: bit 34 ID_AA64SMFR0_EL1.F16F32: bit 35 ID_AA64SMFR0_EL1.I8I32: bits 39-36 ID_AA64SMFR0_EL1.F64F64: bit 48 ID_AA64SMFR0_EL1.I16I64: bits 55-52 ID_AA64SMFR0_EL1.FA64: bit 63 ID_AA64MMFR0_EL1.ECV: bits 63-60 ID_AA64MMFR1_EL1.AFP: bits 47-44 ID_AA64MMFR2_EL1.AT: bits 35-32 ID_AA64ISAR0_EL1.RNDR: bits 63-60 ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 ID_AA64ISAR1_EL1.BF16: bits 47-44 ID_AA64ISAR1_EL1.DGH: bits 51-48 ID_AA64ISAR1_EL1.I8MM: bits 55-52 ID_AA64ISAR2_EL1.WFxT: bits 3-0 ID_AA64ISAR2_EL1.RPRES: bits 7-4 ID_AA64ISAR2_EL1.GPA3: bits 11-8 ID_AA64ISAR2_EL1.APA3: bits 15-12 The code is also refactored to use symbolic names for ID register fields for better readability and maintainability. The test case in tests/tcg/aarch64/sysregs.c is also updated to match the intended behavior. Signed-off-by: Zhuojia Shen Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.p= rod.outlook.com Reviewed-by: Peter Maydell [PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1] Signed-off-by: Peter Maydell --- target/arm/helper.c | 96 +++++++++++++++++++++++++------ tests/tcg/aarch64/sysregs.c | 24 ++++++-- tests/tcg/aarch64/Makefile.target | 7 ++- 3 files changed, 103 insertions(+), 24 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d3e8e606475..cee38043540 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8147,31 +8147,89 @@ void register_cp_regs_for_features(ARMCPU *cpu) #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { { .name =3D "ID_AA64PFR0_EL1", - .exported_bits =3D 0x000f000f00ff0000, - .fixed_bits =3D 0x0000000000000011 }, + .exported_bits =3D R_ID_AA64PFR0_FP_MASK | + R_ID_AA64PFR0_ADVSIMD_MASK | + R_ID_AA64PFR0_SVE_MASK | + R_ID_AA64PFR0_DIT_MASK, + .fixed_bits =3D (0x1u << R_ID_AA64PFR0_EL0_SHIFT) | + (0x1u << R_ID_AA64PFR0_EL1_SHIFT) }, { .name =3D "ID_AA64PFR1_EL1", - .exported_bits =3D 0x00000000000000f0 }, + .exported_bits =3D R_ID_AA64PFR1_BT_MASK | + R_ID_AA64PFR1_SSBS_MASK | + R_ID_AA64PFR1_MTE_MASK | + R_ID_AA64PFR1_SME_MASK }, { .name =3D "ID_AA64PFR*_EL1_RESERVED", - .is_glob =3D true }, - { .name =3D "ID_AA64ZFR0_EL1" }, + .is_glob =3D true }, + { .name =3D "ID_AA64ZFR0_EL1", + .exported_bits =3D R_ID_AA64ZFR0_SVEVER_MASK | + R_ID_AA64ZFR0_AES_MASK | + R_ID_AA64ZFR0_BITPERM_MASK | + R_ID_AA64ZFR0_BFLOAT16_MASK | + R_ID_AA64ZFR0_SHA3_MASK | + R_ID_AA64ZFR0_SM4_MASK | + R_ID_AA64ZFR0_I8MM_MASK | + R_ID_AA64ZFR0_F32MM_MASK | + R_ID_AA64ZFR0_F64MM_MASK }, + { .name =3D "ID_AA64SMFR0_EL1", + .exported_bits =3D R_ID_AA64SMFR0_F32F32_MASK | + R_ID_AA64SMFR0_B16F32_MASK | + R_ID_AA64SMFR0_F16F32_MASK | + R_ID_AA64SMFR0_I8I32_MASK | + R_ID_AA64SMFR0_F64F64_MASK | + R_ID_AA64SMFR0_I16I64_MASK | + R_ID_AA64SMFR0_FA64_MASK }, { .name =3D "ID_AA64MMFR0_EL1", - .fixed_bits =3D 0x00000000ff000000 }, - { .name =3D "ID_AA64MMFR1_EL1" }, + .exported_bits =3D R_ID_AA64MMFR0_ECV_MASK, + .fixed_bits =3D (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) | + (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, + { .name =3D "ID_AA64MMFR1_EL1", + .exported_bits =3D R_ID_AA64MMFR1_AFP_MASK }, + { .name =3D "ID_AA64MMFR2_EL1", + .exported_bits =3D R_ID_AA64MMFR2_AT_MASK }, { .name =3D "ID_AA64MMFR*_EL1_RESERVED", - .is_glob =3D true }, + .is_glob =3D true }, { .name =3D "ID_AA64DFR0_EL1", - .fixed_bits =3D 0x0000000000000006 }, - { .name =3D "ID_AA64DFR1_EL1" }, + .fixed_bits =3D (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) }, + { .name =3D "ID_AA64DFR1_EL1" }, { .name =3D "ID_AA64DFR*_EL1_RESERVED", - .is_glob =3D true }, + .is_glob =3D true }, { .name =3D "ID_AA64AFR*", - .is_glob =3D true }, + .is_glob =3D true }, { .name =3D "ID_AA64ISAR0_EL1", - .exported_bits =3D 0x00fffffff0fffff0 }, + .exported_bits =3D R_ID_AA64ISAR0_AES_MASK | + R_ID_AA64ISAR0_SHA1_MASK | + R_ID_AA64ISAR0_SHA2_MASK | + R_ID_AA64ISAR0_CRC32_MASK | + R_ID_AA64ISAR0_ATOMIC_MASK | + R_ID_AA64ISAR0_RDM_MASK | + R_ID_AA64ISAR0_SHA3_MASK | + R_ID_AA64ISAR0_SM3_MASK | + R_ID_AA64ISAR0_SM4_MASK | + R_ID_AA64ISAR0_DP_MASK | + R_ID_AA64ISAR0_FHM_MASK | + R_ID_AA64ISAR0_TS_MASK | + R_ID_AA64ISAR0_RNDR_MASK }, { .name =3D "ID_AA64ISAR1_EL1", - .exported_bits =3D 0x000000f0ffffffff }, + .exported_bits =3D R_ID_AA64ISAR1_DPB_MASK | + R_ID_AA64ISAR1_APA_MASK | + R_ID_AA64ISAR1_API_MASK | + R_ID_AA64ISAR1_JSCVT_MASK | + R_ID_AA64ISAR1_FCMA_MASK | + R_ID_AA64ISAR1_LRCPC_MASK | + R_ID_AA64ISAR1_GPA_MASK | + R_ID_AA64ISAR1_GPI_MASK | + R_ID_AA64ISAR1_FRINTTS_MASK | + R_ID_AA64ISAR1_SB_MASK | + R_ID_AA64ISAR1_BF16_MASK | + R_ID_AA64ISAR1_DGH_MASK | + R_ID_AA64ISAR1_I8MM_MASK }, + { .name =3D "ID_AA64ISAR2_EL1", + .exported_bits =3D R_ID_AA64ISAR2_WFXT_MASK | + R_ID_AA64ISAR2_RPRES_MASK | + R_ID_AA64ISAR2_GPA3_MASK | + R_ID_AA64ISAR2_APA3_MASK }, { .name =3D "ID_AA64ISAR*_EL1_RESERVED", - .is_glob =3D true }, + .is_glob =3D true }, }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); #endif @@ -8508,8 +8566,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = =3D { { .name =3D "MIDR_EL1", - .exported_bits =3D 0x00000000ffffffff }, - { .name =3D "REVIDR_EL1" }, + .exported_bits =3D R_MIDR_EL1_REVISION_MASK | + R_MIDR_EL1_PARTNUM_MASK | + R_MIDR_EL1_ARCHITECTURE_MASK | + R_MIDR_EL1_VARIANT_MASK | + R_MIDR_EL1_IMPLEMENTER_MASK }, + { .name =3D "REVIDR_EL1" }, }; modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); #endif diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c index 40cf8d2877e..46b931f781d 100644 --- a/tests/tcg/aarch64/sysregs.c +++ b/tests/tcg/aarch64/sysregs.c @@ -22,6 +22,13 @@ #define HWCAP_CPUID (1 << 11) #endif =20 +/* + * Older assemblers don't recognize newer system register names, + * but we can still access them by the Sn_n_Cn_Cn_n syntax. + */ +#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2 +#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + int failed_bit_count; =20 /* Read and print system register `id' value */ @@ -112,18 +119,23 @@ int main(void) * minimum valid fields - for the purposes of this check allowed * to have non-zero values. */ - get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0)); - get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff)); + get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0)); + get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff)); + get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff)); /* TGran4 & TGran64 as pegged to -1 */ - get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000)); - get_cpu_reg_check_zero(id_aa64mmfr1_el1); + get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000)); + get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000)); + get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000)); /* EL1/EL0 reported as AA64 only */ get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011)); - get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0)); + get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff)); /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); get_cpu_reg_check_zero(id_aa64dfr1_el1); - get_cpu_reg_check_zero(id_aa64zfr0_el1); + get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff)); +#ifdef HAS_ARMV9_SME + get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000)); +#endif =20 get_cpu_reg_check_zero(id_aa64afr0_el1); get_cpu_reg_check_zero(id_aa64afr1_el1); diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index fc8d90ed692..db122ab4ff3 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -23,7 +23,8 @@ config-cc.mak: Makefile $(call cc-option,-march=3Darmv8.1-a+sve2, CROSS_CC_HAS_SVE2);= \ $(call cc-option,-march=3Darmv8.3-a, CROSS_CC_HAS_ARMV8_= 3); \ $(call cc-option,-mbranch-protection=3Dstandard, CROSS_CC_HAS_ARMV8_= BTI); \ - $(call cc-option,-march=3Darmv8.5-a+memtag, CROSS_CC_HAS_ARMV8_= MTE)) 3> config-cc.mak + $(call cc-option,-march=3Darmv8.5-a+memtag, CROSS_CC_HAS_ARMV8_= MTE); \ + $(call cc-option,-march=3Darmv9-a+sme, CROSS_CC_HAS_ARMV9_= SME)) 3> config-cc.mak -include config-cc.mak =20 # Pauth Tests @@ -53,7 +54,11 @@ endif ifneq ($(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS +=3D sysregs +ifneq ($(CROSS_CC_HAS_ARMV9_SME),) +sysregs: CFLAGS+=3D-march=3Darmv9-a+sme -DHAS_ARMV9_SME +else sysregs: CFLAGS+=3D-march=3Darmv8.1-a+sve +endif =20 # SVE ioctl test AARCH64_TESTS +=3D sve-ioctls --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938741; cv=none; d=zohomail.com; s=zohoarc; b=iq+AlFpitMf32mVvbZZofVG8LElS1naabjBBBhiBBTaMdYFAB9y6I9oUlOLGdAm2Zs2323l8eNgA25QIvhwP+2OXGLFt45C6AWThsKnBypkZzNjpVqfeK7TLXwJRAFGeR63JDoaP2SlmyGYWtRThRB/nKfM02bh0RI59BFX3wFo= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3npsTUveFtQ4HNUpCii6m95dErHPlNzn4rRyXMWJ2LY=; b=FtUPtj6STbtw9GjlSpF61MkZUBHAuggA25z6TacVSdPaz12QqRGvzMjGbgFCuFpBBL L2Wdt4EyO9Wu9Im/dRDLRiByXSvEF3rFNPv3gPfORsAuWYbCUQEznC/ub7vNlIhavaxW KsAc3W7+7oC03UsUWVa7hRzUn6EYzCD4nDY0WaZlDnmLETvmnbj46JI1x8QJT2hvBRAu 5v2LD86fpCRdaCLgIuJWwXKDxjirFAGMM3o07GbqlqBAtojzxMn8Idx/lke5jhVnbaf8 /YeNTNO3FtumTM+b3W5pkQv/i386zaWV6G0qV1JF3C1HfgOqVUfutJJMD6N0fGYJWTDk 86Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3npsTUveFtQ4HNUpCii6m95dErHPlNzn4rRyXMWJ2LY=; b=8C6YdvUzpvzL28gKEWCa2viCHbkO6TFtGsFMPiujBnHcBnwX7LnooNg7jN9RiZolEy B7a9UII7S6jtFeXyrC2JKSWUguj+fWsXZys7zY5bRuBrzZ78qzJ/AYTL9qBgjXDsPOUv uFvmml4TEXFYgUtoFemkE9yF9cGeWjgP2HI2ml6RN6GuzPzk2Y24VysHbru0Z2dXpqLv LW5uu8K153bIps60d3fvVHet2nyysMBsOWwwqwZw+J2PmgBw+8IwQzCxfhRVCuTj6mwV gJMhKe85aiKucXDPvu3fgUfvz+9tLS5TLqyVsOELy562Phmd9q3xavmlIiIXS3yPEaG6 J7kQ== X-Gm-Message-State: AFqh2kq17xXZMLn4QyLl5H/9AZ2bbo4em1DCumQZ87HSJMURFwqq4dOX aVVfcb1ug732nJWRZo3l7tIvEOE6eHeCjQff X-Google-Smtp-Source: AMrXdXtxs0f3WcBZwO4QXP0GRz6hH9BUooflS5IYtENsq+JBPCnV13mNiE+uP7BPFGj108c+mpWiqA== X-Received: by 2002:a05:600c:3d1b:b0:3d0:6a57:66a5 with SMTP id bh27-20020a05600c3d1b00b003d06a5766a5mr36114367wmb.0.1672937082502; Thu, 05 Jan 2023 08:44:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/34] hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope Date: Thu, 5 Jan 2023 16:44:11 +0000 Message-Id: <20230105164417.3994639-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938743838100003 From: Philippe Mathieu-Daud=C3=A9 This function is not used anywhere outside this file, so we can make the function "static void". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20221216214924.4711-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 3 --- hw/arm/smmu-common.c | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 21e62342e92..c5683af07d6 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -173,7 +173,4 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_ad= dr_t iova, /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); =20 -/* Unmap the range of all the notifiers registered to @mr */ -void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr); - #endif /* HW_ARM_SMMU_COMMON_H */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 220838525d4..9f196625a2b 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -483,7 +483,7 @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n) } =20 /* Unmap all notifiers attached to @mr */ -inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr) +static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr) { IOMMUNotifier *n; =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938477; cv=none; d=zohomail.com; s=zohoarc; b=AKwJc6OsznZVmPxseL4CuBSemKJCxhQSJ05SO9IbLIT7HFWBOLOkHDJQVjDIjfKg7urto2rCsf8LUJhHsUidtV0ig82LwdjOjjHk7C0SbbIinFCgi2Gm8RaK4MBkM45UEUqAZsN5PD91oqpkLkljFHi8MblbeFt6Ny6qiJVf8pg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672938477; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NIfbKJ/3ZkCvJIhNz8wE2t2u1al6fnbpkmOv2zew4vY=; b=epli8E96GNmQy0ZzDCpcKAO5hpzrRH2qNXwbqvuNAj1GCFWKxsGDoBKUe6FUeILv1M+Krb1i81B15Xp55zlY/180IWuXxflth2B+qfDJo8Jija8Cqp2vuNId7OTfJNnpE8orEMR2qjm7hbGFKmvc+ZOdBW9ipw1kBXcv8Uy3erQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672938477141983.0330999256707; Thu, 5 Jan 2023 09:07:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMf-0001Lj-6W; Thu, 05 Jan 2023 11:45:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMI-0000m7-0B for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:50 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTMC-0007Ss-Lq for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:48 -0500 Received: by mail-wm1-x32a.google.com with SMTP id i17-20020a05600c355100b003d99434b1cfso1787135wmq.1 for ; Thu, 05 Jan 2023 08:44:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NIfbKJ/3ZkCvJIhNz8wE2t2u1al6fnbpkmOv2zew4vY=; b=MAzC5WOQTyz31T9GyWYxgHhDqod4dRuoANpsKo05PnaKOpRtBQ0OynQFAD2vgFRvAv ewi2SLseQKhc4xziNLaWTPNfw08VOLf5wBUJwxbm2EKYtBESIznPeqE7YuLdCEA4fARs JylCfUxGodTkbJvxjdT4KykXfdEHfmr1TIVFix/V0IN6AiO6+lFSIDBnddwCehX/lFvw 0xAGOIFkYKW5SxL7JRzfNzUQDXGK7cW7d8cknK9cPkFZYrjV6ev8H+hTCqZ7sfwU5OAm T0J3YPpkG1WFGcUhMQDEoEjGZMO6faPUw43rUd/dNmDGpQD0o4igDn+VOsTqM/4DZrK0 yxyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NIfbKJ/3ZkCvJIhNz8wE2t2u1al6fnbpkmOv2zew4vY=; b=rANS9RJwe0Nhz1XVgQ+ENZ0ItIWtYPhaoCJp9ZOxdwrB8dol9Qn2pwj+Z/lNefi7zj S9x4OVsa2MoAcwlw8IaVbykAOTU7Lp7dzsVaI8+ZfDDZVs5daPLCfYHUIAKrOIy6v/Gd +qknPmBh2etd6aJ9gFRthR0pAQnDfflt3RUdrQ2VUHw8m4Be86c6BV/XyNk8ohsvnKiQ V60Uj6qe3/YaiTbyrK6JHEOhmA8Iky2ozNVHtKHsdfpbtJUNTZ7+5DfAn1PmZselQybe Qq+drBDLDfeykpIUWBfKEE34Lwo4HtZUJBQHwfU0w3UOQowpaCu0bNXZIzsOICUcXub4 CRhQ== X-Gm-Message-State: AFqh2kpjSyKxa3oaFZwrtKa5w0CMFfIBwa8D6uvba0dD3EezrowOB2ka 4anqamWA5iT7rrfXJABqoULSuzCeDmBd599c X-Google-Smtp-Source: AMrXdXtyW3a/FpULxdv7zIcYfL5a0b80t5oeoPd4c2LCTTMj2hLx+Dc1XllXtm/Df3AQ/WGLT4OQPw== X-Received: by 2002:a05:600c:1f18:b0:3cf:5583:8b3f with SMTP id bd24-20020a05600c1f1800b003cf55838b3fmr35524312wmb.20.1672937083374; Thu, 05 Jan 2023 08:44:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/34] hw/arm/smmu-common: Avoid using inlined functions with external linkage Date: Thu, 5 Jan 2023 16:44:12 +0000 Message-Id: <20230105164417.3994639-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938479401100001 From: Philippe Mathieu-Daud=C3=A9 When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)") and building with -Wall we get: hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_b= y_asid_iova' is used in an inline function with external linkage [-Wstatic-= in-inline] hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 's= mmu_iotlb_inv_iova' internal linkage void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, ^ static None of our code base require / use inlined functions with external linkage. Some places use internal inlining in the hot path. These two functions are certainly not in any hot path and don't justify any inlining, so these are likely oversights rather than intentional. Reported-by: Stefan Weil Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20221216214924.4711-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 9f196625a2b..54186f31cb5 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -116,7 +116,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg= , SMMUTLBEntry *new) g_hash_table_insert(bs->iotlb, key, new); } =20 -inline void smmu_iotlb_inv_all(SMMUState *s) +void smmu_iotlb_inv_all(SMMUState *s) { trace_smmu_iotlb_inv_all(); g_hash_table_remove_all(s->iotlb); @@ -146,9 +146,8 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer = key, gpointer value, ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 -inline void -smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, - uint8_t tg, uint64_t num_pages, uint8_t ttl) +void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, + uint8_t tg, uint64_t num_pages, uint8_t ttl) { /* if tg is not set we use 4KB range invalidation */ uint8_t granule =3D tg ? tg * 2 + 10 : 12; @@ -174,7 +173,7 @@ smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t = iova, &info); } =20 -inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) +void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) { trace_smmu_iotlb_inv_asid(asid); g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); @@ -374,8 +373,8 @@ error: * * return 0 on success */ -inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags p= erm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) +int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { if (!cfg->aa64) { /* --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938371; cv=none; d=zohomail.com; s=zohoarc; b=jYk4Slat3m2ruWx3EjMVyW6t7QWJB0lI2iwvvBZD9umsKszOZhI18vfzlY54MexJCi5GujgDNgN1nxYIAQqDzJIROCckJIgZrRF9D1dIhFJriku+Z78u3qPxwl1j8QY0yZA6xcWe7IGDU+nNCN1Eovn2sGNgEXkdByZgdGCl1WQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672938371; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WdsQkzgPH1wTahyKLQ7ZmQKEPjf3NSnJoH3HoNNy3yI=; b=DoMq68eOekEgynoAThXrFfQyldzOGs4t1u94ypaMYtoeubn6qmWMMTSxj/RFPFFSUpdGsbBkiq5IMFykysFV77psqpJopHNUz66Dkkz3bSfDE1Esh0hTAf20Mep2EIEIpuNtV4oxsScpEmNTd3OgaDTIa+knC/uj1OQfMXPH7vw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672938371021998.7688422375402; Thu, 5 Jan 2023 09:06:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTNP-0001wf-E4; Thu, 05 Jan 2023 11:46:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMI-0000m9-0B for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:50 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTMD-0007T2-Tq for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:49 -0500 Received: by mail-wm1-x32b.google.com with SMTP id i17-20020a05600c355100b003d99434b1cfso1787162wmq.1 for ; Thu, 05 Jan 2023 08:44:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WdsQkzgPH1wTahyKLQ7ZmQKEPjf3NSnJoH3HoNNy3yI=; b=X6wgz+5PwOZZOdDqD0dokqIsnOAe+JlN75+szGkbO2yzXSBlMujbXS/reBh6/Kt3Hb DyeclxgD3oxKcPcU71NtsBiQQPBdjYLUvyaY9gsZm97OAj1vNVIeUEjV/lXTA5ngxvQ1 umtwlrGDvOo9QxbCJqujTOIEvhBydGooiu6tGFop9qeP5dcDVRdbEVaRBY2mzFkF688P osFjG+SXUqLFd6nX7eKdI+j7+/7FEXnWrTXVLArVXhO9+3nwZ+L+PruAf+ubLdlgXXsq hmssuBDrhYqEAB+US33/FwC3sP0x5T0dBzBKMFFiIGqnz9/7MI17CCE0T8pZjKREpiiN TcBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WdsQkzgPH1wTahyKLQ7ZmQKEPjf3NSnJoH3HoNNy3yI=; b=vjn+INA6TLNc1hYZstwhCCbvwc9dzBl19sG8BwQXRBGm4pHEPCmrmcgKdIrNPyEQT3 yydWP6glLqM3c3NFI1ALPHskxDTO9C5SHBcVhQV0ftm8ZhjwbYafQ5o3roLfUAS5kt4e UOE+BUepF8sKe68ejzeWOMk2ZxiTSQRTUuZojtiaH/geyVgE8cqSm/VT5jhJ7DX5kkOM qCDBkavi+ceqPjcqWvG2oORvwk/ygWXxcDlZyiFffJ/TC05JkqP4RCV9OmVWEM8iNKfF VR06RWbM8QAKA3+RajBou+v+GC4E5OHWyhE9VTrbpBtaQN7M1cGTVLuNEPJpDIiycxzJ Fa8Q== X-Gm-Message-State: AFqh2kotW0gqm3q7aCKzoiHCnJ6iFu75mXbkZt/EUhrNEgnZguRb4EzM 45q3l7BHjI3thFQ4kz4P5BF+0TYHR6XfsuKN X-Google-Smtp-Source: AMrXdXtw8k6gZ7VUmVZhTVbj6zIPdax9X74G4hI67xuETI+uYmHc097rFtb0jlaIeJrwgV6On0r8OQ== X-Received: by 2002:a7b:cd0d:0:b0:3d3:5c7d:a5f5 with SMTP id f13-20020a7bcd0d000000b003d35c7da5f5mr36658213wmj.16.1672937084211; Thu, 05 Jan 2023 08:44:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/34] i.MX7D: Connect GPT timers to IRQ Date: Thu, 5 Jan 2023 16:44:13 +0000 Message-Id: <20230105164417.3994639-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938372519100004 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois So far the GPT timers were unable to raise IRQs to the processor. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 5 +++++ hw/arm/fsl-imx7.c | 10 ++++++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 1c5fa6fd676..50f19d8db04 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -235,6 +235,11 @@ enum FslIMX7IRQs { FSL_IMX7_USB2_IRQ =3D 42, FSL_IMX7_USB3_IRQ =3D 40, =20 + FSL_IMX7_GPT1_IRQ =3D 55, + FSL_IMX7_GPT2_IRQ =3D 54, + FSL_IMX7_GPT3_IRQ =3D 53, + FSL_IMX7_GPT4_IRQ =3D 52, + FSL_IMX7_WDOG1_IRQ =3D 78, FSL_IMX7_WDOG2_IRQ =3D 79, FSL_IMX7_WDOG3_IRQ =3D 10, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index cc6fdb9373f..146bb559bbc 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -219,9 +219,19 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) FSL_IMX7_GPT4_ADDR, }; =20 + static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] =3D { + FSL_IMX7_GPT1_IRQ, + FSL_IMX7_GPT2_IRQ, + FSL_IMX7_GPT3_IRQ, + FSL_IMX7_GPT4_IRQ, + }; + s->gpt[i].ccm =3D IMX_CCM(&s->ccm); sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[= i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + FSL_IMX7_GPTn_IRQ[i])); } =20 for (i =3D 0; i < FSL_IMX7_NUM_GPIOS; i++) { --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938424; cv=none; d=zohomail.com; s=zohoarc; b=RRFxsZINBhLB5ZW7vOnh7JgjwezWuXTUHQHQlgvtvCePMajSJyY8BzEKFDlKtWIMh/0QfGiNZ/HpKNfvR1NHOaWx1cFVByXYTplrfieqfSsi2K051IUyiNZVZXZ10k2YxJXXvtew7LIRmsC8KDOaeq4C1Bo6305Gp8dVLhKRCPo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672938424; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0uX5qcSlWxkIv6XFcZG4vEVBT2aV30N7UKGbpRe6IA0=; b=RboSKEBn6mao9m6Vu5FA03cWPlv2Rjuqve4JqmTQ4/sbJOUbMJgM5RMWTTwSBDWPPTEvIVOuDQO6NsVDVqluEs2T27N6NfNMI7rbsMnMlMGT8fmdREcgJWLzcF6S60XdV7UHbGMPXjlUi7qZzWPHID/q6USP2arhB1Qna9XfumA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167293842437226.47237302091014; Thu, 5 Jan 2023 09:07:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMf-0001M0-Ci; Thu, 05 Jan 2023 11:45:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMJ-0000oG-Dg for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:51 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTMF-0007Pb-1r for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:51 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m3so19556073wmq.0 for ; Thu, 05 Jan 2023 08:44:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0uX5qcSlWxkIv6XFcZG4vEVBT2aV30N7UKGbpRe6IA0=; b=o+90ALjoozOnofJKn5PdDOdOKiJRyPHwHIvFdCUomRnMG8Jg/3KyxxBOqWdooRQiwp 3+0fjKYSNcVJdw4dvJnmGuHatud6KE0nlqAZb18wyvKyx7uHG504M4qjmiVIAeqWnWnH YPZlhF+RYsNHSOQi9/dcTOnhW77uzWWi7TtjdmUBSwIniCvt+8kAvpiPX40p5hmzU5e5 9Q+VLKwNM4RdyTFDxzz4k2mapbCZw93n2dA89MqRxo8gxQMlo1wNjwA69bhhmPaX/+l0 aEcEJw8b1RLcu8elRX+rXwlwBcZJ4gb4I4VmOrFtdbZFjMC4JigFn+BnMTd16VBqXtEE YvNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0uX5qcSlWxkIv6XFcZG4vEVBT2aV30N7UKGbpRe6IA0=; b=FD2A6Sfm5mIqJ43iAIzhTKEzr0r9hv32GL3nTPfhoOQO/jopjoDQ3wvK2JC7XFUgdt NsZE+GefTHxCcHu78hZA5NrguWYl7Te4cJiJcs9XWXoj3E/P9yjfSMtV8iZTA+g+SCYb wSZepFPY2fhemVkiACPqbLMcuw1q61x6OS6Ad3EaxBYg2pYbdYltx+Bk9NzZmo1XHRG5 S47B+RP686txZvTz1D/H9Z3aZ/7ikDIFn4CJhNzNq9Q5NaNmZKO0bcqxOOKe1k54g0qc rkmYz/7EgG10cvbKNW9bzCbAzNdD8DG3bwh9McMIwc/K71PdB3s5W3hNvslbk29CgIrr Am/Q== X-Gm-Message-State: AFqh2krb8FXt1CxO65SG1TqVlzYCSFjd96XJZz5nCX+2VsGMCQs+Z824 mUW/sxxLHBbdCPVYhDawuwnTDe1VQR6JdGis X-Google-Smtp-Source: AMrXdXteTzm5D3Cr9rSEGmEjVilx7vzd/oaGJfDqxIz7aI2MpHrNrsxZKqTHEGFAsT+ZUFrXuPoMyw== X-Received: by 2002:a05:600c:1f11:b0:3d0:57ea:319c with SMTP id bd17-20020a05600c1f1100b003d057ea319cmr36874405wmb.13.1672937084993; Thu, 05 Jan 2023 08:44:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/34] i.MX7D: Compute clock frequency for the fixed frequency clocks. Date: Thu, 5 Jan 2023 16:44:14 +0000 Message-Id: <20230105164417.3994639-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938426377100003 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois CCM derived clocks will have to be added later. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx7_ccm.c | 49 +++++++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c index 075159e497b..f135ec7b7e4 100644 --- a/hw/misc/imx7_ccm.c +++ b/hw/misc/imx7_ccm.c @@ -16,6 +16,10 @@ #include "hw/misc/imx7_ccm.h" #include "migration/vmstate.h" =20 +#include "trace.h" + +#define CKIH_FREQ 24000000 /* 24MHz crystal input */ + static void imx7_analog_reset(DeviceState *dev) { IMX7AnalogState *s =3D IMX7_ANALOG(dev); @@ -219,16 +223,43 @@ static const VMStateDescription vmstate_imx7_ccm =3D { static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk cloc= k) { /* - * This function is "consumed" by GPT emulation code, however on - * i.MX7 each GPT block can have their own clock root. This means - * that this functions needs somehow to know requester's identity - * and the way to pass it: be it via additional IMXClk constants - * or by adding another argument to this method needs to be - * figured out + * This function is "consumed" by GPT emulation code. Some clocks + * have fixed frequencies and we can provide requested frequency + * easily. However for CCM provided clocks (like IPG) each GPT + * timer can have its own clock root. + * This means we need additionnal information when calling this + * function to know the requester's identity. */ - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n", - TYPE_IMX7_CCM, __func__); - return 0; + uint32_t freq =3D 0; + + switch (clock) { + case CLK_NONE: + break; + case CLK_32k: + freq =3D CKIL_FREQ; + break; + case CLK_HIGH: + freq =3D CKIH_FREQ; + break; + case CLK_IPG: + case CLK_IPG_HIGH: + /* + * For now we don't have a way to figure out the device this + * function is called for. Until then the IPG derived clocks + * are left unimplemented. + */ + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n= ", + TYPE_IMX7_CCM, __func__, clock); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n", + TYPE_IMX7_CCM, __func__, clock); + break; + } + + trace_ccm_clock_freq(clock, freq); + + return freq; } =20 static void imx7_ccm_class_init(ObjectClass *klass, void *data) --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672939064; cv=none; d=zohomail.com; s=zohoarc; b=CsSG85xsx2cOxQEHTMWpGod3YYVB+qqXaKSfC0Vc/T/zM45blWSn7Ji2RAx+G4hM7OAPHtuPANPY87oUtorLc3pr9KxMcMYXvoTpZoSAm2l+hJK/duDs4qdFYAArOPFpL4jEhbyg8Jn4L4SDaC4EDe4ROLFsACNBGD4XwLhBwRE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672939064; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HjXI1ybyBjJZ/wjqPnfmihak0F0npX5WBOx0bgmkSU8=; b=Q1G27SIq9fknGy0tbyOFtxusmt2nVSb6UXofW3NaHsfLZxDslVBKa6IDr3FQBgyHl6Ww5LppCI45rbSI0/D2EyH6qMg7n2yc2UoWWMo9qq1Wo5G8z5CQjW6hg0AKNNAx6auQIcc1S6ZNb/K4aGtI33XVPdTdEL1cB4Iwc+PfDpM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672939064021243.30494225873838; Thu, 5 Jan 2023 09:17:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMg-0001Nu-CR; Thu, 05 Jan 2023 11:45:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMJ-0000oH-Hm for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:51 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTMF-0007Tj-4g for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:51 -0500 Received: by mail-wm1-x332.google.com with SMTP id k26-20020a05600c1c9a00b003d972646a7dso1727997wms.5 for ; Thu, 05 Jan 2023 08:44:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HjXI1ybyBjJZ/wjqPnfmihak0F0npX5WBOx0bgmkSU8=; b=leXeI1/9WEM1c5T5kiTNJp/db6voMAceui3q7C2GThMl7Cg/v2h+PKzRs2tYBKouGD Q7pHDFOw2ioI4+1xwdbAKiQMZPWZ/0C8jkkVMmoMZKlnBfX5sD5cHlcQ0qJGpTtsefKu C1Rwdh92sJBmmF08xc2YBnxclzSZVsoYMngMO7uxiTPmyNmF0LUWj4/AMivKNsfFZqFe VrQxWY9cBFeDmeqn5aewwyP5xCJ2GAOKEN/X3iaZNMy+6MeUQ/WfnD9oF9/Z/l7XLjG7 9apo8bYgfSmY00WmvEnpfbpHnX8FQxMIVu2XzmErgnCkpQOtmbVITse6vexl8Ssqyzl4 79+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HjXI1ybyBjJZ/wjqPnfmihak0F0npX5WBOx0bgmkSU8=; b=u/PV7hnx2sOn6mS85SB4jaRS0T5BMPT8ankg+5GZV6biQK49uLZffEWBzooR/lZJLT /Coqa4Q2LOI4xcFKp7qVRF1vIDPtGDrKVvJ9NXAuPSOIVtI5j0GXt2ze5lMxhmsIUrCI 8e+0vubM87Jkn0rkyDaJ1xZ7rK7k6Kk64hliQ5WbyCIf6XSDRrIauLtRimlN6oblpyPD azqC4Yei7JPCeRLLQM+HaiiDrFVle9lhomCZTG6q6Kxz/M3BLt/Ljg3vu7J2B4iol1VQ fpVUipjDICatXz9eO/Q8EffBhk/QUs6ndFZqlH3/U5u49dSs103r/jL4FOe/cIDpODgB oSBA== X-Gm-Message-State: AFqh2kotapWTNa+xx8U/12iV5qzj6QXs0Bxi6Vn/ViMhv+F6m66LN2bQ T+BswKS+2k7HgiFgs6gcdzZd8fxG4Ta8WeVz X-Google-Smtp-Source: AMrXdXtTyE3s9BXNdZWAFXmddvWdnHIuYwNQQNvZQAZ0GERdjfbGFshfrq9pacUNKxCMSItdGz+4Sg== X-Received: by 2002:a05:600c:3482:b0:3d3:4f56:62e1 with SMTP id a2-20020a05600c348200b003d34f5662e1mr35638336wmq.27.1672937085846; Thu, 05 Jan 2023 08:44:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/34] i.MX6UL: Add a specific GPT timer instance for the i.MX6UL Date: Thu, 5 Jan 2023 16:44:15 +0000 Message-Id: <20230105164417.3994639-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672939066232100001 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source. Signed-off-by: Jean-Christophe Dubois Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/timer/imx_gpt.h | 1 + hw/arm/fsl-imx6ul.c | 2 +- hw/misc/imx6ul_ccm.c | 6 ------ hw/timer/imx_gpt.c | 25 +++++++++++++++++++++++++ 4 files changed, 27 insertions(+), 7 deletions(-) diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h index ff5c8a351a0..5a1230da35e 100644 --- a/include/hw/timer/imx_gpt.h +++ b/include/hw/timer/imx_gpt.h @@ -78,6 +78,7 @@ #define TYPE_IMX25_GPT "imx25.gpt" #define TYPE_IMX31_GPT "imx31.gpt" #define TYPE_IMX6_GPT "imx6.gpt" +#define TYPE_IMX6UL_GPT "imx6ul.gpt" #define TYPE_IMX7_GPT "imx7.gpt" =20 #define TYPE_IMX_GPT TYPE_IMX25_GPT diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index f1897123294..d88d6cc1c5f 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -81,7 +81,7 @@ static void fsl_imx6ul_init(Object *obj) */ for (i =3D 0; i < FSL_IMX6UL_NUM_GPTS; i++) { snprintf(name, NAME_SIZE, "gpt%d", i); - object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT); + object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT); } =20 /* diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c index a65d0314556..e01bb68ac72 100644 --- a/hw/misc/imx6ul_ccm.c +++ b/hw/misc/imx6ul_ccm.c @@ -522,12 +522,6 @@ static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMS= tate *dev, IMXClk clock) case CLK_32k: freq =3D CKIL_FREQ; break; - case CLK_HIGH: - freq =3D CKIH_FREQ; - break; - case CLK_HIGH_DIV: - freq =3D CKIH_FREQ / 8; - break; default: qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n", TYPE_IMX6UL_CCM, __func__, clock); diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 80b83026399..7222b1b3874 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -115,6 +115,17 @@ static const IMXClk imx6_gpt_clocks[] =3D { CLK_HIGH, /* 111 reference clock */ }; =20 +static const IMXClk imx6ul_gpt_clocks[] =3D { + CLK_NONE, /* 000 No clock source */ + CLK_IPG, /* 001 ipg_clk, 532MHz*/ + CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ + CLK_EXT, /* 011 External clock */ + CLK_32k, /* 100 ipg_clk_32k */ + CLK_NONE, /* 101 not defined */ + CLK_NONE, /* 110 not defined */ + CLK_NONE, /* 111 not defined */ +}; + static const IMXClk imx7_gpt_clocks[] =3D { CLK_NONE, /* 000 No clock source */ CLK_IPG, /* 001 ipg_clk, 532MHz*/ @@ -539,6 +550,13 @@ static void imx6_gpt_init(Object *obj) s->clocks =3D imx6_gpt_clocks; } =20 +static void imx6ul_gpt_init(Object *obj) +{ + IMXGPTState *s =3D IMX_GPT(obj); + + s->clocks =3D imx6ul_gpt_clocks; +} + static void imx7_gpt_init(Object *obj) { IMXGPTState *s =3D IMX_GPT(obj); @@ -566,6 +584,12 @@ static const TypeInfo imx6_gpt_info =3D { .instance_init =3D imx6_gpt_init, }; =20 +static const TypeInfo imx6ul_gpt_info =3D { + .name =3D TYPE_IMX6UL_GPT, + .parent =3D TYPE_IMX25_GPT, + .instance_init =3D imx6ul_gpt_init, +}; + static const TypeInfo imx7_gpt_info =3D { .name =3D TYPE_IMX7_GPT, .parent =3D TYPE_IMX25_GPT, @@ -577,6 +601,7 @@ static void imx_gpt_register_types(void) type_register_static(&imx25_gpt_info); type_register_static(&imx31_gpt_info); type_register_static(&imx6_gpt_info); + type_register_static(&imx6ul_gpt_info); type_register_static(&imx7_gpt_info); } =20 --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672938397; cv=none; d=zohomail.com; s=zohoarc; b=HUJEgVz28ink5kYWAVfqqP2cAM0zcrL4gzQ6PvfX9iodzK7x1LkbKjosCnhfAJvtRT/+Dqn0xhz9Ntc0WGzGyzEQjVT/XYoNR/sFiHba+GAt/lCmTsqPHg+9VMbj9ruajmiBjJJ80DwyZYZpY7Ma/pMLHiUDzX1u1b8k9pYrw6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672938397; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U/noDqf89C9CE4dX2bLJg9toJeQoQFfDbIKZFjOUmRk=; b=fEDlrTWdxtqgzJmU1vam/CIqjHpAdKCa0DFxgQyD5Qc8Rr4kMK6K7saDAJHnbfpg462aY03WB3fMB9cwaAY7gg+KoosRAr7WpdibLbu9E795WxEJly+GClD9AEP6QqHcns4292NSTVxRcYMcdWzH+GZc8EDOaT1fkL4z8ghqYlk= ARC-Authentication-Results: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U/noDqf89C9CE4dX2bLJg9toJeQoQFfDbIKZFjOUmRk=; b=cQspyqTg9+5Gy5xoOBRy4F4PPYqREgACYNyCW6DV8vDkYc8y9m6FiAFqaVN4JdMZs4 TE9SybAWg3T5x/i8/8p78YY1zZoEVeqsmfYLL7WqDhxR+23hUfPQQ4Bc2bFTcITOWpx9 pBBkELAx2Je9LxAcmuXej86BaTXY/gHY6EA0DjoPDCxLg3hbDmLuLwX4uMsgTNuvN4oO ZDYHedyvC4FCSGHKJfEOg759qQ7umAvITCwtyriq5/TqRhGFN5XRlfYJxFpDp/BncLUo 7hMgDqAB9e91QcKPFgKWRbwgY3gmuvWLg/xrUdQONTP2TmqKY83oJ7qjfx9xu04MHMpG ucFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U/noDqf89C9CE4dX2bLJg9toJeQoQFfDbIKZFjOUmRk=; b=bWinC4S03egB7dvSL5J65pzDdcRuRdLjvXdFLesTDSeBDrw2DGoAkWnpaQgBd1da09 5Bbfz3zV5vvE0clhtoem6Dxx3bYA3O7g+nx/id/IK8n4FttFdREWG1t3l/G6JusDiDJB gAlXAYpkEUX2XPfrQRkbHrOgKYeLK2OHOIM+woncMiM7OV20VS4Cup35SIBCPGfWHIfU HukR4mg+byH1SqZvg6hV6SHZA7c1yWADhL1Qx9Heyc82GTd+C+e2K/Yuj/2uflthPCWe 4LwRO2wlhdYd9R7pfB5ivenXWtS6J/vJFI2ualt/fGIRXTadEFVbIWg4v2dF/1U6viM2 wZxA== X-Gm-Message-State: AFqh2kqKse+XCMvtol0IPsIfmfdD9PhzMOAL6p94mI7nP0g3gSX6lBDL xYA1Wi9TwXgGO6TZWi67wWylM8x9p5wG+zLk X-Google-Smtp-Source: AMrXdXscVtjk4hAw35RjcwhzD08a1osP2J51OqSn88BxzjK3XPi60TfzxRypAeaxjctKrqcICThvjA== X-Received: by 2002:a05:600c:2247:b0:3d3:4b1a:6ff9 with SMTP id a7-20020a05600c224700b003d34b1a6ff9mr37348699wmm.26.1672937086730; Thu, 05 Jan 2023 08:44:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/34] i.MX7D: Connect IRQs to GPIO devices. Date: Thu, 5 Jan 2023 16:44:16 +0000 Message-Id: <20230105164417.3994639-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672938398307100005 Content-Type: text/plain; charset="utf-8" From: Jean-Christophe Dubois IRQs were not associated to the various GPIO devices inside i.MX7D. This patch brings the i.MX7D on par with i.MX6. Signed-off-by: Jean-Christophe Dubois Message-id: 20221226101418.415170-1-jcd@tribudubois.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 15 +++++++++++++++ hw/arm/fsl-imx7.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 50f19d8db04..4e5e0718648 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -240,6 +240,21 @@ enum FslIMX7IRQs { FSL_IMX7_GPT3_IRQ =3D 53, FSL_IMX7_GPT4_IRQ =3D 52, =20 + FSL_IMX7_GPIO1_LOW_IRQ =3D 64, + FSL_IMX7_GPIO1_HIGH_IRQ =3D 65, + FSL_IMX7_GPIO2_LOW_IRQ =3D 66, + FSL_IMX7_GPIO2_HIGH_IRQ =3D 67, + FSL_IMX7_GPIO3_LOW_IRQ =3D 68, + FSL_IMX7_GPIO3_HIGH_IRQ =3D 69, + FSL_IMX7_GPIO4_LOW_IRQ =3D 70, + FSL_IMX7_GPIO4_HIGH_IRQ =3D 71, + FSL_IMX7_GPIO5_LOW_IRQ =3D 72, + FSL_IMX7_GPIO5_HIGH_IRQ =3D 73, + FSL_IMX7_GPIO6_LOW_IRQ =3D 74, + FSL_IMX7_GPIO6_HIGH_IRQ =3D 75, + FSL_IMX7_GPIO7_LOW_IRQ =3D 76, + FSL_IMX7_GPIO7_HIGH_IRQ =3D 77, + FSL_IMX7_WDOG1_IRQ =3D 78, FSL_IMX7_WDOG2_IRQ =3D 79, FSL_IMX7_WDOG3_IRQ =3D 10, diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 146bb559bbc..afc74807990 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -245,8 +245,37 @@ static void fsl_imx7_realize(DeviceState *dev, Error *= *errp) FSL_IMX7_GPIO7_ADDR, }; =20 + static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] =3D { + FSL_IMX7_GPIO1_LOW_IRQ, + FSL_IMX7_GPIO2_LOW_IRQ, + FSL_IMX7_GPIO3_LOW_IRQ, + FSL_IMX7_GPIO4_LOW_IRQ, + FSL_IMX7_GPIO5_LOW_IRQ, + FSL_IMX7_GPIO6_LOW_IRQ, + FSL_IMX7_GPIO7_LOW_IRQ, + }; + + static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] =3D { + FSL_IMX7_GPIO1_HIGH_IRQ, + FSL_IMX7_GPIO2_HIGH_IRQ, + FSL_IMX7_GPIO3_HIGH_IRQ, + FSL_IMX7_GPIO4_HIGH_IRQ, + FSL_IMX7_GPIO5_HIGH_IRQ, + FSL_IMX7_GPIO6_HIGH_IRQ, + FSL_IMX7_GPIO7_HIGH_IRQ, + }; + sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADD= R[i]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, + FSL_IMX7_GPIOn_ADDR[i]); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + FSL_IMX7_GPIOn_LOW_IRQ[i])); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + FSL_IMX7_GPIOn_HIGH_IRQ[i])); } =20 /* --=20 2.25.1 From nobody Wed Feb 11 04:36:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1672937732; cv=none; d=zohomail.com; s=zohoarc; b=TBqlRKo5idw5tdfQjs1u0/VfeXr9msn5Wz7vgm8tIqjmF/p5jZ5C5qfOVfxrgrHf3Sq6HUfaiu3MG7oJ0f67YtlgqyAmkQF2xTOnaXhO/GiaOpcrtWEhPivNdI52e/bP1mKw2b4CluzG/ICgcsfwFQNaRe5THco7/1P/o9MRCxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672937732; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=33dG/KwajZrq9i+KPj0Q5eXpSM4wjc/WwsMuu9dKq4E=; b=KnIT21K7A98ixAffWU4Q6ato0wQEtj5cKUZyPRyYMAWtaSiPo+/7VFvQbUTK16gmvtzVUSMhIejSHujD+NyeXqUBHDm2Z0P+3E1gHnq4BUN9ccmPm1jCCuWYHDPnIwa8p5l79Li/LdggdDVfAW27QzskG8I706lQ1jI8dPVmwOI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1672937732039675.9905581526627; Thu, 5 Jan 2023 08:55:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDTMh-0001Rs-Vu; Thu, 05 Jan 2023 11:45:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTMJ-0000pA-Ol for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:52 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTMH-0007Mj-OG for qemu-devel@nongnu.org; Thu, 05 Jan 2023 11:44:51 -0500 Received: by mail-wm1-x335.google.com with SMTP id g10so14661594wmo.1 for ; Thu, 05 Jan 2023 08:44:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id hg9-20020a05600c538900b003cf71b1f66csm3055547wmb.0.2023.01.05.08.44.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:44:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=33dG/KwajZrq9i+KPj0Q5eXpSM4wjc/WwsMuu9dKq4E=; b=VKNL61CwUWs3h9VqU/Dbd+x5sXmEWRnn7PJwWPHV4Z+Osgkau1oJBvTE5g7g0ZHIuO oXMCrmRImNZfmBh4Z5+ESDUKldnMmRg7MRgzUavAYoGovksBQlnuhE0jcBcmtO/kDrzP xdGw2+Jyd/xrt9yW3noSI4j+yvIJVL3Co4DvaoKVOxcgvVvXHT7togHQymyYVZE3LyPC 5crSx+1Vj7xvZLHH92Mrycg6liUPRS7BcEK9Q7Ezow0BsXSxi0/OPK0jX/QQEDhmzZcf 6QCtAQmAA8qbC74O6mXWn/2P9OsFSh6XuBZZL8Kc2/Po+wwvgHZTk7P/v2iRns5THcaY NSWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=33dG/KwajZrq9i+KPj0Q5eXpSM4wjc/WwsMuu9dKq4E=; b=f0JWadfNPN+1rET+9HXMOxV60ZGFFDzF7oRzfyKghNfPFUrOplLf0D0+T1h2uT4EEF mrpWe+6pzZRjrn5MCV/jLdd3DWAbsm4nWDR/xtoQvkZWzUpU/Ih1BidXm31quZTMhMqP OuWrFO0obJ0B9/YDegyC479xBO8EgBx/vi2uynaLNg5Q21uOXPeBUuuxH2P8Pt5DpYOx lWf/+5NFfsgugrZ1tK9V1KdSn53wfsuJ0y27DLBwroFIQPkOgWNXDVXCtECBHJ9dVumq yCs/neqWkwcWx+HvKjqMRAiq89DN+0oPf29NHJb6bFXTlAHptJRTpXxw+wOrUaR74dUy YztA== X-Gm-Message-State: AFqh2kqxz2zqIMtJRzcCkCpAd7jenQ+TKMS1w11flve0B4hjLE/9AU2H C3gRO5EWtOr52eATnofeWxgRDFnbO9P4M01T X-Google-Smtp-Source: AMrXdXuajnAFRWrCO3D7xXJ7q/yI1vKXZtSmsHmkruTdOq1niiD3diSaMZbQhsuLJBTv04ASwy0sxQ== X-Received: by 2002:a05:600c:3d0e:b0:3d3:4aa6:4fd0 with SMTP id bh14-20020a05600c3d0e00b003d34aa64fd0mr36932398wmb.6.1672937087484; Thu, 05 Jan 2023 08:44:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/34] hw/net: Fix read of uninitialized memory in imx_fec. Date: Thu, 5 Jan 2023 16:44:17 +0000 Message-Id: <20230105164417.3994639-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105164417.3994639-1-peter.maydell@linaro.org> References: <20230105164417.3994639-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672937733629100003 Content-Type: text/plain; charset="utf-8" From: Stephen Longfield Size is used at lines 1088/1188 for the loop, which reads the last 4 bytes from the crc_ptr so it does need to get increased, however it shouldn't be increased before the buffer is passed to CRC computation, or the crc32 function will access uninitialized memory. This was pointed out to me by clg@kaod.org during the code review of a similar patch to hw/net/ftgmac100.c Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b Signed-off-by: Stephen Longfield Reviewed-by: Patrick Venture Message-id: 20221221183202.3788132-1-slongfield@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/imx_fec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 8c11b237de7..c862d965930 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1068,9 +1068,9 @@ static ssize_t imx_fec_receive(NetClientState *nc, co= nst uint8_t *buf, return 0; } =20 - /* 4 bytes for the CRC. */ - size +=3D 4; crc =3D cpu_to_be32(crc32(~0, buf, size)); + /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr.= */ + size +=3D 4; crc_ptr =3D (uint8_t *) &crc; =20 /* Huge frames are truncated. */ @@ -1164,9 +1164,9 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, return 0; } =20 - /* 4 bytes for the CRC. */ - size +=3D 4; crc =3D cpu_to_be32(crc32(~0, buf, size)); + /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr.= */ + size +=3D 4; crc_ptr =3D (uint8_t *) &crc; =20 if (shift16) { --=20 2.25.1