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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.18.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:18:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RTwMqyhlkCLAE14wwdpweGikJKU6H9FwK5bch9gSJbk=; b=Kr6/wqmjMyOFMK+cIZ3rJrAxGCjuU1irdVP0/ilPhumrH4kZ9nNALIn6ds/jgmPmLJ mA8qu1P4ES3AWCIt8mssLHqBWkf/pzzaZOT1seOtZy7Ekm9zZwUPEyBmB6Hv5xYTiNX7 MbqpKF3gLlptyk+1PC+ah3om0GrJD7WrsJk1ORiMFChojAvAPEiapWeMKhZtwqPeYkXM J+DD5dtdbGjBx1l87asd7hDWH7LGW2p90Zc+gsvHwAMlkZIe+o1t9O/OOgzOOm75D6DW LvImS/cHRA1+I4Sgwfvy4Qx1g16M/aQq6u2vrkvl55raRK2EcvRyZ7B/aj0ze9aXzEif mbQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RTwMqyhlkCLAE14wwdpweGikJKU6H9FwK5bch9gSJbk=; b=dTfup/GAwxWUHpgUBVH0tRwQOu1YzhPi9m9JhfqXyd/5R7FgBt4tVnqo0XHXHPZm3p ucP3q9mHguMJUV3ZSPqy50/oSrOOJwUwdkab+jfPt8R8884qfzsvl/p61D1EbemEHF0t kISkMx/U6wwhzn/WFpMOWZA7SI2bcElg7Y6JwUcHldBWy8pRqA7+6Zcz2qcUagdDaDVS p60vMy4BPkH7EPJDyqevs64YRcJY2q4NZ+IvVjXPVhaAx8trnN1wlH288Mk44LWCmbLI YjXHDaza93iZpX+25eIZICOejIYucghy+Qf0efxbnufQoVptqiHIE/Icr86hBVMSRSGT bbhg== X-Gm-Message-State: AFqh2ko5UjFOhoZWPTpLTyWxVMZWQiB1NoDiN3bU77sX2ps6n6SS9Fgb MNLv/+Ff4i2yIJxKpd+qttyDGUzDhw8JxBVTmY4= X-Google-Smtp-Source: AMrXdXuU5MUCmBWQmURljRj9y6J/AOY4Bq3FTZ2GmOXAa/P3uEu8X48b4+OaF2I+pEIYcGT1PtXDyw== X-Received: by 2002:ac8:1382:0:b0:3a9:8b48:f8f with SMTP id h2-20020ac81382000000b003a98b480f8fmr63259237qtj.67.1672769919600; Tue, 03 Jan 2023 10:18:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 37/40] target/arm: Move "cfgend" to class property Date: Tue, 3 Jan 2023 10:16:43 -0800 Message-Id: <20230103181646.55711-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1672770498179100006 Content-Type: text/plain; charset="utf-8" Remove the cfgend variable entirely and reuse the property accessor functions created for reset-hivecs. This removes the last setting of cpu->reset_sctlr, to we can remove that as well, using only the class value. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 8 -------- target/arm/cpu.c | 26 ++++++++++++-------------- target/arm/helper.c | 4 ++-- 3 files changed, 14 insertions(+), 24 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5921660d86..23070a9c25 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -954,7 +954,6 @@ struct ArchCPU { uint32_t revidr; uint32_t reset_fpsid; uint64_t ctr; - uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; @@ -987,13 +986,6 @@ struct ArchCPU { int gic_vprebits; /* number of virtual preemption bits */ int gic_pribits; /* number of physical priority bits */ =20 - /* Whether the cfgend input is high (i.e. this CPU should reset into - * big-endian mode). This setting isn't used directly: instead it mod= ifies - * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on= the - * architecture version. - */ - bool cfgend; - QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3262e86e61..17d08e0e9c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1222,7 +1222,6 @@ static void arm_cpu_initfn(Object *obj) cpu->revidr =3D acc->revidr; cpu->id_afr0 =3D acc->id_afr0; cpu->reset_fpsid =3D acc->reset_fpsid; - cpu->reset_sctlr =3D acc->reset_sctlr; cpu->reset_auxcr =3D acc->reset_auxcr; cpu->pmsav7_dregion =3D acc->pmsav7_dregion; cpu->sau_sregion =3D acc->sau_sregion; @@ -1280,9 +1279,6 @@ static void arm_cpu_initfn(Object *obj) static Property arm_cpu_reset_cbar_property =3D DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); =20 -static Property arm_cpu_cfgend_property =3D - DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); - static Property arm_cpu_has_vfp_property =3D DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); =20 @@ -1442,8 +1438,6 @@ static void arm_cpu_post_init(Object *obj) &cpu->psci_conduit, OBJ_PROP_FLAG_READWRITE); =20 - qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); - if (kvm_enabled()) { kvm_arm_add_vcpu_properties(obj); } @@ -1771,14 +1765,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 - if (cpu->cfgend) { - if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { - cpu->reset_sctlr |=3D SCTLR_EE; - } else { - cpu->reset_sctlr |=3D SCTLR_B; - } - } - if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); } @@ -2306,6 +2292,18 @@ static void arm_cpu_leaf_class_init(ObjectClass *oc,= void *data) } =20 #ifndef CONFIG_USER_ONLY + /* + * When the cfgend input is high, the CPU should reset into + * big-endian mode. Modify the reset_sctlr value to have SCTLR_B + * or SCTLR_EE set, depending on the architecture version. + */ + class_property_add(oc, "cfgend", "bool", NULL, + arm_class_prop_get_sctlrbit, + arm_class_prop_set_sctlrbit, + (void *)(uintptr_t) + (arm_class_feature(acc, ARM_FEATURE_V7) + ? SCTLR_EE : SCTLR_B)); + if (arm_class_feature(acc, ARM_FEATURE_GENERIC_TIMER)) { class_property_add(oc, "cntfrq", "uint64", NULL, arm_class_prop_uint64_ofs, diff --git a/target/arm/helper.c b/target/arm/helper.c index 67d32c2e59..e414fa11dd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7995,7 +7995,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL3_RW, .raw_writefn =3D raw_write, .writefn =3D sctlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), - .resetvalue =3D cpu->reset_sctlr }, + .resetvalue =3D acc->reset_sctlr }, }; =20 define_arm_cp_regs(cpu, el3_regs); @@ -8331,7 +8331,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, - .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, + .writefn =3D sctlr_write, .resetvalue =3D acc->reset_sctlr, .raw_writefn =3D raw_write, }; if (arm_feature(env, ARM_FEATURE_XSCALE)) { --=20 2.34.1