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c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ke5Y/zE7+LRZE2T1AS2NN+TQGmtCytDxNNS64y+D96U=; b=AiKqYZrt4TuQ5ihD6D3mR3vgq1VFv9Mip5MMsUdR6EJ2URZB7ozFIeD41qeo+25zsabq 85PJ1HliIdPXqDpa7hvyzMQUG+SoAQ/0+DO3tRKS1Qj1OTyaF5cFx2+gUWj8WMsh5XG9 ODRlQVod943u3YW71I2chIEw4dd8gPCqq22c2JjOOOQONOvCZ8Fy96td0ZplOexBPtgt MdNTvnmI+oMC/VmvDLNtfYhU0gLd+PBupWbuhKlGmSZWAZi/mW6lj7YzCIpOMK0oBybs URg1CrsU/FEaOqHcctsTSCN0xPF/I5DYGa5mgM+4FduUyMkxIzlLUa1w9jJTyqncMU2C jA== From: Mukilan Thiyagarajan To: , , CC: , , , Mukilan Thiyagarajan Subject: [PATCH v2 2/2] target/hexagon: rename aliased register HEX_REG_P3_0 Date: Thu, 29 Dec 2022 14:50:06 +0530 Message-ID: <20221229092006.10709-3-quic_mthiyaga@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221229092006.10709-1-quic_mthiyaga@quicinc.com> References: <20221229092006.10709-1-quic_mthiyaga@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HW1676Ppt6Id4N66sGR1WAKgUcrXDl_F X-Proofpoint-ORIG-GUID: HW1676Ppt6Id4N66sGR1WAKgUcrXDl_F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-29_04,2022-12-28_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 spamscore=0 mlxscore=0 mlxlogscore=942 phishscore=0 bulkscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212290077 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=quic_mthiyaga@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672305695806000003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch renames the identifier of the 32bit register HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED. This change is to intended to provide some warning that HEX_REG_P3_0 is an aliased register which has multiple representations in CPU state and therefore might require special handling in some contexts. The hope is to prevent accidental misuse of this register e.g the issue reported for the signals tests failure [here][1]. [1]: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html Signed-off-by: Mukilan Thiyagarajan Reviewed-by: Taylor Simpson --- target/hexagon/cpu.c | 6 +++--- target/hexagon/genptr.c | 12 ++++++------ target/hexagon/hex_regs.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 658ca4ff78..807037c586 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -86,7 +86,7 @@ static target_ulong adjust_stack_ptrs(CPUHexagonState *en= v, target_ulong addr) return addr; } =20 -/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */ +/* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */ static target_ulong read_p3_0(CPUHexagonState *env) { int32_t control_reg =3D 0; @@ -102,7 +102,7 @@ static void print_reg(FILE *f, CPUHexagonState *env, in= t regnum) { target_ulong value; =20 - if (regnum =3D=3D HEX_REG_P3_0) { + if (regnum =3D=3D HEX_REG_P3_0_ALIASED) { value =3D read_p3_0(env); } else { value =3D regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) @@ -198,7 +198,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f,= int flags) print_reg(f, env, HEX_REG_M0); print_reg(f, env, HEX_REG_M1); print_reg(f, env, HEX_REG_USR); - print_reg(f, env, HEX_REG_P3_0); + print_reg(f, env, HEX_REG_P3_0_ALIASED); print_reg(f, env, HEX_REG_GP); print_reg(f, env, HEX_REG_UGP); print_reg(f, env, HEX_REG_PC); diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 6cf2e0ed43..66a968c884 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -163,7 +163,7 @@ static inline void gen_read_p3_0(TCGv control_reg) =20 /* * Certain control registers require special handling on read - * HEX_REG_P3_0 aliased to the predicate registers + * HEX_REG_P3_0_ALIASED aliased to the predicate registers * -> concat the 4 predicate registers together * HEX_REG_PC actual value stored in DisasContext * -> assign from ctx->base.pc_next @@ -173,7 +173,7 @@ static inline void gen_read_p3_0(TCGv control_reg) static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num, TCGv dest) { - if (reg_num =3D=3D HEX_REG_P3_0) { + if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) { gen_read_p3_0(dest); } else if (reg_num =3D=3D HEX_REG_PC) { tcg_gen_movi_tl(dest, ctx->base.pc_next); @@ -194,7 +194,7 @@ static inline void gen_read_ctrl_reg(DisasContext *ctx,= const int reg_num, static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg= _num, TCGv_i64 dest) { - if (reg_num =3D=3D HEX_REG_P3_0) { + if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) { TCGv p3_0 =3D tcg_temp_new(); gen_read_p3_0(p3_0); tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]); @@ -238,7 +238,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv cont= rol_reg) =20 /* * Certain control registers require special handling on write - * HEX_REG_P3_0 aliased to the predicate registers + * HEX_REG_P3_0_ALIASED aliased to the predicate registers * -> break the value across 4 predicate registe= rs * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext * -> clear the changes @@ -246,7 +246,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv cont= rol_reg) static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num, TCGv val) { - if (reg_num =3D=3D HEX_REG_P3_0) { + if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) { gen_write_p3_0(ctx, val); } else { gen_log_reg_write(reg_num, val); @@ -266,7 +266,7 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx= , int reg_num, static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num, TCGv_i64 val) { - if (reg_num =3D=3D HEX_REG_P3_0) { + if (reg_num =3D=3D HEX_REG_P3_0_ALIASED) { TCGv val32 =3D tcg_temp_new(); tcg_gen_extrl_i64_i32(val32, val); gen_write_p3_0(ctx, val32); diff --git a/target/hexagon/hex_regs.h b/target/hexagon/hex_regs.h index a63c2c0fd5..bddfc28021 100644 --- a/target/hexagon/hex_regs.h +++ b/target/hexagon/hex_regs.h @@ -58,7 +58,7 @@ enum { HEX_REG_LC0 =3D 33, HEX_REG_SA1 =3D 34, HEX_REG_LC1 =3D 35, - HEX_REG_P3_0 =3D 36, + HEX_REG_P3_0_ALIASED =3D 36, HEX_REG_M0 =3D 38, HEX_REG_M1 =3D 39, HEX_REG_USR =3D 40, --=20 2.17.1