From nobody Tue Sep 16 21:36:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1672262137; cv=none; d=zohomail.com; s=zohoarc; b=jXtddbEL0S602iWShbYkKzHxBL4VN2It9LoS2n6TZOqyoDr9obV6WdIVOiChOQ1/JHDxr42kAeBzmaolSy4JpMLDTzVjGpLx/wMdy9ne2ySqP64UNEBeTtwnTY2nbDh58+5wXd7z7x7KkrJB4Oh/VaGbitFYYdTjYNBl+CQjqc4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672262137; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oVJFKsp59cwVp6y3vI3ISc2HPHZR9ucnLhs9QSRVrN0=; b=TJRKiKTqoY0Nzr95aoSSGv3R4+28KHeS6uXFTT3JtcMXxSb3d7DzgTbl+nevCrIcDmhUmWpQeSA2Klcbw6ACcvur0EvnH7SAMQ/eeLMQt1Q6d43KaUYxGUBIZjVRm0wJffVGBQZwGDZmMiKuzTsoJkgP0t/Q7Ao5CbjInF8hoUI= ARC-Authentication-Results: i=1; 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Wed, 28 Dec 2022 21:13:28 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 5479F5000A8; Wed, 28 Dec 2022 13:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=oVJFKsp59cwVp6y3vI3ISc2HPHZR9ucnLhs9QSRVrN0=; b=iQUGY70+7Setzi+gRRl2ffyiDTK9BYGanw/azRvwnE+hMfzAafofP0nbQ8njfdZu044j tVoWzTC3vj0bIKYCLUToMRJrhPt0foalN6AUuhyNc8/8ihKx+yA6qjLQRJw0Hblbu2r8 1AubowqB/Q9135XfLEg28dGNNKjXWbZQoFvibWEXokN/gg/yEWJ+hGNMr2vitbDPydHZ tu4bqQe7XbUH12DknEBZREFEcraChQxXzQFWLa+fIioea0dsDKxAaLroux0X22CBdIl7 vZGB9Mfmo20j4ugJOQfbwHx7vBk7gSQH+6NTTNa+QyUGPFxxg3s7d+lgt6wmAStyKjyE Xg== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v2 1/6] Hexagon (target/hexagon) Add overrides for jumpr31 instructions Date: Wed, 28 Dec 2022 13:13:19 -0800 Message-Id: <20221228211324.26989-2-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221228211324.26989-1-tsimpson@quicinc.com> References: <20221228211324.26989-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672262138869000001 Add overrides for SL2_jumpr31 Unconditional SL2_jumpr31_t Predicated true (old value) SL2_jumpr31_f Predicated false (old value) SL2_jumpr31_tnew Predicated true (new value) SL2_jumpr31_fnew Predicated false (new value) Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 13 +++++++++++++ target/hexagon/genptr.c | 8 ++++++++ 2 files changed, 21 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 19697b42a5..3ee530f5d9 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1015,6 +1015,19 @@ #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \ gen_asl_r_r_sat(RdV, RsV, RtV) =20 +#define fGEN_TCG_SL2_jumpr31(SHORTCODE) \ + gen_jumpr(ctx, hex_gpr[HEX_REG_LR]) + +#define fGEN_TCG_SL2_jumpr31_t(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_pred[0]) +#define fGEN_TCG_SL2_jumpr31_f(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_NE, hex_pred[0]) + +#define fGEN_TCG_SL2_jumpr31_tnew(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_EQ, hex_new_pred_value[0]) +#define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \ + gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0]) + /* Floating point */ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ gen_helper_conv_sf2df(RddV, cpu_env, RsV) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 6cf2e0ed43..ee67cb0069 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -553,6 +553,14 @@ static void gen_cond_jumpr(DisasContext *ctx, TCGv dst= _pc, gen_write_new_pc_addr(ctx, dst_pc, cond, pred); } =20 +static void gen_cond_jumpr31(DisasContext *ctx, TCGCond cond, TCGv pred) +{ + TCGv LSB =3D tcg_temp_new(); + tcg_gen_andi_tl(LSB, pred, 1); + gen_cond_jumpr(ctx, hex_gpr[HEX_REG_LR], cond, LSB); + tcg_temp_free(LSB); +} + static void gen_cond_jump(DisasContext *ctx, TCGCond cond, TCGv pred, int pc_off) { --=20 2.17.1 From nobody Tue Sep 16 21:36:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1672262056; cv=none; d=zohomail.com; s=zohoarc; b=M+/5egzC7mBTYMVZnCQqqSvh7wYPE7uUtPlKETuogi9iQwrhzGQKZV9QYwD3VP0B/HmjkUvyEFkwHRQsDnKMBk+0n74C7ArAi9bSNIIzqGNole1DqV6UzE4fuHMw3i6nw6uyDLjPpiHLpf/Xwy+SQgDn/wlPIqlotowu9jNEgCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672262056; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672262058409000001 Add overrides for J2_callr J2_callrt J2_callrf Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 6 ++++++ target/hexagon/macros.h | 10 ---------- target/hexagon/genptr.c | 20 ++++++++++++++++++++ 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 3ee530f5d9..231654e6c1 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -614,11 +614,17 @@ =20 #define fGEN_TCG_J2_call(SHORTCODE) \ gen_call(ctx, riV) +#define fGEN_TCG_J2_callr(SHORTCODE) \ + gen_callr(ctx, RsV) =20 #define fGEN_TCG_J2_callt(SHORTCODE) \ gen_cond_call(ctx, PuV, TCG_COND_EQ, riV) #define fGEN_TCG_J2_callf(SHORTCODE) \ gen_cond_call(ctx, PuV, TCG_COND_NE, riV) +#define fGEN_TCG_J2_callrt(SHORTCODE) \ + gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV) +#define fGEN_TCG_J2_callrf(SHORTCODE) \ + gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV) =20 #define fGEN_TCG_J2_endloop0(SHORTCODE) \ gen_endloop0(ctx) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index cd64bb8eec..f6cc0e950c 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -421,16 +421,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) #define fHINTJR(TARGET) { /* Not modelled in qemu */} -#define fCALL(A) \ - do { \ - fWRITE_LR(fREAD_NPC()); \ - fBRANCH(A, COF_TYPE_CALL); \ - } while (0) -#define fCALLR(A) \ - do { \ - fWRITE_LR(fREAD_NPC()); \ - fBRANCH(A, COF_TYPE_CALLR); \ - } while (0) #define fWRITE_LOOP_REGS0(START, COUNT) \ do { \ WRITE_RREG(HEX_REG_LC0, COUNT); \ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index ee67cb0069..9e31f3418b 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -670,6 +670,14 @@ static void gen_call(DisasContext *ctx, int pc_off) gen_write_new_pc_pcrel(ctx, pc_off, TCG_COND_ALWAYS, NULL); } =20 +static void gen_callr(DisasContext *ctx, TCGv new_pc) +{ + TCGv next_PC =3D + tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes); + gen_log_reg_write(HEX_REG_LR, next_PC); + gen_write_new_pc_addr(ctx, new_pc, TCG_COND_ALWAYS, NULL); +} + static void gen_cond_call(DisasContext *ctx, TCGv pred, TCGCond cond, int pc_off) { @@ -686,6 +694,18 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred, gen_set_label(skip); } =20 +static void gen_cond_callr(DisasContext *ctx, + TCGCond cond, TCGv pred, TCGv new_pc) +{ + TCGv lsb =3D tcg_temp_new(); + TCGLabel *skip =3D gen_new_label(); + tcg_gen_andi_tl(lsb, pred, 1); + tcg_gen_brcondi_tl(cond, lsb, 0, skip); + tcg_temp_free(lsb); + gen_callr(ctx, new_pc); + gen_set_label(skip); +} + static void gen_endloop0(DisasContext *ctx) { TCGv lpcfg =3D tcg_temp_local_new(); --=20 2.17.1 From nobody Tue Sep 16 21:36:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1672262140; cv=none; d=zohomail.com; s=zohoarc; b=BTkKjm5v/SZGaydlv9SV2ecY8i7OtWf0AEV93gZ7TNbWARhS7UdC4no/19IS0bfYWkNqde/fi3LwB79HcrAC9o+6Sjl6+IE/Y+iHX0RbqJzS1iX+6itt3+k6MF/fm6OduzQGwkqtTi9I/ymVI/yysX4jSuTk1a7fGl1sIPsSTTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672262140; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 28 Dec 2022 21:13:28 GMT Received: from hu-devc-lv-u18-c.qualcomm.com (hu-tsimpson-lv.qualcomm.com [10.47.235.220]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTP id 2BSLDSf8021703; Wed, 28 Dec 2022 21:13:28 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 593D45000AF; Wed, 28 Dec 2022 13:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=05YqAL/3RGNpThfg2LqJUcXYylCgETUi8ge7DyFH2N4=; b=PjU+wM8fW1GGaV7QX5xIz9hUbw49WRhDoEnGtrY6waJvxcBhSqo+XhfzTf6g9XS77WxP /ULpksBqA18HsuQDrJiFfe64t5ogkEstEa4oDqs/JXwEkNR7EnJhJgjNqXqNx4aaImdE 0LYavF7dNMOO2GL4amf1L2N0yIbYLNt64uuc3ZHtCq7ndwunH0qzLYPeFD4QSvRTPqE7 4Dax9LvDcRF++5UTF5owN/L7U03oddQ22aAiprvPTIo6aaWSKXd9H6KC6NvyyAYM8n0Y oV3iNOKNSX6BGt05gkLJ9r9Lm5ju/IIyImzDQPyjPeaq2OI63lzcIHya3QoMzjLlbuCK FQ== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v2 3/6] Hexagon (target/hexagon) Add overrides for endloop1/endloop01 Date: Wed, 28 Dec 2022 13:13:21 -0800 Message-Id: <20221228211324.26989-4-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221228211324.26989-1-tsimpson@quicinc.com> References: <20221228211324.26989-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672262140852000007 Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 4 ++ target/hexagon/genptr.c | 79 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 231654e6c1..1ac23b75a0 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -628,6 +628,10 @@ =20 #define fGEN_TCG_J2_endloop0(SHORTCODE) \ gen_endloop0(ctx) +#define fGEN_TCG_J2_endloop1(SHORTCODE) \ + gen_endloop1(ctx) +#define fGEN_TCG_J2_endloop01(SHORTCODE) \ + gen_endloop01(ctx) =20 /* * Compound compare and jump instructions diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9e31f3418b..0eef2a2068 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -763,6 +763,85 @@ static void gen_endloop0(DisasContext *ctx) tcg_temp_free(lpcfg); } =20 +static void gen_endloop1(DisasContext *ctx) +{ + /* + * if (hex_gpr[HEX_REG_LC1] > 1) { + * PC =3D hex_gpr[HEX_REG_SA1]; + * hex_new_value[HEX_REG_LC1] =3D hex_gpr[HEX_REG_LC1] - 1; + * } + */ + TCGLabel *label =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, label); + { + gen_jumpr(ctx, hex_gpr[HEX_REG_SA1]); + tcg_gen_subi_tl(hex_new_value[HEX_REG_LC1], hex_gpr[HEX_REG_LC1], = 1); + } + gen_set_label(label); +} + +static void gen_endloop01(DisasContext *ctx) +{ + TCGv lpcfg =3D tcg_temp_local_new(); + + GET_USR_FIELD(USR_LPCFG, lpcfg); + + /* + * if (lpcfg =3D=3D 1) { + * hex_new_pred_value[3] =3D 0xff; + * hex_pred_written |=3D 1 << 3; + * } + */ + TCGLabel *label1 =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1); + { + tcg_gen_movi_tl(hex_new_pred_value[3], 0xff); + tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3); + } + gen_set_label(label1); + + /* + * if (lpcfg) { + * SET_USR_FIELD(USR_LPCFG, lpcfg - 1); + * } + */ + TCGLabel *label2 =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2); + { + tcg_gen_subi_tl(lpcfg, lpcfg, 1); + SET_USR_FIELD(USR_LPCFG, lpcfg); + } + gen_set_label(label2); + + /* + * if (hex_gpr[HEX_REG_LC0] > 1) { + * PC =3D hex_gpr[HEX_REG_SA0]; + * hex_new_value[HEX_REG_LC0] =3D hex_gpr[HEX_REG_LC0] - 1; + * } else { + * if (hex_gpr[HEX_REG_LC1] > 1) { + * hex_next_pc =3D hex_gpr[HEX_REG_SA1]; + * hex_new_value[HEX_REG_LC1] =3D hex_gpr[HEX_REG_LC1] - 1; + * } + * } + */ + TCGLabel *label3 =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3); + { + gen_jumpr(ctx, hex_gpr[HEX_REG_SA0]); + tcg_gen_subi_tl(hex_new_value[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], = 1); + tcg_gen_br(done); + } + gen_set_label(label3); + tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, done); + { + gen_jumpr(ctx, hex_gpr[HEX_REG_SA1]); + tcg_gen_subi_tl(hex_new_value[HEX_REG_LC1], hex_gpr[HEX_REG_LC1], = 1); + } + gen_set_label(done); + tcg_temp_free(lpcfg); +} + static void gen_cmp_jumpnv(DisasContext *ctx, TCGCond cond, TCGv val, TCGv src, int pc_off) { --=20 2.17.1 From nobody Tue Sep 16 21:36:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1672262064; cv=none; d=zohomail.com; s=zohoarc; b=Y1DnptHewilIVl9rfWjA9KWLiOKOAF91IMe/egB72cHGRN9u6snCvUpJQDYHV669YdaAjX38dVI1TR/HtUIQdOyoSlX2XgIqb159zUqkPcMavn8WsGkalzPlvclvJAniyOWV9Sudikksdgg2LeIggdEumDf4ppIX8E/1sIaepcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1672262064; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bJ89UgkOBFgPAiR4mlY+EauBzQ88vRJ3V6Sb/FHkqss=; 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Wed, 28 Dec 2022 21:13:28 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 5BB365000B0; Wed, 28 Dec 2022 13:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=bJ89UgkOBFgPAiR4mlY+EauBzQ88vRJ3V6Sb/FHkqss=; b=kVwl2+jLhVve48+Ajs4ym0Uhci5utuUSCE33QhjQMWmKjjUUBipt+ZFsSKySaRXecrGs 8095uiYXNvUIuJ9yrX6yRyaEQ7LYsMxXXRoIkJcyVgqwMhRkdTz3/zEtNgZ9GNgxWokI pGGtyw8EboUPY0t4ORGW+QeQZG3MwRRlsrbQ9kz64ozK9RWogJgHSRfsTE1dDPbDEPCD vWb2sw8w4QE+NkbJtDBGzMZAGTZJyPbIwgdT1nlQZCRlSd1j7a3919kMU4/r/Prj6EXk Liaa9Bm67ligWm4sWETYdA9D/or/x7Vnnvt9gwAEjUs1EJZdPgQ5QvrnURECACNSZhkv 8g== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v2 4/6] Hexagon (target/hexagon) Add overrides for dealloc-return instructions Date: Wed, 28 Dec 2022 13:13:22 -0800 Message-Id: <20221228211324.26989-5-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221228211324.26989-1-tsimpson@quicinc.com> References: <20221228211324.26989-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672262064476000001 These instructions perform a deallocframe+return (jumpr r31) Add overrides for L4_return SL2_return L4_return_t L4_return_f L4_return_tnew_pt L4_return_fnew_pt L4_return_tnew_pnt L4_return_fnew_pnt SL2_return_t SL2_return_f SL2_return_tnew SL2_return_fnew This patch eliminates the last helper that uses write_new_pc, so we remove it from op_helper.c Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 54 ++++++++++++++++++++++++ target/hexagon/genptr.c | 86 ++++++++++++++++++++++++++++++++++++++ target/hexagon/op_helper.c | 24 ----------- 3 files changed, 140 insertions(+), 24 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 1ac23b75a0..b54036655a 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -508,6 +508,60 @@ #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) =20 +/* + * dealloc_return + * Assembler mapped to + * r31:30 =3D dealloc_return(r30):raw + */ +#define fGEN_TCG_L4_return(SHORTCODE) \ + gen_return(ctx, RddV, RsV) + +/* + * sub-instruction version (no RddV, so handle it manually) + */ +#define fGEN_TCG_SL2_return(SHORTCODE) \ + do { \ + TCGv_i64 RddV =3D tcg_temp_new_i64(); \ + gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \ + gen_log_reg_write_pair(HEX_REG_FP, RddV); \ + tcg_temp_free_i64(RddV); \ + } while (0) + +/* + * Conditional returns follow this naming convention + * _t predicate true + * _f predicate false + * _tnew_pt predicate.new true predict taken + * _fnew_pt predicate.new false predict taken + * _tnew_pnt predicate.new true predict not taken + * _fnew_pnt predicate.new false predict not taken + * Predictions are not modelled in QEMU + * + * Example: + * if (p1) r31:30 =3D dealloc_return(r30):raw + */ +#define fGEN_TCG_L4_return_t(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ); +#define fGEN_TCG_L4_return_f(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE) +#define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) +#define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) +#define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ) +#define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \ + gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE) + +#define fGEN_TCG_SL2_return_t(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0]) +#define fGEN_TCG_SL2_return_f(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0]) +#define fGEN_TCG_SL2_return_tnew(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_new_pred_value[0]) +#define fGEN_TCG_SL2_return_fnew(SHORTCODE) \ + gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_new_pred_value[0]) + /* * Mathematical operations with more than one definition require * special handling diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 0eef2a2068..1544d181f1 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -706,6 +706,92 @@ static void gen_cond_callr(DisasContext *ctx, gen_set_label(skip); } =20 +/* frame ^=3D (int64_t)FRAMEKEY << 32 */ +static void gen_frame_unscramble(TCGv_i64 frame) +{ + TCGv_i64 framekey =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(framekey, hex_gpr[HEX_REG_FRAMEKEY]); + tcg_gen_shli_i64(framekey, framekey, 32); + tcg_gen_xor_i64(frame, frame, framekey); + tcg_temp_free_i64(framekey); +} + +static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA) +{ + Insn *insn =3D ctx->insn; /* Needed for CHECK_NOSHUF */ + CHECK_NOSHUF(EA, 8); + tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx); +} + +static void gen_return_base(DisasContext *ctx, TCGv_i64 dst, TCGv src, + TCGv r29) +{ + /* + * frame =3D *src + * dst =3D frame_unscramble(frame) + * SP =3D src + 8 + * PC =3D dst.w[1] + */ + TCGv_i64 frame =3D tcg_temp_new_i64(); + TCGv r31 =3D tcg_temp_new(); + + gen_load_frame(ctx, frame, src); + gen_frame_unscramble(frame); + tcg_gen_mov_i64(dst, frame); + tcg_gen_addi_tl(r29, src, 8); + tcg_gen_extrh_i64_i32(r31, dst); + gen_jumpr(ctx, r31); + + tcg_temp_free_i64(frame); + tcg_temp_free(r31); +} + +static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src) +{ + TCGv r29 =3D tcg_temp_new(); + gen_return_base(ctx, dst, src, r29); + gen_log_reg_write(HEX_REG_SP, r29); + tcg_temp_free(r29); +} + +/* if (pred) dst =3D dealloc_return(src):raw */ +static void gen_cond_return(DisasContext *ctx, TCGv_i64 dst, TCGv src, + TCGv pred, TCGCond cond) +{ + TCGv LSB =3D tcg_temp_new(); + TCGv mask =3D tcg_temp_new(); + TCGv r29 =3D tcg_temp_local_new(); + TCGLabel *skip =3D gen_new_label(); + tcg_gen_andi_tl(LSB, pred, 1); + + /* Initialize the results in case the predicate is false */ + tcg_gen_movi_i64(dst, 0); + tcg_gen_movi_tl(r29, 0); + + /* Set the bit in hex_slot_cancelled if the predicate is flase */ + tcg_gen_movi_tl(mask, 1 << ctx->insn->slot); + tcg_gen_or_tl(mask, hex_slot_cancelled, mask); + tcg_gen_movcond_tl(cond, hex_slot_cancelled, LSB, tcg_constant_tl(0), + mask, hex_slot_cancelled); + tcg_temp_free(mask); + + tcg_gen_brcondi_tl(cond, LSB, 0, skip); + tcg_temp_free(LSB); + gen_return_base(ctx, dst, src, r29); + gen_set_label(skip); + gen_log_predicated_reg_write(HEX_REG_SP, r29, ctx->insn->slot); + tcg_temp_free(r29); +} + +/* sub-instruction version (no RddV, so handle it manually) */ +static void gen_cond_return_subinsn(DisasContext *ctx, TCGCond cond, TCGv = pred) +{ + TCGv_i64 RddV =3D tcg_temp_local_new_i64(); + gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond); + gen_log_predicated_reg_write_pair(HEX_REG_FP, RddV, ctx->insn->slot); + tcg_temp_free_i64(RddV); +} + static void gen_endloop0(DisasContext *ctx) { TCGv lpcfg =3D tcg_temp_local_new(); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 35449ef524..9aa0f963fa 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -105,30 +105,6 @@ void log_store64(CPUHexagonState *env, target_ulong ad= dr, env->mem_log_stores[slot].data64 =3D val; } =20 -void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof, - target_ulong addr) -{ - HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); - - if (pkt_has_multi_cof) { - /* - * If more than one branch is taken in a packet, only the first one - * is actually done. - */ - if (env->branch_taken) { - HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, " - "ignoring the second one\n"); - } else { - fCHECK_PCALIGN(addr); - env->gpr[HEX_REG_PC] =3D addr; - env->branch_taken =3D 1; - } - } else { - fCHECK_PCALIGN(addr); - env->gpr[HEX_REG_PC] =3D addr; - } -} - /* Handy place to set a breakpoint */ void HELPER(debug_start_packet)(CPUHexagonState *env) { --=20 2.17.1 From nobody Tue Sep 16 21:36:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1672262028; cv=none; d=zohomail.com; s=zohoarc; b=Xo77y03RwLaEQx9/8mDDMnxdJUNAntViZS5wvMAULebwyYTeu9h6qKR73yku6CrQNLWH0RqL+KT26qGlh1wvXXT5mxRdDSjdz/w3y3fxrhqOFcMgcwOIoAUj9VXfhwpH9hvujgi7NVYWgnDGvdLlgOdm2wVpI1pYHlcgd4818+A= ARC-Message-Signature: i=1; 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Wed, 28 Dec 2022 21:13:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTP id 3mntgkr0nb-1; Wed, 28 Dec 2022 21:13:29 +0000 Received: from NALASPPMTA01.qualcomm.com (NALASPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2BSLDTkU010139; Wed, 28 Dec 2022 21:13:29 GMT Received: from hu-devc-lv-u18-c.qualcomm.com (hu-tsimpson-lv.qualcomm.com [10.47.235.220]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTP id 2BSLDSka010130; Wed, 28 Dec 2022 21:13:29 +0000 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 5E2835000B1; Wed, 28 Dec 2022 13:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=u7FfKDzyisHsJhXKiftsJCFiNfgZ3N9bBB38SNd+VOk=; b=BOGY07TbZ/6ia9DsKUSgclxQfEqn45d4C2U436b3jnaSS/480623lyHLzGzaKd5bk+ei ruSCJPxxTuvz9mtVNg/sDKTNrAr7B++YueJIxILOjtb7JBlb4F+CteObTZTOyQFTU1RG zZIUlL78MTHvnXq4GlWpi6Tbl0HHgfubuXulI9AxSyeOQeM9LtfNYqXjH1kddguqtOb8 DLgy0OdNyOfICe4g2etwJp//jSCXHf4Co7YpRGte0w/rMg8iDkZoJA6uO6XIqqCAlLVL mqRP7iO7aEMXb7GBnOU8glhmjRcGTA/PslN1IC44yK5ObD99wHqV8vJm7XtudKy1iTHG fA== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, bcain@quicinc.com, quic_mathbern@quicinc.com Subject: [PATCH v2 5/6] Hexagon (target/hexagon) Analyze packet before generating TCG Date: Wed, 28 Dec 2022 13:13:23 -0800 Message-Id: <20221228211324.26989-6-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221228211324.26989-1-tsimpson@quicinc.com> References: <20221228211324.26989-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=tsimpson@qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672262030581000001 We create a new generator that creates an analyze_ function for each instruction. Currently, these functions record the writes to R, P, and C registers by calling ctx_log_reg_write[_pair] or ctx_log_pred_write. During gen_start_packet, we invoke the analyze_ function for each instruction in the packet, and we mark the implicit register and predicate writes. Doing the analysis up front has several advantages - We remove calls to ctx_log_* from gen_tcg_funcs.py and genptr.c - After the analysis is performed, we can initialize hex_new_value for each of the predicated assignments rather than during TCG generation for the instructions - This is a stepping stone for future work where the analysis will include the set of registers that are written. In cases where the packet doesn't have an overlap between the registers that are written and registers that are read, we can avoid the intermediate step of writing to hex_new_value. Note that other checks will also be needed (e.g., no instructions can raise an exception). Signed-off-by: Taylor Simpson --- target/hexagon/insn.h | 3 + target/hexagon/translate.h | 43 ++-- target/hexagon/genptr.c | 5 +- target/hexagon/idef-parser/parser-helpers.c | 5 - target/hexagon/translate.c | 145 +++++++----- target/hexagon/README | 11 +- target/hexagon/gen_analyze_func_table.py | 52 +++++ target/hexagon/gen_analyze_funcs.py | 239 ++++++++++++++++++++ target/hexagon/gen_tcg_funcs.py | 21 -- target/hexagon/meson.build | 18 ++ 10 files changed, 428 insertions(+), 114 deletions(-) create mode 100755 target/hexagon/gen_analyze_func_table.py create mode 100755 target/hexagon/gen_analyze_funcs.py diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h index 3e7a22c91e..1dedb6c486 100644 --- a/target/hexagon/insn.h +++ b/target/hexagon/insn.h @@ -29,6 +29,7 @@ struct Packet; struct DisasContext; =20 typedef void (*SemanticInsn)(struct DisasContext *ctx); +typedef void (*AnalyzeInsn)(struct DisasContext *ctx); =20 struct Instruction { SemanticInsn generate; /* pointer to genptr routine */ @@ -74,4 +75,6 @@ struct Packet { =20 typedef struct Packet Packet; =20 +extern const AnalyzeInsn opcode_analyze[]; + #endif diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d971f4f095..4cdaf9ac70 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -38,6 +38,7 @@ typedef struct DisasContext { int reg_log[REG_WRITES_MAX]; int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); + DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); int preg_log[PRED_WRITES_MAX]; int preg_log_idx; DECLARE_BITMAP(pregs_written, NUM_PREGS); @@ -62,32 +63,36 @@ typedef struct DisasContext { bool is_tight_loop; } DisasContext; =20 -static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) -{ - if (test_bit(rnum, ctx->regs_written)) { - HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum); - } - ctx->reg_log[ctx->reg_log_idx] =3D rnum; - ctx->reg_log_idx++; - set_bit(rnum, ctx->regs_written); -} - -static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum) -{ - ctx_log_reg_write(ctx, rnum); - ctx_log_reg_write(ctx, rnum + 1); -} - static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) { ctx->preg_log[ctx->preg_log_idx] =3D pnum; ctx->preg_log_idx++; - set_bit(pnum, ctx->pregs_written); } =20 -static inline bool is_preloaded(DisasContext *ctx, int num) +static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, + bool is_predicated) +{ + if (rnum =3D=3D HEX_REG_P3_0) { + for (int i =3D 0; i < NUM_PREGS; i++) { + ctx_log_pred_write(ctx, i); + } + } else { + if (!test_bit(rnum, ctx->regs_written)) { + ctx->reg_log[ctx->reg_log_idx] =3D rnum; + ctx->reg_log_idx++; + set_bit(rnum, ctx->regs_written); + } + if (is_predicated) { + set_bit(rnum, ctx->predicated_regs); + } + } +} + +static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum, + bool is_predicated) { - return test_bit(num, ctx->regs_written); + ctx_log_reg_write(ctx, rnum, is_predicated); + ctx_log_reg_write(ctx, rnum + 1, is_predicated); } =20 static inline bool is_vreg_preloaded(DisasContext *ctx, int num) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1544d181f1..b70402c819 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -149,6 +149,7 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TC= Gv val) hex_new_pred_value[pnum], base_val); } tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); + set_bit(pnum, ctx->pregs_written); =20 tcg_temp_free(base_val); } @@ -231,7 +232,6 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv cont= rol_reg) for (int i =3D 0; i < NUM_PREGS; i++) { tcg_gen_extract_tl(hex_p8, control_reg, i * 8, 8); gen_log_pred_write(ctx, i, hex_p8); - ctx_log_pred_write(ctx, i); } tcg_temp_free(hex_p8); } @@ -250,7 +250,6 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx= , int reg_num, gen_write_p3_0(ctx, val); } else { gen_log_reg_write(reg_num, val); - ctx_log_reg_write(ctx, reg_num); if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) { ctx->num_packets =3D 0; } @@ -273,10 +272,8 @@ static inline void gen_write_ctrl_reg_pair(DisasContex= t *ctx, int reg_num, tcg_gen_extrh_i64_i32(val32, val); gen_log_reg_write(reg_num + 1, val32); tcg_temp_free(val32); - ctx_log_reg_write(ctx, reg_num + 1); } else { gen_log_reg_write_pair(reg_num, val); - ctx_log_reg_write_pair(ctx, reg_num); if (reg_num =3D=3D HEX_REG_QEMU_PKT_CNT) { ctx->num_packets =3D 0; ctx->num_insns =3D 0; diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 8110686c51..5b28f372af 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1438,10 +1438,6 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexVal= ue *reg, HexValue *value) locp, "gen_log_reg_write(", ®->reg.id, ", ", &value_m, ");\n"); - OUT(c, - locp, - "ctx_log_reg_write(ctx, ", ®->reg.id, - ");\n"); gen_rvalue_free(c, locp, reg); gen_rvalue_free(c, locp, &value_m); } @@ -1894,7 +1890,6 @@ void gen_pred_assign(Context *c, YYLTYPE *locp, HexVa= lue *left_pred, if (is_direct) { OUT(c, locp, "gen_log_pred_write(ctx, ", pred_id, ", ", left_pred, ");\n"); - OUT(c, locp, "ctx_log_pred_write(ctx, ", pred_id, ");\n"); gen_rvalue_free(c, locp, left_pred); } /* Free temporary value */ diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 75f28e08ad..477111bda2 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -28,6 +28,8 @@ #include "decode.h" #include "translate.h" #include "printinsn.h" +#include "analyze_funcs_generated.c.inc" +#include "analyze_func_table_generated.c.inc" =20 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; @@ -265,6 +267,76 @@ static bool need_next_PC(DisasContext *ctx) return false; } =20 +/* + * The insn->analyze functions mark most of the writes in a packet + * However, there are some implicit writes marked as attributes + * of the applicable instructions. + */ +static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnu= m) +{ + uint16_t opcode =3D ctx->insn->opcode; + if (GET_ATTRIB(opcode, attrib)) { + /* + * USR is used to set overflow and FP exceptions, + * so treat it as conditional + */ + bool is_predicated =3D GET_ATTRIB(opcode, A_CONDEXEC) || + rnum =3D=3D HEX_REG_USR; + + /* LC0/LC1 is conditionally written by endloop instructions */ + if ((rnum =3D=3D HEX_REG_LC0 || rnum =3D=3D HEX_REG_LC1) && + (opcode =3D=3D J2_endloop0 || + opcode =3D=3D J2_endloop1 || + opcode =3D=3D J2_endloop01)) { + is_predicated =3D true; + } + + ctx_log_reg_write(ctx, rnum, is_predicated); + } +} + +static void mark_implicit_reg_writes(DisasContext *ctx) +{ + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); + mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); + mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); +} + +static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pn= um) +{ + if (GET_ATTRIB(ctx->insn->opcode, attrib)) { + ctx_log_pred_write(ctx, pnum); + } +} + +static void mark_implicit_pred_writes(DisasContext *ctx) +{ + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); + mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); +} + +static void analyze_packet(DisasContext *ctx) +{ + Packet *pkt =3D ctx->pkt; + for (int i =3D 0; i < pkt->num_insns; i++) { + Insn *insn =3D &pkt->insn[i]; + ctx->insn =3D insn; + if (opcode_analyze[insn->opcode]) { + opcode_analyze[insn->opcode](ctx); + } + mark_implicit_reg_writes(ctx); + mark_implicit_pred_writes(ctx); + } +} + static void gen_start_packet(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; @@ -275,6 +347,7 @@ static void gen_start_packet(DisasContext *ctx) ctx->next_PC =3D next_PC; ctx->reg_log_idx =3D 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); + bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; bitmap_zero(ctx->pregs_written, NUM_PREGS); ctx->future_vregs_idx =3D 0; @@ -291,6 +364,8 @@ static void gen_start_packet(DisasContext *ctx) ctx->s1_store_processed =3D false; ctx->pre_commit =3D true; =20 + analyze_packet(ctx); + if (HEX_DEBUG) { /* Handy place to set a breakpoint before the packet executes */ gen_helper_debug_start_packet(cpu_env); @@ -312,6 +387,14 @@ static void gen_start_packet(DisasContext *ctx) if (need_pred_written(pkt)) { tcg_gen_movi_tl(hex_pred_written, 0); } + if (!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { + int i =3D find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_RE= GS); + while (i < TOTAL_PER_THREAD_REGS) { + tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]); + i =3D find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REG= S, + i + 1); + } + } =20 if (pkt->pkt_has_hvx) { tcg_gen_movi_tl(hex_VRegs_updated, 0); @@ -336,66 +419,6 @@ bool is_gather_store_insn(DisasContext *ctx) return false; } =20 -/* - * The LOG_*_WRITE macros mark most of the writes in a packet - * However, there are some implicit writes marked as attributes - * of the applicable instructions. - */ -static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnu= m) -{ - uint16_t opcode =3D ctx->insn->opcode; - if (GET_ATTRIB(opcode, attrib)) { - /* - * USR is used to set overflow and FP exceptions, - * so treat it as conditional - */ - bool is_predicated =3D GET_ATTRIB(opcode, A_CONDEXEC) || - rnum =3D=3D HEX_REG_USR; - - /* LC0/LC1 is conditionally written by endloop instructions */ - if ((rnum =3D=3D HEX_REG_LC0 || rnum =3D=3D HEX_REG_LC1) && - (opcode =3D=3D J2_endloop0 || - opcode =3D=3D J2_endloop1 || - opcode =3D=3D J2_endloop01)) { - is_predicated =3D true; - } - - if (is_predicated && !is_preloaded(ctx, rnum)) { - tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); - } - - ctx_log_reg_write(ctx, rnum); - } -} - -static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pn= um) -{ - if (GET_ATTRIB(ctx->insn->opcode, attrib)) { - ctx_log_pred_write(ctx, pnum); - } -} - -static void mark_implicit_reg_writes(DisasContext *ctx) -{ - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); - mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); - mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); -} - -static void mark_implicit_pred_writes(DisasContext *ctx) -{ - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); - mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); -} - static void mark_store_width(DisasContext *ctx) { uint16_t opcode =3D ctx->insn->opcode; @@ -423,9 +446,7 @@ static void mark_store_width(DisasContext *ctx) static void gen_insn(DisasContext *ctx) { if (ctx->insn->generate) { - mark_implicit_reg_writes(ctx); ctx->insn->generate(ctx); - mark_implicit_pred_writes(ctx); mark_store_width(ctx); } else { gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); diff --git a/target/hexagon/README b/target/hexagon/README index 6cb5affddb..d00c85d554 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -52,6 +52,8 @@ header files in /target/hexagon gen_tcg_func_table.py -> tcg_func_table_generated.c.inc gen_helper_funcs.py -> helper_funcs_generated.c.inc gen_idef_parser_funcs.py -> idef_parser_input.h + gen_analyze_funcs.py -> analyze_funcs_generated.c.inc + gen_analyze_func_table.py -> analyze_func_table.c.inc =20 Qemu helper functions have 3 parts DEF_HELPER declaration indicates the signature of the helper @@ -87,7 +89,6 @@ tcg_funcs_generated.c.inc TCGv RtV =3D hex_gpr[insn->regno[2]]; gen_helper_A2_add(RdV, cpu_env, RsV, RtV); gen_log_reg_write(RdN, RdV); - ctx_log_reg_write(ctx, RdN); tcg_temp_free(RdV); } =20 @@ -162,7 +163,6 @@ istruction. gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot); tcg_temp_free(slot); gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); - ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); tcg_temp_free_ptr(VdV); tcg_temp_free_ptr(VuV); tcg_temp_free_ptr(VvV); @@ -195,9 +195,14 @@ when the override is present. vreg_src_off(ctx, VvN); fGEN_TCG_V6_vaddw({ fHIDE(int i;) fVFOREACH(32, i) { VdV.w[i] =3D = VuV.w[i] + VvV.w[i] ; } }); gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); - ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); } =20 +We also generate an analyze_ function for each instruction. Currentl= y, +these functions record the writes to registers by calling ctx_log_*. Duri= ng +gen_start_packet, we invoke the analyze_ function for each instructio= n in +the packet, and we mark the implicit writes. After the analysis is perfor= med, +we initialize hex_new_value for each of the predicated assignments. + In addition to instruction semantics, we use a generator to create the dec= ode tree. This generation is also a two step process. The first step is to r= un target/hexagon/gen_dectree_import.c to produce diff --git a/target/hexagon/gen_analyze_func_table.py b/target/hexagon/gen_= analyze_func_table.py new file mode 100755 index 0000000000..6fab906ad3 --- /dev/null +++ b/target/hexagon/gen_analyze_func_table.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2022 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +import hex_common + +def main(): + hex_common.read_semantics_file(sys.argv[1]) + hex_common.read_attribs_file(sys.argv[2]) + hex_common.calculate_attribs() + tagregs =3D hex_common.get_tagregs() + tagimms =3D hex_common.get_tagimms() + + with open(sys.argv[3], 'w') as f: + f.write("#ifndef HEXAGON_ANALYZE_TABLE_H\n") + f.write("#define HEXAGON_ANALYZE_TABLE_H\n\n") + + f.write("const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] =3D {\n") + for tag in hex_common.tags: + ## Skip the diag instructions + if ( tag =3D=3D "Y6_diag" ) : + continue + if ( tag =3D=3D "Y6_diag0" ) : + continue + if ( tag =3D=3D "Y6_diag1" ) : + continue + + f.write(" [%s] =3D analyze_%s,\n" % (tag, tag)) + f.write("};\n\n") + + f.write("#endif /* HEXAGON_ANALYZE_TABLE_H */\n") + +if __name__ =3D=3D "__main__": + main() diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py new file mode 100755 index 0000000000..c8eb1d5219 --- /dev/null +++ b/target/hexagon/gen_analyze_funcs.py @@ -0,0 +1,239 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2022 Qualcomm Innovation Center, Inc. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +import hex_common + +## +## Helpers for gen_analyze_func +## +def is_predicated(tag): + return 'A_CONDEXEC' in hex_common.attribdict[tag] + +def analyze_opn_old(f, tag, regtype, regid, regno): + regN =3D "%s%sN" % (regtype, regid) + predicated =3D "true" if is_predicated(tag) else "false" + if (regtype =3D=3D "R"): + if (regid in {"ss", "tt"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"dd", "ee", "xx", "yy"}): + f.write(" const int %s =3D insn->regno[%d];\n" % (regN, reg= no)) + f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \ + (regN, predicated)) + elif (regid in {"s", "t", "u", "v"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d", "e", "x", "y"}): + f.write(" const int %s =3D insn->regno[%d];\n" % (regN, reg= no)) + f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \ + (regN, predicated)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "P"): + if (regid in {"s", "t", "u", "v"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d", "e", "x"}): + f.write(" const int %s =3D insn->regno[%d];\n" % (regN, reg= no)) + f.write(" ctx_log_pred_write(ctx, %s);\n" % (regN)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "C"): + if (regid =3D=3D "ss"): + f.write("// const int %s =3D insn->regno[%d] + HEX_REG_SA0;= \n" % \ + (regN, regno)) + elif (regid =3D=3D "dd"): + f.write(" const int %s =3D insn->regno[%d] + HEX_REG_SA0;\n= " % \ + (regN, regno)) + f.write(" ctx_log_reg_write_pair(ctx, %s, %s);\n" % \ + (regN, predicated)) + elif (regid =3D=3D "s"): + f.write("// const int %s%sN =3D insn->regno[%d] + HEX_REG_S= A0;\n" % \ + (regtype, regid, regno)) + elif (regid =3D=3D "d"): + f.write(" const int %s =3D insn->regno[%d] + HEX_REG_SA0;\n= " % \ + (regN, regno)) + f.write(" ctx_log_reg_write(ctx, %s, %s);\n" % \ + (regN, predicated)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "M"): + if (regid =3D=3D "u"): + f.write("// const int %s =3D insn->regno[%d];\n"% \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "V"): + if (regid in {"dd", "xx"}): + f.write("// const int %s =3D insn->regno[%d];\n" %\ + (regN, regno)) + elif (regid in {"uu", "vv"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s", "u", "v", "w"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d", "x", "y"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "Q"): + if (regid in {"d", "e", "x"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s", "t", "u", "v"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "G"): + if (regid in {"dd"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"ss"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "S"): + if (regid in {"dd"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"d"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"ss"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + elif (regid in {"s"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + else: + print("Bad register parse: ", regtype, regid) + +def analyze_opn_new(f, tag, regtype, regid, regno): + regN =3D "%s%sN" % (regtype, regid) + if (regtype =3D=3D "N"): + if (regid in {"s", "t"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "P"): + if (regid in {"t", "u", "v"}): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + elif (regtype =3D=3D "O"): + if (regid =3D=3D "s"): + f.write("// const int %s =3D insn->regno[%d];\n" % \ + (regN, regno)) + else: + print("Bad register parse: ", regtype, regid) + else: + print("Bad register parse: ", regtype, regid) + +def analyze_opn(f, tag, regtype, regid, toss, numregs, i): + if (hex_common.is_pair(regid)): + analyze_opn_old(f, tag, regtype, regid, i) + elif (hex_common.is_single(regid)): + if hex_common.is_old_val(regtype, regid, tag): + analyze_opn_old(f,tag, regtype, regid, i) + elif hex_common.is_new_val(regtype, regid, tag): + analyze_opn_new(f, tag, regtype, regid, i) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + +## +## Generate the code to analyze the instruction +## For A2_add: Rd32=3Dadd(Rs32,Rt32), { RdV=3DRsV+RtV;} +## We produce: +## static void analyze_A2_add(DisasContext *ctx) +## { +## Insn *insn __attribute__((unused)) =3D ctx->insn; +## const int RdN =3D insn->regno[0]; +## ctx_log_reg_write(ctx, RdN, false); +## // const int RsN =3D insn->regno[1]; +## // const int RtN =3D insn->regno[2]; +## } +## +def gen_analyze_func(f, tag, regs, imms): + f.write("static void analyze_%s(DisasContext *ctx)\n" %tag) + f.write('{\n') + + f.write(" Insn *insn __attribute__((unused)) =3D ctx->insn;\n") + + i=3D0 + ## Analyze all the registers + for regtype,regid,toss,numregs in regs: + analyze_opn(f, tag, regtype, regid, toss, numregs, i) + i +=3D 1 + + + f.write("}\n\n") + +def gen_def_analyze_func(f, tag, tagregs, tagimms): + regs =3D tagregs[tag] + imms =3D tagimms[tag] + + gen_analyze_func(f, tag, regs, imms) + +def main(): + hex_common.read_semantics_file(sys.argv[1]) + hex_common.read_attribs_file(sys.argv[2]) + hex_common.read_overrides_file(sys.argv[3]) + hex_common.read_overrides_file(sys.argv[4]) + hex_common.calculate_attribs() + tagregs =3D hex_common.get_tagregs() + tagimms =3D hex_common.get_tagimms() + + with open(sys.argv[5], 'w') as f: + f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") + f.write("#define HEXAGON_TCG_FUNCS_H\n\n") + + for tag in hex_common.tags: + ## Skip the diag instructions + if ( tag =3D=3D "Y6_diag" ) : + continue + if ( tag =3D=3D "Y6_diag0" ) : + continue + if ( tag =3D=3D "Y6_diag1" ) : + continue + + gen_def_analyze_func(f, tag, tagregs, tagimms) + + f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n") + +if __name__ =3D=3D "__main__": + main() diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 7e8ba17ca2..615b60a67b 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -44,15 +44,6 @@ def genptr_decl_pair_writable(f, tag, regtype, regid, re= gno): (regN, regno)) else: f.write(" const int %s =3D insn->regno[%d];\n" % (regN, regno)) - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - f.write(" if (!is_preloaded(ctx, %s)) {\n" % regN) - f.write(" tcg_gen_mov_tl(hex_new_value[%s], hex_gpr[%s]);\n= " % \ - (regN, regN)) - f.write(" }\n") - f.write(" if (!is_preloaded(ctx, %s + 1)) {\n" % regN) - f.write(" tcg_gen_mov_tl(hex_new_value[%s + 1], hex_gpr[%s = + 1]);\n" % \ - (regN, regN)) - f.write(" }\n") =20 def genptr_decl_writable(f, tag, regtype, regid, regno): regN=3D"%s%sN" % (regtype,regid) @@ -63,11 +54,6 @@ def genptr_decl_writable(f, tag, regtype, regid, regno): (regN, regno)) else: f.write(" const int %s =3D insn->regno[%d];\n" % (regN, regno)) - if ('A_CONDEXEC' in hex_common.attribdict[tag]): - f.write(" if (!is_preloaded(ctx, %s)) {\n" % regN) - f.write(" tcg_gen_mov_tl(hex_new_value[%s], hex_gpr[%s]);\n= " % \ - (regN, regN)) - f.write(" }\n") =20 def genptr_decl(f, tag, regtype, regid, regno): regN=3D"%s%sN" % (regtype,regid) @@ -465,8 +451,6 @@ def genptr_dst_write_pair(f, tag, regtype, regid): else: f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \ (regtype, regid, regtype, regid)) - f.write(" ctx_log_reg_write_pair(ctx, %s%sN);\n" % \ - (regtype, regid)) =20 def genptr_dst_write(f, tag, regtype, regid): if (regtype =3D=3D "R"): @@ -480,16 +464,12 @@ def genptr_dst_write(f, tag, regtype, regid): else: f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \ (regtype, regid, regtype, regid)) - f.write(" ctx_log_reg_write(ctx, %s%sN);\n" % \ - (regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "P"): if (regid in {"d", "e", "x"}): f.write(" gen_log_pred_write(ctx, %s%sN, %s%sV);\n" % \ (regtype, regid, regtype, regid)) - f.write(" ctx_log_pred_write(ctx, %s%sN);\n" % \ - (regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "C"): @@ -581,7 +561,6 @@ def genptr_dst_write_opn(f,regtype, regid, tag): ## TCGv RtV =3D hex_gpr[insn->regno[2]]; ## ## gen_log_reg_write(RdN, RdV); -## ctx_log_reg_write(ctx, RdN); ## tcg_temp_free(RdV); ## } ## diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index e8f250fcac..87aef6283e 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -67,6 +67,24 @@ tcg_func_table_generated =3D custom_target( ) hexagon_ss.add(tcg_func_table_generated) =20 +analyze_funcs_generated =3D custom_target( + 'analyze_funcs_generated.c.inc', + output: 'analyze_funcs_generated.c.inc', + depends: [semantics_generated], + depend_files: [hex_common_py, attribs_def, gen_tcg_h, gen_tcg_hvx_h], + command: [python, files('gen_analyze_funcs.py'), semantics_generated, = attribs_def, gen_tcg_h, gen_tcg_hvx_h, '@OUTPUT@'], +) +hexagon_ss.add(analyze_funcs_generated) + +analyze_func_table_generated =3D custom_target( + 'analyze_func_table_generated.c.inc', + output: 'analyze_func_table_generated.c.inc', + depends: [semantics_generated], + depend_files: [hex_common_py, attribs_def], + command: [python, files('gen_analyze_func_table.py'), semantics_genera= ted, attribs_def, '@OUTPUT@'], +) +hexagon_ss.add(analyze_func_table_generated) + printinsn_generated =3D custom_target( 'printinsn_generated.h.inc', output: 'printinsn_generated.h.inc', --=20 2.17.1 From nobody Tue Sep 16 21:36:28 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1672262042532000001 Analyze HVX vector and predicate registers Signed-off-by: Taylor Simpson --- target/hexagon/translate.h | 14 ++++++++------ target/hexagon/translate.c | 28 ++++++++++++++++++++++++++++ target/hexagon/gen_analyze_funcs.py | 17 ++++++++++++++--- target/hexagon/gen_tcg_funcs.py | 18 ------------------ 4 files changed, 50 insertions(+), 27 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 4cdaf9ac70..5cd0baf216 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -54,6 +54,8 @@ typedef struct DisasContext { DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); DECLARE_BITMAP(vregs_updated, NUM_VREGS); DECLARE_BITMAP(vregs_select, NUM_VREGS); + DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); + DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); int qreg_log[NUM_QREGS]; bool qreg_is_predicated[NUM_QREGS]; int qreg_log_idx; @@ -95,12 +97,6 @@ static inline void ctx_log_reg_write_pair(DisasContext *= ctx, int rnum, ctx_log_reg_write(ctx, rnum + 1, is_predicated); } =20 -static inline bool is_vreg_preloaded(DisasContext *ctx, int num) -{ - return test_bit(num, ctx->vregs_updated) || - test_bit(num, ctx->vregs_updated_tmp); -} - intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, int num, bool alloc_ok); intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, @@ -116,12 +112,18 @@ static inline void ctx_log_vreg_write(DisasContext *c= tx, ctx->vreg_log_idx++; =20 set_bit(rnum, ctx->vregs_updated); + if (is_predicated) { + set_bit(rnum, ctx->predicated_future_vregs); + } } if (type =3D=3D EXT_NEW) { set_bit(rnum, ctx->vregs_select); } if (type =3D=3D EXT_TMP) { set_bit(rnum, ctx->vregs_updated_tmp); + if (is_predicated) { + set_bit(rnum, ctx->predicated_tmp_vregs); + } } } =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 477111bda2..0facf2438a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -356,6 +356,8 @@ static void gen_start_packet(DisasContext *ctx) bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); bitmap_zero(ctx->vregs_updated, NUM_VREGS); bitmap_zero(ctx->vregs_select, NUM_VREGS); + bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); + bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); ctx->qreg_log_idx =3D 0; for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; @@ -395,6 +397,32 @@ static void gen_start_packet(DisasContext *ctx) i + 1); } } + if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { + int i =3D find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); + while (i < NUM_VREGS) { + const intptr_t VdV_off =3D + ctx_future_vreg_off(ctx, i, 1, true); + intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); + tcg_gen_gvec_mov(MO_64, VdV_off, + src_off, + sizeof(MMVector), + sizeof(MMVector)); + i =3D find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i= + 1); + } + } + if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { + int i =3D find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); + while (i < NUM_VREGS) { + const intptr_t VdV_off =3D + ctx_tmp_vreg_off(ctx, i, 1, true); + intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); + tcg_gen_gvec_mov(MO_64, VdV_off, + src_off, + sizeof(MMVector), + sizeof(MMVector)); + i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); + } + } =20 if (pkt->pkt_has_hvx) { tcg_gen_movi_tl(hex_VRegs_updated, 0); diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index c8eb1d5219..831006c111 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -83,9 +83,16 @@ def analyze_opn_old(f, tag, regtype, regid, regno): else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "V"): + newv =3D "EXT_DFL" + if (hex_common.is_new_result(tag)): + newv =3D "EXT_NEW" + elif (hex_common.is_tmp_result(tag)): + newv =3D "EXT_TMP" if (regid in {"dd", "xx"}): - f.write("// const int %s =3D insn->regno[%d];\n" %\ + f.write(" const int %s =3D insn->regno[%d];\n" %\ (regN, regno)) + f.write(" ctx_log_vreg_write_pair(ctx, %s, %s, %s);\n" % \ + (regN, newv, predicated)) elif (regid in {"uu", "vv"}): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) @@ -93,14 +100,18 @@ def analyze_opn_old(f, tag, regtype, regid, regno): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) elif (regid in {"d", "x", "y"}): - f.write("// const int %s =3D insn->regno[%d];\n" % \ + f.write(" const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) + f.write(" ctx_log_vreg_write(ctx, %s, %s, %s);\n" % \ + (regN, newv, predicated)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): if (regid in {"d", "e", "x"}): - f.write("// const int %s =3D insn->regno[%d];\n" % \ + f.write(" const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) + f.write(" ctx_log_qreg_write(ctx, %s, %s);\n" % \ + (regN, predicated)) elif (regid in {"s", "t", "u", "v"}): f.write("// const int %s =3D insn->regno[%d];\n" % \ (regN, regno)) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 615b60a67b..2c02fab356 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -159,17 +159,6 @@ def genptr_decl(f, tag, regtype, regid, regno): f.write(" ctx_future_vreg_off(ctx, %s%sN," % \ (regtype, regid)) f.write(" 1, true);\n"); - if 'A_CONDEXEC' in hex_common.attribdict[tag]: - f.write(" if (!is_vreg_preloaded(ctx, %s)) {\n" % (regN= )) - f.write(" intptr_t src_off =3D") - f.write(" offsetof(CPUHexagonState, VRegs[%s%sN]);\n"% \ - (regtype, regid)) - f.write(" tcg_gen_gvec_mov(MO_64, %s%sV_off,\n" % \ - (regtype, regid)) - f.write(" src_off,\n") - f.write(" sizeof(MMVector),\n") - f.write(" sizeof(MMVector));\n") - f.write(" }\n") =20 if (not hex_common.skip_qemu_helper(tag)): f.write(" TCGv_ptr %s%sV =3D tcg_temp_new_ptr();\n" % \ @@ -495,9 +484,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv= =3D"EXT_DFL"): (regtype, regid, regtype, regid)) f.write("%s, insn->slot, %s);\n" % \ (newv, is_predicated)) - f.write(" ctx_log_vreg_write_pair(ctx, %s%sN, %s,\n" % \ - (regtype, regid, newv)) - f.write(" %s);\n" % (is_predicated)) elif (regid in {"d", "x", "y"}): if ('A_CONDEXEC' in hex_common.attribdict[tag]): is_predicated =3D "true" @@ -507,8 +493,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv= =3D"EXT_DFL"): (regtype, regid, regtype, regid, newv)) f.write("insn->slot, %s);\n" % \ (is_predicated)) - f.write(" ctx_log_vreg_write(ctx, %s%sN, %s, %s);\n" % \ - (regtype, regid, newv, is_predicated)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): @@ -520,8 +504,6 @@ def genptr_dst_write_ext(f, tag, regtype, regid, newv= =3D"EXT_DFL"): f.write(" gen_log_qreg_write(%s%sV_off, %s%sN, %s, " % \ (regtype, regid, regtype, regid, newv)) f.write("insn->slot, %s);\n" % (is_predicated)) - f.write(" ctx_log_qreg_write(ctx, %s%sN, %s);\n" % \ - (regtype, regid, is_predicated)) else: print("Bad register parse: ", regtype, regid) else: --=20 2.17.1