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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:34:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h4URkCnDXZ52ZiFju+e2eRoOimDur6z8+OMmjMNkZuk=; b=gByYQlK2ZAa5QNI5o4XJJUmRXJH9N3wKYBZGeZnzfZOAd4FLDEd/A28Q8nJD+3Xv6l /iptq/wcUiux9E3RTHIyybNCPtI64QewsHm/V8jZ3EcwsBHofPfH6XRFPxfWyTkiWUBT QgRnogUyjeGwvBTUFVRnz/4hz+2/71P/UuD6kaCPC9BfAO4LhY3Y1VKCMDwYNfAZK69x il+aPP18PbsngrNf+lvauEtAyczfX4DsGroFWuuh2CsgTtVGxsohuVOyWD1W1sDLMZVA T5u6D2dzbKzcKPn736HD8eWa1uUH2xf+unJyVswml2Gn+H2l+Y+YAtX9IBvnzAb0soQY jYhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h4URkCnDXZ52ZiFju+e2eRoOimDur6z8+OMmjMNkZuk=; b=eeOqIlYIkhTQhZEofLQ5GyekxB4ls9bvtZwZpwMRWWOpx+zX2lARxsgr7HlhD3RMX+ 8dkcFuk0zn/ITM1ZuemMdciIlQ5WBfRyZs4vpY+wNqMqhBFtibBh7iyvwvvmVXsGr+uz n0tMYJDM+wJoPPSM4ZTVqqlQ6nbIWHNXp9B/WI+3Wyg9JONkuWSBrYWvOC4XoasLmvQG aukDWodcH44+qPtqmpzEUq7e2h3TWd852/hRksmEz2lLcRwtCMA6Zr7G7tNyoGnMHlXl yDLjUhEPkEO1GM+OIRd2WxekUzxC/pvB+9VDRTo9HCXhRpFd6U6iEXEiI9hl3vNnCQLy U92g== X-Gm-Message-State: AFqh2ko58XXnFURt6eTigEMU4jWs+arvFlmHQS3+5UJq9pg/NbyX9Lhc WPb+ldfV+/yhR8byaeke+OY6xs+a76Y/DwGd X-Google-Smtp-Source: AMrXdXu2zf4aEb8AB+SqvyyCGZXC3ba/Z5VSnGT+YBsO2eEwEiiKTCemaQ4ySK4XspmiNqmpI2nmog== X-Received: by 2002:a05:6808:2119:b0:35e:d67e:3dcd with SMTP id r25-20020a056808211900b0035ed67e3dcdmr23167829oiw.58.1672234448363; Wed, 28 Dec 2022 05:34:08 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v3 08/10] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Date: Wed, 28 Dec 2022 10:33:34 -0300 Message-Id: <20221228133336.197467-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221228133336.197467-1-dbarboza@ventanamicro.com> References: <20221228133336.197467-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1672234579097000002 All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng --- hw/riscv/boot.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/opentitan.c | 3 +-- hw/riscv/sifive_e.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 8 files changed, 9 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index f7e806143a..cd9c989edb 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -171,10 +171,11 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, exit(1); } =20 -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { + const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; =20 /* diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1e9b0a420e..82ae5e7023 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 85ffdac5be..64d5d435b9 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..3e3f4b0088 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c40885ed5c..bac394c959 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 0c22978b12..0bba5c1640 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -302,8 +302,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, htif_symbol_callback); =20 if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 02f1369843..c8e35f861e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cfd72ecabf..f94653a09b 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,7 +43,7 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); --=20 2.38.1