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[76.14.210.194]) by smtp.gmail.com with ESMTPSA id cp12-20020a170902e78c00b00187022627d7sm4599716plb.36.2022.12.24.15.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Dec 2022 15:57:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZOnun1gj2MJ7bcEZ/RrytneSuuImjXAZrtV+jstCUNA=; b=kCXoFVORgdO7M1aK713svJr+4aj+zxFcfuOyAU2t2VIKYmm+1CsoA9FnxYyIBsu4jH qMNIpcwiXhxmut6fHn2ax4p1zRDdH0qyUkgaUZlgrthsriY9l0x0mZUlNB4sUtKPhTqL EosS0uJk3ur6IhbTch9o2ks7fmb5hgBWb/rGgb9weEO9FHTkg3ZwE82vp2QYLfrr+Beu OgJn+Z/x/o10d3rtWDquJWLyf2cGf55hbCnM2GbluSt5RK7+y7rCoU1GsMo43nj0bp3O eu2Q4U8vitSBPQwot9Y/EhYaHA28s4fgsd9u8UANGxrnf9uqz24lVZBuyUb07CgsN7h5 Ck7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZOnun1gj2MJ7bcEZ/RrytneSuuImjXAZrtV+jstCUNA=; b=A2ol8qbrLLOngMBuD8ayOCO0NpgvU6BR2Iq8C3El1CjDzVOxZqnQjtL8rlhcuJfIKz iHPR87qhPNv0YX7+InxZG0sqAUpNNhQwOE3nD0rCTBUCoq/noquljHN9L+HVfJsCK5Cz ZGDF6QxmQXqWPfhVhCtZVXDNhzKwkiGOLeYrPOtdFo1/vAQhJu85X/Pkl4xV1RRS9kLn MFk3PL8L9/y9+LragYwZ9aYqmcZKWcaBC0XjvcaUyy60wEeq/pkhh31pIlV9h4wx/T0s /qnALRbtVdF5QuG2jt5U7sB0FIwTahc4hXyIum/UGDvggmcBf9Xw7GUPB7ZzbBEGJDJk a6cA== X-Gm-Message-State: AFqh2krll9B8AsGXeX+4TmvHXpXXeeOxE34AAkoO8H3QBU73cYXAwRvs Tk/HYL2cr9cpd5HZOVAC1gkW8maBeSrFG3f9 X-Google-Smtp-Source: AMrXdXushKzAqITpqRazBdfiDttaXnv7g0ihtgqhbfPdWPtZ+HtBhkl1GDj5oGAs6QsoltZTRAOQLA== X-Received: by 2002:a17:902:b58e:b0:191:24a:63e3 with SMTP id a14-20020a170902b58e00b00191024a63e3mr14393665pls.50.1671926270757; Sat, 24 Dec 2022 15:57:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v5 30/43] tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 Date: Sat, 24 Dec 2022 15:57:07 -0800 Message-Id: <20221224235720.842093-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221224235720.842093-1-richard.henderson@linaro.org> References: <20221224235720.842093-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1671927299087100001 For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND. Otherwise, use TCG_CALL_ARG_NORMAL. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/loongarch64/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/riscv/tcg-target.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/sparc64/tcg-target.h | 2 +- tcg/tci/tcg-target.h | 1 + tcg/tcg.c | 42 ++++++++++++++++++------------------ tcg/ppc/tcg-target.c.inc | 6 +++++- 11 files changed, 35 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d9dd777caa..413a5410c5 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -52,6 +52,7 @@ typedef enum { #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL =20 /* optional instructions */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 09dd0550aa..b7843d2d54 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -89,6 +89,7 @@ extern bool use_neon_instructions; /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN =20 /* optional instructions */ diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 42628a2791..7edb7f1d9a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -98,6 +98,7 @@ typedef enum { #else #define TCG_TARGET_CALL_STACK_OFFSET 0 #endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL =20 extern bool have_bmi1; diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 19d4c07170..e5f7a1f09d 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -93,6 +93,7 @@ typedef enum { #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL =20 /* optional instructions */ diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index bb7312aed4..15721c3e42 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -88,6 +88,7 @@ typedef enum { # define TCG_TARGET_CALL_STACK_OFFSET 0 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL =20 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >=3D 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 2ab4b8d04a..232537ccea 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -82,6 +82,7 @@ typedef enum { #define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS =3D=3D 32 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3f77fcf5b3..22d70d431b 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -166,9 +166,9 @@ extern uint64_t s390_facilities[3]; /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL =20 -#define TCG_TARGET_EXTEND_ARGS 1 #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 44ac164b31..0044ac8d78 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -71,7 +71,7 @@ typedef enum { #define TCG_TARGET_STACK_BIAS 2047 #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) -#define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL =20 #if defined(__VIS__) && __VIS__ >=3D 0x300 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index e11c293906..d6e0450ed8 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -158,6 +158,7 @@ typedef enum { /* Used for function call generation. */ #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_STACK_ALIGN 8 +#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS =3D=3D 32 # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else diff --git a/tcg/tcg.c b/tcg/tcg.c index 3ca25f7a28..4c397cb0fa 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1494,24 +1494,24 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) } #endif =20 -#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 - for (i =3D 0; i < nargs; ++i) { - int argtype =3D extract32(typemask, (i + 1) * 3, 3); - bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; - bool is_signed =3D argtype & 1; + if (TCG_TARGET_CALL_ARG_I32 =3D=3D TCG_CALL_ARG_EXTEND) { + for (i =3D 0; i < nargs; ++i) { + int argtype =3D extract32(typemask, (i + 1) * 3, 3); + bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; + bool is_signed =3D argtype & 1; =20 - if (is_32bit) { - TCGv_i64 temp =3D tcg_temp_new_i64(); - TCGv_i32 orig =3D temp_tcgv_i32(args[i]); - if (is_signed) { - tcg_gen_ext_i32_i64(temp, orig); - } else { - tcg_gen_extu_i32_i64(temp, orig); + if (is_32bit) { + TCGv_i64 temp =3D tcg_temp_new_i64(); + TCGv_i32 orig =3D temp_tcgv_i32(args[i]); + if (is_signed) { + tcg_gen_ext_i32_i64(temp, orig); + } else { + tcg_gen_extu_i32_i64(temp, orig); + } + args[i] =3D tcgv_i64_temp(temp); } - args[i] =3D tcgv_i64_temp(temp); } } -#endif /* TCG_TARGET_EXTEND_ARGS */ =20 op =3D tcg_emit_op(INDEX_op_call); =20 @@ -1572,16 +1572,16 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int na= rgs, TCGTemp **args) tcg_debug_assert(TCGOP_CALLI(op) =3D=3D real_args); tcg_debug_assert(pi <=3D ARRAY_SIZE(op->args)); =20 -#if defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS =3D=3D 64 - for (i =3D 0; i < nargs; ++i) { - int argtype =3D extract32(typemask, (i + 1) * 3, 3); - bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; + if (TCG_TARGET_CALL_ARG_I32 =3D=3D TCG_CALL_ARG_EXTEND) { + for (i =3D 0; i < nargs; ++i) { + int argtype =3D extract32(typemask, (i + 1) * 3, 3); + bool is_32bit =3D (argtype & ~1) =3D=3D dh_typecode_i32; =20 - if (is_32bit) { - tcg_temp_free_internal(args[i]); + if (is_32bit) { + tcg_temp_free_internal(args[i]); + } } } -#endif /* TCG_TARGET_EXTEND_ARGS */ } =20 static void tcg_reg_alloc_start(TCGContext *s) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index c2e6bc3296..38ee9974cd 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -44,6 +44,11 @@ # endif #endif =20 +#if TCG_TARGET_REG_BITS =3D=3D 64 +# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND +#else +# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#endif #ifdef _CALL_SYSV # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN #else @@ -2520,7 +2525,6 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int co= unt) =20 /* Parameters for function call generation, used in tcg.c. */ #define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_EXTEND_ARGS 1 =20 #ifdef _CALL_AIX # define LINK_AREA_SIZE (6 * SZR) --=20 2.34.1