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[76.14.210.194]) by smtp.gmail.com with ESMTPSA id cp12-20020a170902e78c00b00187022627d7sm4599716plb.36.2022.12.24.15.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Dec 2022 15:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7stba5MTNOn1+WsG6fk76btOm9hVHehrjjbFHXB3kBc=; b=ysibz+0g/fOp5XTJCMciuWFXemxX2UceDlm3dL7N26FaCVK+WeETlarc6Gztx6H9+j MuGAxvhaGe85a4qo28mkh81i3s6bnQ9ybQOFxylavoLMUiVmP72LnZ2Nr3lHGPmem9qV 1X5zBOYftBXMVOlD7zAlk11amcQhKel1bGOb3JHgup6UimAvkKS0RQkWm2XdzJY0J+IS vzAt4hlobqqa7DbiE0Ka60bhx0xWiqE65kBBEbe8lUNEVIu1uK+DKUsPRIB3PQKLBCRm pETgeto6kY6Z8/DYGn55v4szbmJusDtzC0OHZkGpsHH77PcNnKvCXqgkzsAt/IE5b/OD RR1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7stba5MTNOn1+WsG6fk76btOm9hVHehrjjbFHXB3kBc=; b=ngNdnPw0tWHra1wNI3ErWQixxg2GPhIB9Hkl80czF35sZ//dIqLXLFS7h3zkfloC96 YmsMMOr09ft5r+9bopqbGyAbgcsyaHm+FPbFUTyMOu5+a4L6IJ6xGcHlZIdO4GhNNz62 FC8S/Q7OUIJHfaKsefPyBf5ehPSkTo36ahgLiBhlLuO44HY4K/aOJXkYuqaWG+5oDJxb xpyMmOtfDWuO78sC367OuxU23FdPxgNv9dJotjdTKTA9OsTuoNkoVc02RQrGjvlaJ6Dn NcqetVy+dnzPOp6Yw47OXFkTFise3MD3v5fJxRi7Hy5y+byhSnEBW1Z/JuAApgmbVgTR Sufw== X-Gm-Message-State: AFqh2ko4jrS8x3y+hd4cz45sGJ8M8PcMiTDMvERo/gkG18yB/Y79OzU8 eGVzXVsRnldf/N3vHI+0IupK9nrgKNhzfoez X-Google-Smtp-Source: AMrXdXv4oYPJ+PVCDrAgl6S6Tg/Hsf+qUB/muhGCRanEXLMLF/bVvihKQ6Wmz1awX8XEZcKcgzBuLQ== X-Received: by 2002:a17:902:e543:b0:189:a6b4:91ed with SMTP id n3-20020a170902e54300b00189a6b491edmr21479545plf.17.1671926266243; Sat, 24 Dec 2022 15:57:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alex.bennee@linaro.org, philmd@linaro.org Subject: [PATCH v5 25/43] tcg: Allocate TCGTemp pairs in host memory order Date: Sat, 24 Dec 2022 15:57:02 -0800 Message-Id: <20221224235720.842093-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221224235720.842093-1-richard.henderson@linaro.org> References: <20221224235720.842093-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1671926333301100003 Allocate the first of a pair at the lower address, and the second of a pair at the higher address. This will make it easier to find the beginning of the larger memory block. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 ++-- tcg/tcg.c | 58 ++++++++++++++++++++++------------------------ 2 files changed, 30 insertions(+), 32 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index a9ea27f67a..2c06b5116a 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -62,11 +62,11 @@ static inline unsigned tcg_call_flags(TCGOp *op) #if TCG_TARGET_REG_BITS =3D=3D 32 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) { - return temp_tcgv_i32(tcgv_i64_temp(t)); + return temp_tcgv_i32(tcgv_i64_temp(t) + HOST_BIG_ENDIAN); } static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) { - return temp_tcgv_i32(tcgv_i64_temp(t) + 1); + return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN); } #else extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachab= le"); diff --git a/tcg/tcg.c b/tcg/tcg.c index 36a33a122c..dbf4e864eb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -887,10 +887,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCG= v_ptr base, TCGContext *s =3D tcg_ctx; TCGTemp *base_ts =3D tcgv_ptr_temp(base); TCGTemp *ts =3D tcg_global_alloc(s); - int indirect_reg =3D 0, bigendian =3D 0; -#if HOST_BIG_ENDIAN - bigendian =3D 1; -#endif + int indirect_reg =3D 0; =20 switch (base_ts->kind) { case TEMP_FIXED: @@ -916,7 +913,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv= _ptr base, ts->indirect_reg =3D indirect_reg; ts->mem_allocated =3D 1; ts->mem_base =3D base_ts; - ts->mem_offset =3D offset + bigendian * 4; + ts->mem_offset =3D offset; pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_0"); ts->name =3D strdup(buf); @@ -927,7 +924,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv= _ptr base, ts2->indirect_reg =3D indirect_reg; ts2->mem_allocated =3D 1; ts2->mem_base =3D base_ts; - ts2->mem_offset =3D offset + (1 - bigendian) * 4; + ts2->mem_offset =3D offset + 4; ts2->temp_subindex =3D 1; pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_1"); @@ -1073,37 +1070,43 @@ TCGTemp *tcg_constant_internal(TCGType type, int64_= t val) =20 ts =3D g_hash_table_lookup(h, &val); if (ts =3D=3D NULL) { + int64_t *val_ptr; + ts =3D tcg_temp_alloc(s); =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && type =3D=3D TCG_TYPE_I64) { TCGTemp *ts2 =3D tcg_temp_alloc(s); =20 + tcg_debug_assert(ts2 =3D=3D ts + 1); + ts->base_type =3D TCG_TYPE_I64; ts->type =3D TCG_TYPE_I32; ts->kind =3D TEMP_CONST; ts->temp_allocated =3D 1; - /* - * Retain the full value of the 64-bit constant in the low - * part, so that the hash table works. Actual uses will - * truncate the value to the low part. - */ - ts->val =3D val; =20 - tcg_debug_assert(ts2 =3D=3D ts + 1); ts2->base_type =3D TCG_TYPE_I64; ts2->type =3D TCG_TYPE_I32; ts2->kind =3D TEMP_CONST; ts2->temp_allocated =3D 1; ts2->temp_subindex =3D 1; - ts2->val =3D val >> 32; + + /* + * Retain the full value of the 64-bit constant in the low + * part, so that the hash table works. Actual uses will + * truncate the value to the low part. + */ + ts[HOST_BIG_ENDIAN].val =3D val; + ts[!HOST_BIG_ENDIAN].val =3D val >> 32; + val_ptr =3D &ts[HOST_BIG_ENDIAN].val; } else { ts->base_type =3D type; ts->type =3D type; ts->kind =3D TEMP_CONST; ts->temp_allocated =3D 1; ts->val =3D val; + val_ptr =3D &ts->val; } - g_hash_table_insert(h, &ts->val, ts); + g_hash_table_insert(h, val_ptr, ts); } =20 return ts; @@ -1515,13 +1518,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nar= gs, TCGTemp **args) pi =3D 0; if (ret !=3D NULL) { if (TCG_TARGET_REG_BITS < 64 && (typemask & 6) =3D=3D dh_typecode_= i64) { -#if HOST_BIG_ENDIAN - op->args[pi++] =3D temp_arg(ret + 1); - op->args[pi++] =3D temp_arg(ret); -#else op->args[pi++] =3D temp_arg(ret); op->args[pi++] =3D temp_arg(ret + 1); -#endif nb_rets =3D 2; } else { op->args[pi++] =3D temp_arg(ret); @@ -1555,8 +1553,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) } =20 if (TCG_TARGET_REG_BITS < 64 && is_64bit) { - op->args[pi++] =3D temp_arg(args[i] + HOST_BIG_ENDIAN); - op->args[pi++] =3D temp_arg(args[i] + !HOST_BIG_ENDIAN); + op->args[pi++] =3D temp_arg(args[i]); + op->args[pi++] =3D temp_arg(args[i] + 1); real_args +=3D 2; continue; } @@ -4074,14 +4072,14 @@ static bool tcg_reg_alloc_dup2(TCGContext *s, const= TCGOp *op) } =20 /* If the two inputs form one 64-bit value, try dupm_vec. */ - if (itsl + 1 =3D=3D itsh && itsl->base_type =3D=3D TCG_TYPE_I64) { - temp_sync(s, itsl, s->reserved_regs, 0, 0); - temp_sync(s, itsh, s->reserved_regs, 0, 0); -#if HOST_BIG_ENDIAN - TCGTemp *its =3D itsh; -#else - TCGTemp *its =3D itsl; -#endif + if (itsl->temp_subindex =3D=3D HOST_BIG_ENDIAN && + itsh->temp_subindex =3D=3D !HOST_BIG_ENDIAN && + itsl =3D=3D itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { + TCGTemp *its =3D itsl - HOST_BIG_ENDIAN; + + temp_sync(s, its + 0, s->reserved_regs, 0, 0); + temp_sync(s, its + 1, s->reserved_regs, 0, 0); + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, its->mem_base->reg, its->mem_offset)) { goto done; --=20 2.34.1