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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1671662458; x=1674254459; bh=6Q1etqXq6mt77HOH60 8vmTWlV47LCAy3tVEsE1U6I48=; b=C2Ukcq3lWPLR4H0MxLBRZCNIJg/eqQc9tt Ii/qxBty7T7rb1j7kXhuvKkspHHf7+SZ+ggOHk/HRgywFNPRgZkUrcfukHlsFFb3 3olwDmyx+AfWK9Uq0L7cj6qwVDggLfBHOyD9/vqTb8n1ZovpAHXW5fQOZCLnGGSj Hzy2GkysnOi2zzuY9Wsm6aeRdKLqrgPVolU2IRafw8A6BDUkuiy+GTOfVRy33vsG ThEVoLBYDYfouoRniHy5yG3hfJjSzFTAlx8uE8ryi1g/FeDEFgEj8j9meqHZK6wK ohvo97jspmAYPM8VNub6iF+3p+iqJUnZr7yUQM7C6OUmfzOzrBuA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Alistair Francis Subject: [PULL v2 14/45] target/riscv: Enable native debug itrigger Date: Thu, 22 Dec 2022 08:39:51 +1000 Message-Id: <20221221224022.425831-15-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1671662533674100001 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei When QEMU is not in icount mode, execute instruction one by one. The tdata1 can be read directly. When QEMU is in icount mode, use a timer to simulate the itrigger. The tdata1 may be not right because of lazy update of count in tdata1. Thus, We should pack the adjusted count into tdata1 before read it back. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/debug.c | 72 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 371862cf38..b3574b250f 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -624,10 +624,80 @@ void riscv_itrigger_update_priv(CPURISCVState *env) riscv_itrigger_update_count(env); } =20 +static target_ulong itrigger_validate(CPURISCVState *env, + target_ulong ctrl) +{ + target_ulong val; + + /* validate the generic part first */ + val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT); + + /* validate unimplemented (always zero) bits */ + warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action"); + warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit"); + warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending"); + + /* keep the mode and attribute bits */ + val |=3D ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S | + ITRIGGER_M | ITRIGGER_COUNT); + + return val; +} + +static void itrigger_reg_write(CPURISCVState *env, target_ulong index, + int tdata_index, target_ulong val) +{ + target_ulong new_val; + + switch (tdata_index) { + case TDATA1: + /* set timer for icount */ + new_val =3D itrigger_validate(env, val); + if (new_val !=3D env->tdata1[index]) { + env->tdata1[index] =3D new_val; + if (icount_enabled()) { + env->last_icount =3D icount_get_raw(); + /* set the count to timer */ + timer_mod(env->itrigger_timer[index], + env->last_icount + itrigger_get_count(env, index= )); + } + } + break; + case TDATA2: + qemu_log_mask(LOG_UNIMP, + "tdata2 is not supported for icount trigger\n"); + break; + case TDATA3: + qemu_log_mask(LOG_UNIMP, + "tdata3 is not supported for icount trigger\n"); + break; + default: + g_assert_not_reached(); + } + + return; +} + +static int itrigger_get_adjust_count(CPURISCVState *env) +{ + int count =3D itrigger_get_count(env, env->trigger_cur), executed; + if ((count !=3D 0) && check_itrigger_priv(env, env->trigger_cur)) { + executed =3D icount_get_raw() - env->last_icount; + count +=3D executed; + } + return count; +} + target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) { + int trigger_type; switch (tdata_index) { case TDATA1: + trigger_type =3D extract_trigger_type(env, env->tdata1[env->trigge= r_cur]); + if ((trigger_type =3D=3D TRIGGER_TYPE_INST_CNT) && icount_enabled(= )) { + return deposit64(env->tdata1[env->trigger_cur], 10, 14, + itrigger_get_adjust_count(env)); + } return env->tdata1[env->trigger_cur]; case TDATA2: return env->tdata2[env->trigger_cur]; @@ -656,6 +726,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_inde= x, target_ulong val) type6_reg_write(env, env->trigger_cur, tdata_index, val); break; case TRIGGER_TYPE_INST_CNT: + itrigger_reg_write(env, env->trigger_cur, tdata_index, val); + break; case TRIGGER_TYPE_INT: case TRIGGER_TYPE_EXCP: case TRIGGER_TYPE_EXT_SRC: --=20 2.38.1