From nobody Mon Feb 9 11:32:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1671647088; cv=none; d=zohomail.com; s=zohoarc; b=EJFbkpLdLV+I9Pqv+ELIoih0Kme9jy4+MDfIAkwKmG4HushMuThDLAEc4q5e9UIYK6LL2I90H2iXjySsV6Aa+yVhjrLTDjYgitOaGCIMlmlxP96dK8ts9xTtI+awdzojtbjLSgJuG+wxieJ4+Eq4Y+G+Jk9SHqDCB8KLIKX2oWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671647088; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YZdFtJ+Ib6cOG1cjexHN2bKEmyb+yFYcJLvdmuWEz4U=; b=EymKefA0aVERBmOsjgAtKGcSDhE2a6g3LnUeAuaLkZ80Ur03/xRRiJ/QpmRtpAHKm4iNE1afwx7YIaPzoHdjqoxE++WE9ekZPNK/H6or/N4Gk4uQjsnJjONaDkquNEH/s4qrBgR9i9SHNt0210s4EorwDYg5X1vhl6gRbNbF+UI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16716470889461001.8572841182126; Wed, 21 Dec 2022 10:24:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p83ko-0008Ma-3w; Wed, 21 Dec 2022 13:23:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p83kn-0008LQ-D7 for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:45 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p83kl-0007qV-Hy for qemu-devel@nongnu.org; Wed, 21 Dec 2022 13:23:44 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-14449b7814bso20155231fac.3 for ; Wed, 21 Dec 2022 10:23:43 -0800 (PST) Received: from fedora.. (201-43-103-101.dsl.telesp.net.br. [201.43.103.101]) by smtp.gmail.com with ESMTPSA id w8-20020a056871060800b0014c8685f229sm514577oan.10.2022.12.21.10.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 10:23:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YZdFtJ+Ib6cOG1cjexHN2bKEmyb+yFYcJLvdmuWEz4U=; b=d2u5eBq376GcfsWJzOdvL89wnzregggnTUZHLJUOjGDmGzazp8X+V4V79p+pZM/A4m p4+LPuzEcRmrLhBn0SLfPfZkSD0UpJ3VaZ/jw7FHTKKF5St8QGlRXrSDhlDXJfZ3tw9/ huJXdXcDgOB1nSDtZCPsi3NmS76gGR53GiuDrCY6JKgIzjpC6/oHdFUOUsSv8FuKWt/V /A7PKhG6s1OhLeIORIvInKx+IAsRNkO/ZyLolBPt9l0RmBWCfS7Wh1VLcWqFWNaWtBPC kxHlY4hcnVOwgbX7U9clpf2+xRFXmAx8jD/s+zcQ5rDHYUn4SSEhKzPMHyyE7J3K1rZ1 wzqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YZdFtJ+Ib6cOG1cjexHN2bKEmyb+yFYcJLvdmuWEz4U=; b=tLCq7kPZvTn4vjmopmALbfzrv3QsrTlBtPiXdhOdlbt7AdWNmpp1N+xlyv3AjpnM8C 90vHt/xm8lfSp/B9otGVZt+Mv+fvgzfc2wpyyD3ZBEbc+uPHhSJ56Ev5yiPn2cVnSQQj 6q6Kq4H5w37FJlG6ijb8KdsQyVHUTJ9duK8jRc0QM4LLj9z8mdj5zWw79bbJJQGGGqkZ lPe/Nr3zfCHH0pVDvEL52azjN7yAIEbiBuNEXGPYk2EUdX8gOAaoYlcceNAWmRKgtB53 h4oD7dljqTRJYxzNA+8gJIFoxjTEnEgY1DUpXBkx1qCUBPpIFM5ZRabaxuMgFDu4lrLW 2+tA== X-Gm-Message-State: AFqh2kqEO53xxnNSlUT8l0aLMJHMLZpNOzRe3Noi4DKPcymucDDKicgz zMeSfPDoaYa0fgRErVrTQ9lI66MCPTwYwm2y X-Google-Smtp-Source: AMrXdXtTnYS7zDQ8487j8OcgKFMIYeHmr0u5eFlyHtcfUJjKYCnK1hgEk7nZv+G26+aj9RGBC5uJ2g== X-Received: by 2002:a05:6870:4d03:b0:143:bb26:dd09 with SMTP id pn3-20020a0568704d0300b00143bb26dd09mr1409196oab.35.1671647022597; Wed, 21 Dec 2022 10:23:42 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH 12/15] hw/riscv/boot.c: make riscv_load_initrd() static Date: Wed, 21 Dec 2022 15:22:57 -0300 Message-Id: <20221221182300.307900-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221182300.307900-1-dbarboza@ventanamicro.com> References: <20221221182300.307900-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1671647090788100003 Content-Type: text/plain; charset="utf-8" The only remaining caller is riscv_load_kernel() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 76 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index afe5bae03d..55a3fc1a51 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -160,6 +160,44 @@ target_ulong riscv_load_firmware(const char *firmware_= filename, exit(1); } =20 +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; + hwaddr start, end; + ssize_t size; + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size =3D load_ramdisk(filename, start, mem_size - start); + if (size =3D=3D -1) { + size =3D load_image_targphys(filename, start, mem_size - start); + if (size =3D=3D -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) @@ -209,44 +247,6 @@ out: return kernel_entry; } =20 -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename =3D machine->initrd_filename; - uint64_t mem_size =3D machine->ram_size; - void *fdt =3D machine->fdt; - hwaddr start, end; - ssize_t size; - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size =3D load_ramdisk(filename, start, mem_size - start); - if (size =3D=3D -1) { - size =3D load_image_targphys(filename, start, mem_size - start); - if (size =3D=3D -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end =3D start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 2256b04986..fde0633573 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,7 +44,6 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.38.1