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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671573995; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JEbhiLQ2GQcRGDL18XkLMZphLvwc1KZfcAacZO5hMYQ=; b=cHtnGp8bfaU4T+aiuafhnlg3kmaaDRvzjVStDKU5LcrQbabRj0QVsbgBSt70oEjWm/0+Bk bspqNfZ5fwv7uGCQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH v2 1/5] target/arm: rename handle_semihosting to tcg_handle_semihosting Date: Tue, 20 Dec 2022 19:04:22 -0300 Message-Id: <20221220220426.8827-2-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221220220426.8827-1-farosas@suse.de> References: <20221220220426.8827-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671574130828100001 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana make it clearer from the name that this is a tcg-only function. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- This function moves elsewhere in the original series, but the name change doesn't need to wait. Originally from: [RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihos= ting https://lore.kernel.org/r/20210416162824.25131-39-cfontana@suse.de --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bac2ea62c4..fa741d5175 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10293,7 +10293,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) * trapped to the hypervisor in KVM. */ #ifdef CONFIG_TCG -static void handle_semihosting(CPUState *cs) +static void tcg_handle_semihosting(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -10354,7 +10354,7 @@ void arm_cpu_do_interrupt(CPUState *cs) */ #ifdef CONFIG_TCG if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - handle_semihosting(cs); + tcg_handle_semihosting(cs); return; } #endif --=20 2.35.3 From nobody Tue May 21 11:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671573998; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4l3aPimV1WvtceSCfFT2IaNHN1avZuclDPHJDPo551U=; b=mfWdZ5xnjwxxNS8yXf43GOZHhlMje+57lU327Uw/zT02ppNhIQI1dASG+2C+R2jPLrZDto +rOy/AqJjRIpasCQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH v2 2/5] target/arm: wrap psci call with tcg_enabled Date: Tue, 20 Dec 2022 19:04:23 -0300 Message-Id: <20221220220426.8827-3-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221220220426.8827-1-farosas@suse.de> References: <20221220220426.8827-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671574181024100001 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana for "all" builds (tcg + kvm), we want to avoid doing the psci check if tcg is built-in, but not enabled. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- Originally from: [RFC v14 39/80] target/arm: replace CONFIG_TCG with tcg_enabled https://lore.kernel.org/r/20210416162824.25131-40-cfontana@suse.de --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fa741d5175..193e0ef8fb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,6 +26,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -10341,7 +10342,7 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } =20 - if (arm_is_psci_call(cpu, cs->exception_index)) { + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); return; --=20 2.35.3 From nobody Tue May 21 11:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671574001; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y5V1jhX9pzm3fTgmfFkuVCIs6JasO5NGiAX8tVgYFz8=; b=Je5u/Xxs8qmLDj+Pr92UO6qG1/gNoMfU1Irh/HoMmHt+v/XbI9ir7oSjeAQDZSAVa0ZziC wtUGAegM3FKln+Cw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH v2 3/5] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Date: Tue, 20 Dec 2022 19:04:24 -0300 Message-Id: <20221220220426.8827-4-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221220220426.8827-1-farosas@suse.de> References: <20221220220426.8827-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671574084959100001 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Fabiano Rosas --- Originally from: [RFC v14 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabl= ed() https://lore.kernel.org/r/20210416162824.25131-43-cfontana@suse.de --- target/arm/helper.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 193e0ef8fb..f33687e98d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10107,11 +10107,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState= *cs) unsigned int cur_el =3D arm_current_el(env); int rt; =20 - /* - * Note that new_el can never be 0. If cur_el is 0, then - * el0_a64 is is_a64(), else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + if (tcg_enabled()) { + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + } =20 if (cur_el < new_el) { /* Entry vector offset depends on whether the implemented EL --=20 2.35.3 From nobody Tue May 21 11:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1671574064; cv=none; d=zohomail.com; s=zohoarc; b=CGorsGKW63FIxsk387UQF48HGj4iHw8ceqlqd9FnSnMUgl4k3i3wxorCwg0mWvaMMfJtBEqGzoM4MVdpL2riRf5qLP8E+F0dK3e3KNlSrmPbxyeDkb31l0DId+i40CxonBYF46NAemYLVqDprOI6W1k6jflsLZ9E1IXM9QGvyYg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671574064; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/7BcAL3xC8nxLYT+T8cHD52ZC0T+NIcGPKCGSYbSUow=; b=KQwpQn6t6ExZ1z9/7kSB2cpYKtAbFZ9v7sCtocWaOieg4tsbjKhX1fLRz4J5pifEGVxLZI uGH+r3xTMCBusc0tVelLOm9HPsgIPvKztWuXfRwxmRubS2ECg4Ohc3SL3dBgCSzHL03PaN qiMVKATGV7eppTTLpg8VxbjpawyxRac= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671574005; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/7BcAL3xC8nxLYT+T8cHD52ZC0T+NIcGPKCGSYbSUow=; b=Be1Ux2VHUQlhwgbEaXmFn49GDfKkw8FnPJPn4vl0cOTl6yVdX9xn8ZSceUqY3qI1Hr5fHL 8pNpT391wSP+lhAA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH v2 4/5] target/arm: Move PC alignment check Date: Tue, 20 Dec 2022 19:04:25 -0300 Message-Id: <20221220220426.8827-5-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221220220426.8827-1-farosas@suse.de> References: <20221220220426.8827-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671574067215100001 Content-Type: text/plain; charset="utf-8" Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- target/arm/machine.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433..a186787d2b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -811,6 +811,15 @@ static int cpu_post_load(void *opaque, int version_id) } } =20 + /* + * Misaligned thumb pc is architecturally impossible. Fail the + * incoming migration. For TCG it would trigger the assert in + * thumb_tr_translate_insn(). + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); =20 @@ -828,15 +837,6 @@ static int cpu_post_load(void *opaque, int version_id) } } =20 - /* - * Misaligned thumb pc is architecturally impossible. - * We have an assert in thumb_tr_translate_insn to verify this. - * Fail an incoming migrate to avoid this assert. - */ - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { - return -1; - } - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } --=20 2.35.3 From nobody Tue May 21 11:58:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1671574106; cv=none; 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Tue, 20 Dec 2022 22:06:45 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id IKAtEvUxomPwfAAAMHmgww (envelope-from ); Tue, 20 Dec 2022 22:06:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1671574008; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uNooRhtg57jwueZDg2HkPFfIvQcQ1FUxw6N+xDzNzjc=; b=ZjFyKStgZIG4w5VtecSY3HY3t9sRva9i42R+iLExDXf5Ge541G4aYWgDPUZ+Ica3gIkwO3 ANNN9WB69k5CjVd+12IXJVUoRwO29FMSLVgqtrtjSGMfh28NPVFwACHsbwZ1CGsaWPRcZ+ VkQV1yMFpfHVof420vQ6tSdTkmQXN0U= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671574008; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uNooRhtg57jwueZDg2HkPFfIvQcQ1FUxw6N+xDzNzjc=; b=TuAuMyq4RMxDU16RnMD4lEl3MXZ/wY2Bf/g1rc5eZD43TkTx4JbRGya1qPGdmLK8PCjAlX HJx48XYDxxFnwoAQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH v2 5/5] target/arm: only perform TCG cpu and machine inits if TCG enabled Date: Tue, 20 Dec 2022 19:04:26 -0300 Message-Id: <20221220220426.8827-6-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221220220426.8827-1-farosas@suse.de> References: <20221220220426.8827-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671574108776100003 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana of note, cpreg lists were previously initialized by TCG first, and then thrown away and replaced with the data coming from KVM. Now we just initialize once, either for TCG or for KVM. Signed-off-by: Claudio Fontana [moved arm_cpu_register_gdb_regs_for_features out of tcg_enabled] Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- Originally from: [RFC v14 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled https://lore.kernel.org/r/20210416162824.25131-17-cfontana@suse.de --- target/arm/cpu.c | 31 +++++++++++++++++------------- target/arm/kvm.c | 18 +++++++++--------- target/arm/kvm_arm.h | 3 +-- target/arm/machine.c | 45 +++++++++++++++++++++++++------------------- 4 files changed, 54 insertions(+), 43 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2fa022f62b..fdf30e7268 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -525,9 +525,11 @@ static void arm_cpu_reset_hold(Object *obj) } #endif =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); - arm_rebuild_hflags(env); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); + } } =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) @@ -1600,6 +1602,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 +#ifdef CONFIG_TCG { uint64_t scale; =20 @@ -1625,7 +1628,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, arm_gt_hvtimer_cb, cpu); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { @@ -1943,17 +1947,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - pmu_init(cpu); - - if (!kvm_enabled()) { + if (tcg_enabled()) { + pmu_init(cpu); arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); - } =20 #ifndef CONFIG_USER_ONLY - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_= cb, - cpu); + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_ti= mer_cb, + cpu); #endif + } } else { cpu->isar.id_aa64dfr0 =3D FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); @@ -2049,10 +2052,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) set_feature(env, ARM_FEATURE_VBAR); } =20 - register_cp_regs_for_features(cpu); - arm_cpu_register_gdb_regs_for_features(cpu); + if (tcg_enabled()) { + register_cp_regs_for_features(cpu); + init_cpreg_list(cpu); + } =20 - init_cpreg_list(cpu); + arm_cpu_register_gdb_regs_for_features(cpu); =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2..2f01c26f54 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -438,9 +438,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, ui= nt64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } =20 -/* Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). +/* + * Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about. + * + * The parallel for TCG is init_cpreg_list() */ int kvm_arm_init_cpreg_list(ARMCPU *cpu) { @@ -482,12 +484,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) arraylen++; } =20 - cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); - cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, arraylen); - cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, - arraylen); - cpu->cpreg_vmstate_values =3D g_renew(uint64_t, cpu->cpreg_vmstate_val= ues, - arraylen); + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); cpu->cpreg_array_len =3D arraylen; cpu->cpreg_vmstate_array_len =3D arraylen; =20 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 99017b635c..41de2a7cf1 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -70,8 +70,7 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t d= evid, uint64_t group, * @cpu: ARMCPU * * Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). + * definition of what CPU registers it knows about. * * Returns: 0 if success, else < 0 error code */ diff --git a/target/arm/machine.c b/target/arm/machine.c index a186787d2b..5ac1e6173a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" @@ -687,7 +688,7 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -722,7 +723,7 @@ static int cpu_post_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_finish(&cpu->env); } =20 @@ -741,7 +742,7 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state =3D UINT32_MAX; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -820,27 +821,28 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); =20 - /* - * TCG gen_update_fp_context() relies on the invariant that - * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; - * forbid bogus incoming data with some other value. - */ - if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)= ) { - if (extract32(env->v7m.fpdscr[M_REG_NS], - FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4 || - extract32(env->v7m.fpdscr[M_REG_S], - FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4) { - return -1; + /* + * TCG gen_update_fp_context() relies on the invariant that + * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extensi= on; + * forbid bogus incoming data with some other value. + */ + if (arm_feature(env, ARM_FEATURE_M) && + cpu_isar_feature(aa32_lob, cpu)) { + if (extract32(env->v7m.fpdscr[M_REG_NS], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4 = || + extract32(env->v7m.fpdscr[M_REG_S], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4)= { + return -1; + } } - } =20 - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); + arm_rebuild_hflags(&cpu->env); } - arm_rebuild_hflags(&cpu->env); =20 return 0; } @@ -890,8 +892,13 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), +#ifdef CONFIG_TCG VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), +#else + VMSTATE_UNUSED(sizeof(QEMUTimer *)), + VMSTATE_UNUSED(sizeof(QEMUTimer *)), +#endif /* CONFIG_TCG */ { .name =3D "power_state", .version_id =3D 0, --=20 2.35.3