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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1671416337; x=1674008338; bh=33ydBuzuBnZFvlbDBH 6+hF4mtGaD+zrqRMjuDlazzLE=; b=C6I5OiEII5WEu/vDcZ70Osc+DMyQLeKBov /prYcM4VgEh6jjywoChAlE0KqgLdo44WPgsGSmepfreIwez3YT5iLiYS93g7e+Wd tWqCokieFAlkTwr6nxDZAeZzLoKooMU/AtxLlac/bsB2/VoYEqAoeZ/WAPunhtp2 suSeRhrQR8NXlUVeuMaTK8Nv2q5lIYI89mgBrIADJXhJaxnginjR+B0U9/mBuzre PMnyymrdu6pcAi7EHurIV7v3cPWaOWXGlmUCsrWlpjrSRUDBJ6ctO78cJ+1/3ftW eA6Kn/1Qs4uU4slMQZzqKptuHz5t1Iy6MmY8LeDOfIfs6S62bE6A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , Wilfred Mallawa Subject: [PULL 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Date: Mon, 19 Dec 2022 12:17:01 +1000 Message-Id: <20221219021703.20473-44-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com> References: <20221219021703.20473-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=345d64987=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1671416614304100007 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note the irq number calculation in sifive_plic_{read,write} is correct as the codes make up for the irq number by adding 1. Let's simply update "priority-base" to start from interrupt source 0 and add a comment to make it crystal clear. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa Message-Id: <20221211030829.802437-14-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 2 +- include/hw/riscv/shakti_c.h | 2 +- include/hw/riscv/sifive_e.h | 2 +- include/hw/riscv/sifive_u.h | 2 +- include/hw/riscv/virt.h | 2 +- hw/intc/sifive_plic.c | 5 +++-- 6 files changed, 8 insertions(+), 7 deletions(-) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index 577efad0c4..e65ffeb02d 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -155,7 +155,7 @@ enum { =20 #define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 -#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 #define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 #define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index daf0aae13f..539fe1156d 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -65,7 +65,7 @@ enum { #define SHAKTI_C_PLIC_NUM_SOURCES 28 /* Excluding Priority 0 */ #define SHAKTI_C_PLIC_NUM_PRIORITIES 2 -#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04 +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00 #define SHAKTI_C_PLIC_PENDING_BASE 0x1000 #define SHAKTI_C_PLIC_ENABLE_BASE 0x2000 #define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 9e58247fd8..b824a79e2d 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -89,7 +89,7 @@ enum { */ #define SIFIVE_E_PLIC_NUM_SOURCES 53 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 -#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 +#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 8f63a183c4..e680d61ece 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -158,7 +158,7 @@ enum { =20 #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 -#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04 +#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e1ce0048af..3407c9e8dd 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -98,7 +98,7 @@ enum { #define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 #define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) =20 -#define VIRT_PLIC_PRIORITY_BASE 0x04 +#define VIRT_PLIC_PRIORITY_BASE 0x00 #define VIRT_PLIC_PENDING_BASE 0x1000 #define VIRT_PLIC_ENABLE_BASE 0x2000 #define VIRT_PLIC_ENABLE_STRIDE 0x80 diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 1edeb1e1ed..1a792cc3f5 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -140,7 +140,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr a= ddr, unsigned size) SiFivePLICState *plic =3D opaque; =20 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { - uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; + uint32_t irq =3D (addr - plic->priority_base) >> 2; =20 return plic->source_priority[irq]; } else if (addr_between(addr, plic->pending_base, plic->num_sources >>= 3)) { @@ -187,7 +187,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr= , uint64_t value, SiFivePLICState *plic =3D opaque; =20 if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) { - uint32_t irq =3D ((addr - plic->priority_base) >> 2) + 1; + uint32_t irq =3D (addr - plic->priority_base) >> 2; =20 if (((plic->num_priorities + 1) & plic->num_priorities) =3D=3D 0) { /* @@ -428,6 +428,7 @@ static Property sifive_plic_properties[] =3D { /* number of interrupt sources including interrupt source 0 */ DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1), DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, = 0), + /* interrupt priority register base starting from source 0 */ DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0), DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0), DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0), --=20 2.38.1