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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1671416328; x=1674008329; bh=RignxIYbKCPHxUnIhI qB+bDCTC2InNMQAhk2vcktKns=; b=PYDJjHjNLC1rQdCKSVMqpDaBmtKXMv5VCU FzsIMHg91WUgbZ6ZWWv2dnozHgGAiWzoWOsv/2LuZmOZ+hrOUcjj0TE0ZF7HYS5s QARuHAm27tgrZz+QueiM9wk/7xKE3olmTMWJ6uBcsDTOXU3iNZdXvv8E0fiu5dIh qa6MyAqqp2j2mvTJgzwOZ7+4VwvnlhpUDEnAdm+HlK9Usp6gDeKkoQLRUd1shsJx pp/xiiazyfYY4yc4sAkR7N/44sa5wC7KYzpAD2sXv7x0dxWAPNqMLqjBlAtuNwHh Zfk2BjG81PJ7fvDxE0sef3MVy7kAvkxoaqCwA6QmYk7GnTXm0wQw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Wilfred Mallawa , Alistair Francis Subject: [PULL 40/45] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC Date: Mon, 19 Dec 2022 12:16:58 +1000 Message-Id: <20221219021703.20473-41-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com> References: <20221219021703.20473-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=345d64987=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1671416366112100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 supports 52 interrupt sources while G000 supports 51 interrupt sources. We use the value of G002 and G003, so it is 53 (including source 0). [1] G000 manual: https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_f= e310-g000-manual-v3p2.pdf [2] G002 manual: https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_f= e310-g002-v1p5.pdf [3] G003 manual: https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_f= e310-g003-manual.pdf Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine") Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Message-Id: <20221211030829.802437-11-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_e.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index d738745925..9e58247fd8 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -82,7 +82,12 @@ enum { }; =20 #define SIFIVE_E_PLIC_HART_CONFIG "M" -#define SIFIVE_E_PLIC_NUM_SOURCES 127 +/* + * Freedom E310 G002 and G003 supports 52 interrupt sources while + * Freedom E310 G000 supports 51 interrupt sources. We use the value + * of G002 and G003, so it is 53 (including interrupt source 0). + */ +#define SIFIVE_E_PLIC_NUM_SOURCES 53 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 --=20 2.38.1