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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1671416326; x=1674008327; bh=3esrjL+0ACOe7jvODg Ux8nE+o14tGGAQ9W+P0DFAYvY=; b=gwLdqsleSu4AsS7IUBaE6GMb+L6AH7osH3 YoLF/jRByV/7xkR+vvoBtGi/WuGisXk64dlQuTJbxslLv4CV+le2Yi9F3BrH7HU1 BO7sKwCxc4SDpxEpwWY3EacGqa787HSyTJcEf0Q756MOSQlwVnq63pXiqVhJKeIh c9/Ibm/b4OM8aQVhijD5GvRSwXIAtfHT5tJTjnjZLuzMb8JbjC0gEK4NOw4PhsnV gnVP/bOAS48RHaGRwryeUtu8p3y3H0wUMZ+jLfrMFYwgcMDa/MIT0FXO6JXmHOwg Iu6auIV8ibuhlnUGxBsirSxXvKBTTwUm/UZm3kt07e5txh95sD3g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Wilfred Mallawa , Alistair Francis , Conor Dooley Subject: [PULL 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Date: Mon, 19 Dec 2022 12:16:57 +1000 Message-Id: <20221219021703.20473-40-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221219021703.20473-1-alistair.francis@opensource.wdc.com> References: <20221219021703.20473-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=345d64987=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1671416754987100005 Content-Type: text/plain; charset="utf-8" From: Bin Meng Per chapter 6.5.2 in [1], the number of interupt sources including interrupt source 0 should be 187. [1] PolarFire SoC MSS TRM: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocu= ments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC= .pdf Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC= Icicle Kit board") Signed-off-by: Bin Meng Reviewed-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Conor Dooley Message-Id: <20221211030829.802437-10-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- include/hw/riscv/microchip_pfsoc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index 69a686b54a..577efad0c4 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -153,7 +153,7 @@ enum { #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 =20 -#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 --=20 2.38.1