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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a05600c364700b003d33ab317dasm4135263wmq.14.2022.12.16.13.43.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:43:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bRq697OJRpkwMKWFeobURUSNyr0IVAGEj4jxSGYd0BA=; b=hVWKA9fQ2t/WFzhF/LlZVMHlVn0VG9JBFIsixsL2xWnlUkVBqFUCy34yn9c1BZEHgf /Hb886HyO0fuuez9TQhaARasogVrq90p3AGqDYmjWqxLrdnC1zVKE2ynvAU/2JdlFhXT Xq1Q+zrAk4T4RBUN2sMEBTYinlyDtVBeSbVGMuWCHBVLQbrf1KlKFLjk2wwc9f70I374 6ZG2z93ZAaBYg+iA6aIb0+43Rg7A22UQGe2pjBx/Y9zgro67W+mDYUs0a8HSQT9umZ9c uTqIiSMH9qeJEJV864cxVfeRJbH+60cB12e1rBAbWcTKKGexvYATHpQcTnx5J+dmgYFf 79ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bRq697OJRpkwMKWFeobURUSNyr0IVAGEj4jxSGYd0BA=; b=jbCnVtRdo2HT9atZ9NV7caEX/5jtiH4/hmWAXMOmkUEgekC/mSl2/+TGVCTIGtPtky qIKIJbwHqkAij+/zqnxz26P17Xn+2jdWhB3/nDyYfs67y2AViL7JB7MVNBUbg+LvIPep jRZ0vjTmHntbwugEKyafXWz5jugdoa9GRHVMtfpATblipoVPy3jDld/m34zpQCCFofxS MES9Qll32V+R104ozAgx3ynuDyz0ri+KJmtWZhKNd9HO54PczPubKJPWFEC1CIE2aS/O saRGWHRdqOOGZCGnJStmOZYXGIZCtKPFBsZs3B4YSp0+2X+lSuaG/TH+6ap8o92nw/yY F7kQ== X-Gm-Message-State: AFqh2krbhogsUtQatvDYXwXFwc0xW7UBnGHKZOJGeSx6D9bMTmKLaoid d5OPEnDiAfEB0SiRWT8UxPT8BgukTQAikspf X-Google-Smtp-Source: AMrXdXtLIjFwD5oyukE4kP4wXEH8sYLuiijQXol3sthNGsPajaFF1LccfMT/bM+kVGpDNotQefOl6Q== X-Received: by 2002:a05:600c:5126:b0:3d3:3c60:b2bb with SMTP id o38-20020a05600c512600b003d33c60b2bbmr5903150wms.23.1671226999786; Fri, 16 Dec 2022 13:43:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/36] hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset Date: Fri, 16 Dec 2022 21:42:44 +0000 Message-Id: <20221216214244.1391647-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216214244.1391647-1-peter.maydell@linaro.org> References: <20221216214244.1391647-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1671229741573100001 Convert the TYPE_PHB3_MSI class to 3-phase reset, so we can avoid using the device_class_set_parent_reset() function. Signed-off-by: Peter Maydell Tested-by: Daniel Henrique Barboza Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20221125115240.3005559-8-peter.maydell@linaro.org --- include/hw/ppc/xics.h | 2 +- hw/pci-host/pnv_phb3_msi.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 00b80b08c27..95ead0dd7c9 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -95,7 +95,7 @@ struct ICSStateClass { DeviceClass parent_class; =20 DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; =20 void (*reject)(ICSState *s, uint32_t irq); void (*resend)(ICSState *s); diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index ae908fd9e41..41e63b066f9 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -228,12 +228,14 @@ static void phb3_msi_resend(ICSState *ics) } } =20 -static void phb3_msi_reset(DeviceState *dev) +static void phb3_msi_reset_hold(Object *obj) { - Phb3MsiState *msi =3D PHB3_MSI(dev); - ICSStateClass *icsc =3D ICS_GET_CLASS(dev); + Phb3MsiState *msi =3D PHB3_MSI(obj); + ICSStateClass *icsc =3D ICS_GET_CLASS(obj); =20 - icsc->parent_reset(dev); + if (icsc->parent_phases.hold) { + icsc->parent_phases.hold(obj); + } =20 memset(msi->rba, 0, sizeof(msi->rba)); msi->rba_sum =3D 0; @@ -287,11 +289,12 @@ static void phb3_msi_class_init(ObjectClass *klass, v= oid *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ICSStateClass *isc =3D ICS_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 device_class_set_parent_realize(dc, phb3_msi_realize, &isc->parent_realize); - device_class_set_parent_reset(dc, phb3_msi_reset, - &isc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, phb3_msi_reset_hold, NULL, + &isc->parent_phases); =20 isc->reject =3D phb3_msi_reject; isc->resend =3D phb3_msi_resend; --=20 2.25.1