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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a05600c364700b003d33ab317dasm4135263wmq.14.2022.12.16.13.43.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:43:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wVHkl0SJwne+XihoGUblfNQhtc6oZLY6VgJtTl+eHTg=; b=FCmpYAw630CIzGTFQnm5e10seeZg27awC1jHuFTZSivU22SE2uA7V5DZ/BlZJ3rXtm oaeNvA+hGsg4vl/tLEMZ83+h7Jg+C72nKgG6nRcAb2KlZf4vgXExRBmfH+k+TMC5NUVB TjmwrxDSDucGzUo8gNUc95jDzKjWjjwCjo3ihJrtDJFuC87eWwv/G9lvAB9rxuf42NKp aJjIRGSEInjBKIWfo/uaLRGWtTcbeX1Cpwy5iJ2OQQjzAAh/wz4wpVpmskY54jXFmr4N Z9i7jUfsSmO7icpIIHIkW/SD5FztKAu8VqhFJuTuNVKW5Lr+FasFupR7oARcoooWuye8 n6HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wVHkl0SJwne+XihoGUblfNQhtc6oZLY6VgJtTl+eHTg=; b=BxwRZYjvofDG2LMMD2KMUFWmO1b+rau2HLDqeDb7d5oXrX0ZxbUrefz9WM3PoSWYVV fZm4RoMdA6jQwu9brW5n+JPwa20LHL6iUMAZbZja3JhjHHevnZ8a0snpkpm1/OJ+gx7s 5DzbT0hXjiSD5zE0yG4GPOu4KzOG4cmSxee90959kIHUXTLYJ7Mfu3tssq1F3jCtEw4t AYD1jiruKzfT5YBJK1kyQUnO7y2bz8Hd12Qix5T8b2uUDgUKOWbbGb6f6Jf40eTLY7LQ +S2shOPw/1D6Ib8NoqvCw4bFP+/DmbpIMcjVMOFhQncbvlqHt3E1jYw9oN9pgknUzWXu tlHg== X-Gm-Message-State: ANoB5pmVp8zoi898CEoADYNa7+YGHAzoG1nauDuQJQJ9gfx9GSjC9ZZL zH28H5IwIbwtDIqkh9bjUtO8FC4uI/H6ldHI X-Google-Smtp-Source: AA0mqf5fC7t27/OeKblrJmDmSs6J2MwF4dTCYYY7Rw9D1TuFiXgiyznNXwtQeEazVo4xgeHRGqXRrw== X-Received: by 2002:a05:600c:1e8f:b0:3cf:728e:c224 with SMTP id be15-20020a05600c1e8f00b003cf728ec224mr26222895wmb.6.1671226996409; Fri, 16 Dec 2022 13:43:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/36] pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset Date: Fri, 16 Dec 2022 21:42:40 +0000 Message-Id: <20221216214244.1391647-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216214244.1391647-1-peter.maydell@linaro.org> References: <20221216214244.1391647-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1671228843320100001 Convert the TYPE_PCIE_ROOT_PORT device to 3-phase reset; this is a necessary precursor to converting any of its child classes. Signed-off-by: Peter Maydell Tested-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20221125115240.3005559-4-peter.maydell@linaro.org --- hw/pci-bridge/pcie_root_port.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 460e48269d4..36bc0bafa7e 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -43,9 +43,10 @@ static void rp_write_config(PCIDevice *d, uint32_t addre= ss, pcie_aer_root_write_config(d, address, val, len, root_cmd); } =20 -static void rp_reset(DeviceState *qdev) +static void rp_reset_hold(Object *obj) { - PCIDevice *d =3D PCI_DEVICE(qdev); + PCIDevice *d =3D PCI_DEVICE(obj); + DeviceState *qdev =3D DEVICE(obj); =20 rp_aer_vector_update(d); pcie_cap_root_reset(d); @@ -171,13 +172,14 @@ static void rp_class_init(ObjectClass *klass, void *d= ata) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 k->is_bridge =3D true; k->config_write =3D rp_write_config; k->realize =3D rp_realize; k->exit =3D rp_exit; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset =3D rp_reset; + rc->phases.hold =3D rp_reset_hold; device_class_set_props(dc, rp_props); } =20 --=20 2.25.1