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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671226312; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B5CG4PGerUxdqx8UYWH7MTKHIghaqlUgu4Ciy6KeonQ=; b=ILhXrWT70SZTDPbEQaQJAmp1Y/N7S330dxc+ztyglq0cAxMU9vQbXfbEFUKeGmU1H3qD5L QXKWaf4L5guSBvCQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf Subject: [PATCH 1/5] target/arm: only build psci for TCG Date: Fri, 16 Dec 2022 18:29:40 -0300 Message-Id: <20221216212944.28229-2-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221216212944.28229-1-farosas@suse.de> References: <20221216212944.28229-1-farosas@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671226389354100003 From: Claudio Fontana Signed-off-by: Claudio Fontana Cc: Alexander Graf Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Fabiano Rosas --- Originally from: [RFC v14 09/80] target/arm: only build psci for TCG https://lore.kernel.org/r/20210416162824.25131-10-cfontana@suse.de --- target/arm/meson.build | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 87e911b27f..26e425418f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -61,10 +61,13 @@ arm_softmmu_ss.add(files( 'arm-powerctl.c', 'machine.c', 'monitor.c', - 'psci.c', 'ptw.c', )) =20 +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( + 'psci.c', +)) + subdir('hvf') =20 target_arch +=3D {'arm': arm_ss} --=20 2.35.3 From nobody Sun May 19 13:07:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671226315; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ds1kPSfkEJo2lcQkYVoMrIv8lxj7zxQ5fmyLXqmUynU=; b=A+2cIceqkC8D0ftqaHBEC3JQVMYBFXXL//9xUzjKeJDcRfmNxv8baP90wyT1sBw0gT7htJ jT/U9+a+zU0RLhAw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost Subject: [PATCH 2/5] target/arm: rename handle_semihosting to tcg_handle_semihosting Date: Fri, 16 Dec 2022 18:29:41 -0300 Message-Id: <20221216212944.28229-3-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221216212944.28229-1-farosas@suse.de> References: <20221216212944.28229-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671226473591100003 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana make it clearer from the name that this is a tcg-only function. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- This function moves elsewhere in the original series, but the name change doesn't need to wait. Originally from: [RFC v14 38/80] target/arm: rename handle_semihosting to tcg_handle_semihos= ting https://lore.kernel.org/r/20210416162824.25131-39-cfontana@suse.de --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d8c8223ec3..45bf164a07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10252,7 +10252,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) * trapped to the hypervisor in KVM. */ #ifdef CONFIG_TCG -static void handle_semihosting(CPUState *cs) +static void tcg_handle_semihosting(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -10313,7 +10313,7 @@ void arm_cpu_do_interrupt(CPUState *cs) */ #ifdef CONFIG_TCG if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - handle_semihosting(cs); + tcg_handle_semihosting(cs); return; } #endif --=20 2.35.3 From nobody Sun May 19 13:07:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 16 Dec 2022 21:31:58 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 45E79138FD; Fri, 16 Dec 2022 21:31:56 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id CEQaA8zjnGPAHwAAMHmgww (envelope-from ); Fri, 16 Dec 2022 21:31:56 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_rsa; t=1671226318; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/h/TcKLNuFmV1n9A40Ef7qzjjji24qdhFKETbNQjPjc=; b=nySjFEbtofkCFvI7YoeXMB7pPTGdbjsIFzRfA22TiJM2S9niH5FtxQgO7PaDZCadPqwtQD EwaFbF9S/zVKA5c7YvE7Kf7zflA/UlnN4oLjV6nHe4JrakoVMGf7AvJx1fdYNBrsqCq43/ ap8R+XPD6Af5RLs9UDTRKqodV4N19i8= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671226318; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/h/TcKLNuFmV1n9A40Ef7qzjjji24qdhFKETbNQjPjc=; b=IDU4jFP6OlmUv2Yn4ql79fAapfqffw4sls31S05ckHw+sv1LOdaYhBkeh1Bq5yB+oqeKrT ym2ouLotVqeXE2AQ== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost Subject: [PATCH 3/5] target/arm: wrap semihosting and psci calls with tcg_enabled Date: Fri, 16 Dec 2022 18:29:42 -0300 Message-Id: <20221216212944.28229-4-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221216212944.28229-1-farosas@suse.de> References: <20221216212944.28229-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671226389323100002 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana for "all" builds (tcg + kvm), we want to avoid doing the psci and semihosting checks if tcg is built-in, but not enabled. Signed-off-by: Claudio Fontana Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- Originally from: [RFC v14 39/80] target/arm: replace CONFIG_TCG with tcg_enabled https://lore.kernel.org/r/20210416162824.25131-40-cfontana@suse.de --- target/arm/helper.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 45bf164a07..9d0a53cb00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,6 +26,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -10300,23 +10301,25 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } =20 - if (arm_is_psci_call(cpu, cs->exception_index)) { - arm_handle_psci_call(cpu); - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); - return; - } + if (tcg_enabled()) { + if (arm_is_psci_call(cpu, cs->exception_index)) { + arm_handle_psci_call(cpu); + qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + return; + } =20 - /* - * Semihosting semantics depend on the register width of the code - * that caused the exception, not the target exception level, so - * must be handled here. - */ + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. + */ #ifdef CONFIG_TCG - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - tcg_handle_semihosting(cs); - return; - } + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + tcg_handle_semihosting(cs); + return; + } #endif + } =20 /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of --=20 2.35.3 From nobody Sun May 19 13:07:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671226321; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ArciblxJn99VFUNeKFhgWt1wFbO+tKvCM9aSQYafwj8=; b=UkstPnjvbHbqRHMH7Dqx6/orP9c8eCHCsaFKBxWy/Yl1NSamQZrJLrg5Sgz7OsNK23vA3x g2jiqXpYUpP11MCA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost Subject: [PATCH 4/5] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Date: Fri, 16 Dec 2022 18:29:43 -0300 Message-Id: <20221216212944.28229-5-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221216212944.28229-1-farosas@suse.de> References: <20221216212944.28229-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671226389322100001 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Fabiano Rosas --- Originally from: [RFC v14 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabl= ed() https://lore.kernel.org/r/20210416162824.25131-43-cfontana@suse.de --- target/arm/helper.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9d0a53cb00..92624e2910 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10066,11 +10066,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState= *cs) unsigned int cur_el =3D arm_current_el(env); int rt; =20 - /* - * Note that new_el can never be 0. If cur_el is 0, then - * el0_a64 is is_a64(), else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + if (tcg_enabled()) { + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + } =20 if (cur_el < new_el) { /* Entry vector offset depends on whether the implemented EL --=20 2.35.3 From nobody Sun May 19 13:07:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1671226457; cv=none; d=zohomail.com; s=zohoarc; b=AmD1qKb43ETg3K7O1OKuL426Wk0MJ8+7A4xjMhKf2Qemem5coFU0i8/N3u0oZSpzFwQK4IuPahcn9OMOmt5ayPzNgld7DjCWt6AZxvrkgGhUkTTT0e5U9+HMbT9t2jAmK6haK7uHUJHrExxXn8EPmJG5b0mnlSP7QF9W5Zjb6jQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1671226457; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oaMji3BzjI1LDTZ9j5iQcgfYvZl5G6sjaUFCXl3i2g8=; b=cDzgkl87KhpljZie7uTde9BEePAMjXe8dxXZt0/Ya6gGHiOWUewVp4oVnWRt4USXFrFJ8N ESEaGvyeVBubnwNyJ5Li/aWgdWqkJbleVF+TBl6p3nYEf2Bv881+bxuMHclAZkDnRutlO2 WVphC5t9AmEM0yxHW01C1ihIHE6/SbY= DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1671226324; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oaMji3BzjI1LDTZ9j5iQcgfYvZl5G6sjaUFCXl3i2g8=; b=KUPx8av4bI86SHzKDjoTLf0AX0T7KguYqPKHs0Yt9hePJvEq1DFF2xiP24907OMAIspdMB Ps6cPGYTbA4onrBw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost Subject: [PATCH 5/5] target/arm: only perform TCG cpu and machine inits if TCG enabled Date: Fri, 16 Dec 2022 18:29:44 -0300 Message-Id: <20221216212944.28229-6-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221216212944.28229-1-farosas@suse.de> References: <20221216212944.28229-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1671226459552100003 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana of note, cpreg lists were previously initialized by TCG first, and then thrown away and replaced with the data coming from KVM. Now we just initialize once, either for TCG or for KVM. Signed-off-by: Claudio Fontana [moved arm_cpu_register_gdb_regs_for_features out of tcg_enabled] Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson --- We still need to tell GDB about the register sets even when running with KVM. Originally from: [RFC v14 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled https://lore.kernel.org/r/20210416162824.25131-17-cfontana@suse.de --- target/arm/cpu.c | 31 ++++++++++++---------- target/arm/kvm.c | 18 ++++++------- target/arm/kvm_arm.h | 3 +-- target/arm/machine.c | 61 ++++++++++++++++++++++++-------------------- 4 files changed, 62 insertions(+), 51 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 38d066c294..a0c77ba153 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -523,9 +523,11 @@ static void arm_cpu_reset(DeviceState *dev) } #endif =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); - arm_rebuild_hflags(env); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); + } } =20 #ifndef CONFIG_USER_ONLY @@ -1597,6 +1599,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 +#ifdef CONFIG_TCG { uint64_t scale; =20 @@ -1622,7 +1625,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, arm_gt_hvtimer_cb, cpu); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { @@ -1940,17 +1944,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - pmu_init(cpu); - - if (!kvm_enabled()) { + if (tcg_enabled()) { + pmu_init(cpu); arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); - } =20 #ifndef CONFIG_USER_ONLY - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_= cb, - cpu); + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_ti= mer_cb, + cpu); #endif + } } else { cpu->isar.id_aa64dfr0 =3D FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); @@ -2046,10 +2049,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) set_feature(env, ARM_FEATURE_VBAR); } =20 - register_cp_regs_for_features(cpu); - arm_cpu_register_gdb_regs_for_features(cpu); + if (tcg_enabled()) { + register_cp_regs_for_features(cpu); + init_cpreg_list(cpu); + } =20 - init_cpreg_list(cpu); + arm_cpu_register_gdb_regs_for_features(cpu); =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2..2f01c26f54 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -438,9 +438,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, ui= nt64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } =20 -/* Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). +/* + * Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about. + * + * The parallel for TCG is init_cpreg_list() */ int kvm_arm_init_cpreg_list(ARMCPU *cpu) { @@ -482,12 +484,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) arraylen++; } =20 - cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); - cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, arraylen); - cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, - arraylen); - cpu->cpreg_vmstate_values =3D g_renew(uint64_t, cpu->cpreg_vmstate_val= ues, - arraylen); + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); cpu->cpreg_array_len =3D arraylen; cpu->cpreg_vmstate_array_len =3D arraylen; =20 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 99017b635c..41de2a7cf1 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -70,8 +70,7 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t d= evid, uint64_t group, * @cpu: ARMCPU * * Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). + * definition of what CPU registers it knows about. * * Returns: 0 if success, else < 0 error code */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 54c5c62433..4cc4468d3e 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" @@ -687,7 +688,7 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -722,7 +723,7 @@ static int cpu_post_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_finish(&cpu->env); } =20 @@ -741,7 +742,7 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state =3D UINT32_MAX; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -811,36 +812,37 @@ static int cpu_post_load(void *opaque, int version_id) } } =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); =20 - /* - * TCG gen_update_fp_context() relies on the invariant that - * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; - * forbid bogus incoming data with some other value. - */ - if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)= ) { - if (extract32(env->v7m.fpdscr[M_REG_NS], - FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4 || - extract32(env->v7m.fpdscr[M_REG_S], - FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4) { - return -1; + /* + * TCG gen_update_fp_context() relies on the invariant that + * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extensi= on; + * forbid bogus incoming data with some other value. + */ + if (arm_feature(env, ARM_FEATURE_M) && + cpu_isar_feature(aa32_lob, cpu)) { + if (extract32(env->v7m.fpdscr[M_REG_NS], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4 = || + extract32(env->v7m.fpdscr[M_REG_S], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) !=3D 4)= { + return -1; + } } - } =20 - /* - * Misaligned thumb pc is architecturally impossible. - * We have an assert in thumb_tr_translate_insn to verify this. - * Fail an incoming migrate to avoid this assert. - */ - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { - return -1; - } + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } =20 - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); + arm_rebuild_hflags(&cpu->env); } - arm_rebuild_hflags(&cpu->env); =20 return 0; } @@ -890,8 +892,13 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), +#ifdef CONFIG_TCG VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), +#else + VMSTATE_UNUSED(sizeof(QEMUTimer *)), + VMSTATE_UNUSED(sizeof(QEMUTimer *)), +#endif /* CONFIG_TCG */ { .name =3D "power_state", .version_id =3D 0, --=20 2.35.3