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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i12-20020a05600c354c00b003cfd64b6be1sm8388787wmq.27.2022.12.15.04.50.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:50:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OyeQ4yPNj+C/vssV1sHtgciwO5ee7WuxGatE6ryMCsI=; b=junQ3quI5fbUMmuI7S5Gq+4v7cOmFduiyj4PobxrECTuYPP6FMcMjdpsEIPDl0dFPc 2nICW9KY3eWeDbB1FRlwMgdCtXUClbG/zha+T8dya/0Ov4s1450WZKFDxGk0nOHRTFoQ 8FPnit15wahNN8741lN0P6lnw7aOH+S/Pfwp39xvCT6h/HUp37x9dd8ALM0MI4TWa9nQ bklJpMMABbYFOPHhQOFQze3M9Hz6WgiRnb/F84CdhB0tN+nInO5FSbyJVMocVXfzdsnm 9eJp9wezkWRF+ZDlsbEs2z91c6YgOzGJCHsYcvIL9KpxvNoY/3EPQGHpLkmpd+4tn15L 2wWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OyeQ4yPNj+C/vssV1sHtgciwO5ee7WuxGatE6ryMCsI=; b=RXstwa0cOq5cYynl4K46xkPAPnTq4j7M80YN8yzWs4pYlXaoYH2HQGVoMmCuKyYesA iW3JlLUs6T6D/ACE2IAnVIxd9lI4eG2+Rn3ftHdj02Ua3TYuVepEXgZxFBJXDmkT4IRW jlTBSgx0Aw6um90SaTcm4GtK3xPnAUt/Dr5e+AyVoIhuE4AlnFXiM8cJHzRwhufRvm7c TQrlHBY9etH8tSOYb6Ojx82vIFd9BaDbbvy6N1Pc34iZzjr2G26ugyrJN/v4v70aMiWY F/tTucpU1PdFytGI05+Zwd10IkPiF5Z2SU9Ps7wKOMBRYdbVHbrqq9PAaeNk9SzxLBXP Ln6w== X-Gm-Message-State: ANoB5pmG8RZEfhN7TKq1/qeza2YwZsc9zawX/b8ClAhzN0UlxS2oxdKW yE2lKkSj93u/VBHCom420Te95g3pCMXv86IH X-Google-Smtp-Source: AA0mqf4k3hbY5JeH1+IT6yQk92yg39YQqtU9Rsz1ZPqAtO4+Qx4EYqjnFAnyni3ELM26vzbeVHWXfA== X-Received: by 2002:a05:600c:1c9e:b0:3d2:7a7:5cc6 with SMTP id k30-20020a05600c1c9e00b003d207a75cc6mr19796040wms.18.1671108624721; Thu, 15 Dec 2022 04:50:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps Date: Thu, 15 Dec 2022 12:49:54 +0000 Message-Id: <20221215125009.980128-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215125009.980128-1-peter.maydell@linaro.org> References: <20221215125009.980128-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1671108673404100003 Content-Type: text/plain; charset="utf-8" For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS and IC IALLUIS cache maintenance instructions. The HCR_EL2.TOCU bit traps all the other cache maintenance instructions that operate to the point of unification: AArch64 IC IVAU, IC IALLU, DC CVAU AArch32 ICIMVAU, ICIALLU, DCCMVAU The two trap bits between them cover all of the cache maintenance instructions which must also check the HCR_TPU flag. Turn the old aa64_cacheop_pou_access() function into a helper function which takes the set of HCR_EL2 flags to check as an argument, and call it from new access_ticab() and access_tocu() functions as appropriate for each cache op. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0ec1c3ffbd6..eee95a42f7f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4273,9 +4273,7 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMS= tate *env, return CP_ACCESS_OK; } =20 -static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) +static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcr= flags) { /* Cache invalidate/clean to Point of Unification... */ switch (arm_current_el(env)) { @@ -4286,8 +4284,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMS= tate *env, } /* fall through */ case 1: - /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ - if (arm_hcr_el2_eff(env) & HCR_TPU) { + /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ + if (arm_hcr_el2_eff(env) & hcrflags) { return CP_ACCESS_TRAP_EL2; } break; @@ -4295,6 +4293,18 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARM= State *env, return CP_ACCESS_OK; } =20 +static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); +} + +static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4935,15 +4945,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_ticab }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_tocu }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_tocu }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, @@ -4961,7 +4971,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, + .accessfn =3D access_tocu }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -5138,13 +5148,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D tlbiipas2is_hyp_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab = }, { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tocu }, { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tocu }, { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, @@ -5158,7 +5168,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tocu }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, --=20 2.25.1