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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1670958504; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+8FhzPg+FJF8Pm4/rHzoK9yBUqnncwNHtOeps6BM5Ps=; b=Vs7rjY81ffayIRgc/58f5vPpnUShXmHWHMFB9tt35haoiwjJ2bn5UM+F8tPuS51IIqhBCG nWQ+3M1oF/yok5Cw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost Subject: [PATCH 1/6] target/arm: Fix checkpatch comment style warnings in helper.c Date: Tue, 13 Dec 2022 16:05:32 -0300 Message-Id: <20221213190537.511-2-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221213190537.511-1-farosas@suse.de> References: <20221213190537.511-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1670958613765100003 Content-Type: text/plain; charset="utf-8" Fix these: WARNING: Block comments use a leading /* on a separate line WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck --- This is roughly a combination of the following patches from https://lore.kernel.org/r/20210416162824.25131-1-cfontana@suse.de [RFC v14 11/80] target/arm: tcg: fix comment style before move to cpu-mmu [RFC v14 13/80] target/arm: fix style in preparation of new cpregs module [RFC v14 30/80] target/arm: fixup sve_exception_el code style before move [RFC v14 32/80] target/arm: fix comments style of fp_exception_el before mo= ving it [RFC v14 36/80] target/arm: fix style of arm_cpu_do_interrupt functions bef= ore move --- target/arm/helper.c | 323 +++++++++++++++++++++++++++++--------------- 1 file changed, 215 insertions(+), 108 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d8c8223ec3..77da24b0e8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -83,7 +83,8 @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPReg= Info *ri) static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v) { - /* Raw write of a coprocessor register (as needed for migration, etc). + /* + * Raw write of a coprocessor register (as needed for migration, etc). * Note that constant registers are treated as write-ignored; the * caller should check for success by whether a readback gives the * value written. @@ -101,7 +102,8 @@ static void write_raw_cp_reg(CPUARMState *env, const AR= MCPRegInfo *ri, =20 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { - /* Return true if the regdef would cause an assertion if you called + /* + * Return true if the regdef would cause an assertion if you called * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a * program bug for it not to have the NO_RAW flag). * NB that returning false here doesn't necessarily mean that calling @@ -184,7 +186,8 @@ bool write_list_to_cpustate(ARMCPU *cpu) if (ri->type & ARM_CP_NO_RAW) { continue; } - /* Write value and confirm it reads back as written + /* + * Write value and confirm it reads back as written * (to catch read-only registers and partially read-only * registers where the incoming migration value doesn't match) */ @@ -237,7 +240,8 @@ static gint cpreg_key_compare(gconstpointer a, gconstpo= inter b) =20 void init_cpreg_list(ARMCPU *cpu) { - /* Initialise the cpreg_tuples[] array based on the cp_regs hash. + /* + * Initialise the cpreg_tuples[] array based on the cp_regs hash. * Note that we require cpreg_tuples[] to be sorted by key ID. */ GList *keys; @@ -279,7 +283,8 @@ static CPAccessResult access_el3_aa32ns(CPUARMState *en= v, return CP_ACCESS_OK; } =20 -/* Some secure-only AArch32 registers trap to EL3 if used from +/* + * Some secure-only AArch32 registers trap to EL3 if used from * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). * Note that an access from Secure EL1 can only happen if EL3 is AArch64. * We assume that the .access field is set to PL1_RW. @@ -301,7 +306,8 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState= *env, return CP_ACCESS_TRAP_UNCATEGORIZED; } =20 -/* Check for traps to performance monitor registers, which are controlled +/* + * Check for traps to performance monitor registers, which are controlled * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. */ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, @@ -375,7 +381,8 @@ static void fcse_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value) { - /* Unlike real hardware the qemu TLB uses virtual addresses, + /* + * Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ tlb_flush(CPU(cpu)); @@ -390,7 +397,8 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, =20 if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table + /* + * For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ @@ -582,7 +590,8 @@ static void tlbiipas2is_hyp_write(CPUARMState *env, con= st ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo cp_reginfo[] =3D { - /* Define the secure and non-secure FCSE identifier CP registers + /* + * Define the secure and non-secure FCSE identifier CP registers * separately because there is no secure bank in V8 (no _EL3). This a= llows * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. @@ -597,7 +606,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - /* Define the secure and non-secure context identifier CP registers + /* + * Define the secure and non-secure context identifier CP registers * separately because there is no secure bank in V8 (no _EL3). This a= llows * the secure register to be properly reset and migrated. In the * non-secure case, the 32-bit register will have reset and migration @@ -618,7 +628,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { - /* NB: Some of these registers exist in v8 but with more precise + /* + * NB: Some of these registers exist in v8 but with more precise * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). */ /* MMU Domain access control / MPU write buffer control */ @@ -628,7 +639,8 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. + /* + * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. * For v6 and v5, these mappings are overly broad. */ { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, @@ -646,7 +658,8 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { - /* Not all pre-v6 cores implemented this WFI, so this is slightly + /* + * Not all pre-v6 cores implemented this WFI, so this is slightly * over-broad. */ { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, @@ -654,12 +667,14 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { - /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which + /* + * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which * is UNPREDICTABLE; we choose to NOP as most implementations do). */ { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, .access =3D PL1_W, .type =3D ARM_CP_WFI }, - /* L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice + /* + * L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd * OMAPCP will override this space. */ @@ -673,14 +688,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D 0 }, - /* We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; + /* + * We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; * implementing it as RAZ means the "debug architecture version" bits * will read as a reserved value, which should cause Linux to not try * to use the debug hardware. */ { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MMU TLB control. Note that the wildcarding means we cover not just + /* + * MMU TLB control. Note that the wildcarding means we cover not just * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. */ { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, @@ -708,7 +725,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, =20 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ if (!arm_feature(env, ARM_FEATURE_V8)) { - /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. + /* + * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ @@ -724,7 +742,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, value |=3D R_CPACR_ASEDIS_MASK; } =20 - /* VFPv3 and upwards with NEON implement 32 double precision + /* + * VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { @@ -766,7 +785,8 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMC= PRegInfo *ri) =20 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - /* Call cpacr_write() so that we reset with the correct RAO bits set + /* + * Call cpacr_write() so that we reset with the correct RAO bits set * for our CPU features. */ cpacr_write(env, ri, 0); @@ -807,7 +827,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "MVA_prefetch", .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* We need to break the TB after ISB to execute self-modifying code + /* + * We need to break the TB after ISB to execute self-modifying code * correctly and also to take any pending interrupts immediately. * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. */ @@ -822,7 +843,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue =3D 0, }, - /* Watchpoint Fault Address Register : should actually only be present + /* + * Watchpoint Fault Address Register : should actually only be present * for 1136, 1176, 11MPCore. */ { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, @@ -1027,7 +1049,8 @@ static bool event_supported(uint16_t number) static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { - /* Performance monitor registers user accessibility is controlled + /* + * Performance monitor registers user accessibility is controlled * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable * trapping to EL2 or EL3 for other accesses. */ @@ -1115,7 +1138,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) =20 -/* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing +/* + * Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing * the current EL, security state, and register configuration. */ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) @@ -1479,7 +1503,8 @@ static uint64_t pmccntr_read(CPUARMState *env, const = ARMCPRegInfo *ri) static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and + /* + * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are * accessed. @@ -1590,7 +1615,8 @@ static void pmevtyper_write(CPUARMState *env, const A= RMCPRegInfo *ri, env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; pmevcntr_op_finish(env, counter); } - /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when + /* + * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when * PMSELR value is equal to or greater than the number of implemented * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. */ @@ -1691,8 +1717,10 @@ static uint64_t pmevcntr_read(CPUARMState *env, cons= t ARMCPRegInfo *ri, } return ret; } else { - /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR - * are CONSTRAINED UNPREDICTABLE. */ + /* + * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. + */ return 0; } } @@ -1767,7 +1795,8 @@ static void pmintenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Note that even though the AArch64 view of this register has bits + /* + * Note that even though the AArch64 view of this register has bits * [10:0] all RES0 we can only mask the bottom 5, to comply with the * architectural requirements for bits which are RES0 only in some * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 @@ -1830,7 +1859,8 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (!arm_feature(env, ARM_FEATURE_EL2)) { valid_mask &=3D ~SCR_HCE; =20 - /* On ARMv7, SMD (or SCD as it is called in v7) is only + /* + * On ARMv7, SMD (or SCD as it is called in v7) is only * supported if EL2 exists. The bit is UNK/SBZP when * EL2 is unavailable. In QEMU ARMv7, we force it to always zero * when EL2 is unavailable. @@ -1886,7 +1916,8 @@ static uint64_t ccsidr_read(CPUARMState *env, const A= RMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 - /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + /* + * Acquire the CSSELR index from the bank corresponding to the CCSIDR * bank */ uint32_t index =3D A32_BANKED_REG_GET(env, csselr, @@ -1961,7 +1992,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* Performance monitors are implementation defined in v7, + /* + * Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we * follow. * @@ -2115,7 +2147,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D csselr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), offsetof(CPUARMState, cp15.csselr_ns) } }, - /* Auxiliary ID register: this actually has an IMPDEF value but for now + /* + * Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */ { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, @@ -2123,7 +2156,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid1, .resetvalue =3D 0 }, - /* Auxiliary fault status registers: these also are IMPDEF, and we + /* + * Auxiliary fault status registers: these also are IMPDEF, and we * choose to RAZ/WI for all cores. */ { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -2134,7 +2168,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MAIR can just read-as-written because we don't implement caches + /* + * MAIR can just read-as-written because we don't implement caches * and so don't need to care about memory attributes. */ { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -2146,10 +2181,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), .resetvalue =3D 0 }, - /* For non-long-descriptor page tables these are PRRR and NMRR; + /* + * For non-long-descriptor page tables these are PRRR and NMRR; * regardless they still act as reads-as-written for QEMU. */ - /* MAIR0/1 are defined separately from their 64-bit counterpart which + /* + * MAIR0/1 are defined separately from their 64-bit counterpart which * allows them to assign the correct fieldoffset based on the endiann= ess * handled in the field definitions. */ @@ -2312,7 +2349,8 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { - /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. + /* + * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. * Writable only at the highest implemented exception level. */ int el =3D arm_current_el(env); @@ -2471,7 +2509,8 @@ static CPAccessResult gt_stimer_access(CPUARMState *e= nv, const ARMCPRegInfo *ri, bool isread) { - /* The AArch64 register view of the secure physical timer is + /* + * The AArch64 register view of the secure physical timer is * always accessible from EL3, and configurably accessible from * Secure EL1. */ @@ -2506,7 +2545,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; =20 if (gt->ctl & 1) { - /* Timer enabled: calculate and set current ISTATUS, irq, and + /* + * Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? @@ -2529,7 +2569,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) /* Next transition is when we hit cval */ nexttick =3D gt->cval + offset; } - /* Note that the desired next expiry time might be beyond the + /* + * Note that the desired next expiry time might be beyond the * signed-64-bit range of a QEMUTimer -- in this case we just * set the timer for as far in the future as possible. When the * timer expires we will reset the timer for any remaining period. @@ -2646,7 +2687,8 @@ static void gt_ctl_write(CPUARMState *env, const ARMC= PRegInfo *ri, /* Enable toggled */ gt_recalc_timer(cpu, timeridx); } else if ((oldval ^ value) & 2) { - /* IMASK toggled: don't need to recalculate, + /* + * IMASK toggled: don't need to recalculate, * just set the interrupt line based on ISTATUS */ int irqstate =3D (oldval & 4) && !(value & 2); @@ -2957,7 +2999,8 @@ static void arm_gt_cntfrq_reset(CPUARMState *env, con= st ARMCPRegInfo *opaque) } =20 static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - /* Note that CNTFRQ is purely reads-as-written for the benefit + /* + * Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. * Our reset value matches the fixed frequency we implement the timer = at. */ @@ -3120,7 +3163,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, - /* Secure timer -- this is actually restricted to only EL3 + /* + * Secure timer -- this is actually restricted to only EL3 * and configurably Secure-EL1 via the accessfn. */ { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3159,7 +3203,8 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #else =20 -/* In user-mode most of the generic timer registers are inaccessible +/* + * In user-mode most of the generic timer registers are inaccessible * however modern kernels (4.12+) allow access to cntvct_el0 */ =20 @@ -3167,7 +3212,8 @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 - /* Currently we have no support for QEMUTimer in linux-user so we + /* + * Currently we have no support for QEMUTimer in linux-user so we * can't call gt_get_countervalue(env), instead we directly * call the lower level functions. */ @@ -3208,7 +3254,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, bool isread) { if (ri->opc2 & 4) { - /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in + /* + * The ATS12NSO* operations must trap to EL3 or EL2 if executed in * Secure EL1 (which can only happen if EL3 is AArch64). * They are simply UNDEF if executed from NS EL1. * They function normally from EL2 or EL3. @@ -3369,7 +3416,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, } } } else { - /* fsr is a DFSR/IFSR value for the short descriptor + /* + * fsr is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). * Convert it to a 32-bit PAR. */ @@ -3658,7 +3706,8 @@ static void pmsav7_rgnr_write(CPUARMState *env, const= ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { - /* Reset for all these registers is handled in arm_cpu_reset(), + /* + * Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do * not register cpregs but still need the state to be reset. */ @@ -3759,7 +3808,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, } =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID + /* + * With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); @@ -3876,7 +3926,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, }; =20 -/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing +/* + * Note that unlike TTBCR, writing to TTBCR2 does not require flushing * qemu tlbs nor adjusting cached masks. */ static const ARMCPRegInfo ttbcr2_reginfo =3D { @@ -3914,7 +3965,8 @@ static void omap_wfi_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* On OMAP there are registers indicating the max/min index of dcache = lines + /* + * On OMAP there are registers indicating the max/min index of dcache = lines * containing a dirty line; cache flush operations have to reset these. */ env->cp15.c15_i_max =3D 0x000; @@ -3946,7 +3998,8 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, - /* TODO: Peripheral port remap register: + /* + * TODO: Peripheral port remap register: * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), * when MMU is off. @@ -3975,7 +4028,8 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), .resetvalue =3D 0, }, - /* XScale specific cache-lockdown: since we have no cache we NOP these + /* + * XScale specific cache-lockdown: since we have no cache we NOP these * and hope the guest does not really rely on cache behaviour. */ { .name =3D "XSCALE_LOCK_ICACHE_LINE", @@ -3993,7 +4047,8 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { - /* RAZ/WI the whole crn=3D15 space, when we don't have a more specific + /* + * RAZ/WI the whole crn=3D15 space, when we don't have a more specific * implementation of this implementation-defined space. * Ideally this should eventually disappear in favour of actually * implementing the correct behaviour for all cores. @@ -4033,7 +4088,8 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[= ] =3D { }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { - /* The cache test-and-clean instructions always return (1 << 30) + /* + * The cache test-and-clean instructions always return (1 << 30) * to indicate that there are no dirty cache lines. */ { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, @@ -4069,7 +4125,8 @@ static uint64_t mpidr_read_val(CPUARMState *env) =20 if (arm_feature(env, ARM_FEATURE_V7MP)) { mpidr |=3D (1U << 31); - /* Cores which are uniprocessor (non-coherent) + /* + * Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set * bit 30. (For instance, Cortex-R5). */ @@ -4271,7 +4328,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMS= tate *env, return CP_ACCESS_OK; } =20 -/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions +/* + * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ =20 @@ -4404,7 +4462,8 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL2 + /* + * Invalidate by VA, EL2 * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ @@ -4418,7 +4477,8 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL3 + /* + * Invalidate by VA, EL3 * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ @@ -4443,7 +4503,8 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL1&0 (AArch64 version). + /* + * Invalidate by VA, EL1&0 (AArch64 version). * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. @@ -4764,7 +4825,8 @@ static CPAccessResult sp_el0_access(CPUARMState *env,= const ARMCPRegInfo *ri, bool isread) { if (!(env->pstate & PSTATE_SP)) { - /* Access to SP_EL0 is undefined if it's being used as + /* + * Access to SP_EL0 is undefined if it's being used as * the stack pointer. */ return CP_ACCESS_TRAP_UNCATEGORIZED; @@ -4804,7 +4866,8 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } =20 if (raw_read(env, ri) =3D=3D value) { - /* Skip the TLB flush if nothing actually changed; Linux likes + /* + * Skip the TLB flush if nothing actually changed; Linux likes * to do a lot of pointless SCTLR writes. */ return; @@ -4872,7 +4935,8 @@ static void mdcr_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, } =20 static const ARMCPRegInfo v8_cp_reginfo[] =3D { - /* Minimal set of EL0-visible registers. This will need to be expanded + /* + * Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. */ { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, @@ -5155,7 +5219,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, - /* We rely on the access checks not allowing the guest to write to the + /* + * We rely on the access checks not allowing the guest to write to the * state field when SPSel indicates that it's being used as the stack * pointer. */ @@ -5233,7 +5298,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; } else if (cpu->psci_conduit !=3D QEMU_PSCI_CONDUIT_SMC) { - /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. + /* + * Architecturally HCR.TSC is RES0 if EL3 is not implemented. * However, if we're using the SMC PSCI conduit then QEMU is * effectively acting like EL3 firmware and so the guest at * EL2 should retain the ability to prevent EL1 from being @@ -5657,7 +5723,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY - /* Unlike the other EL2-related AT operations, these must + /* + * Unlike the other EL2-related AT operations, these must * UNDEF from EL3 if EL2 is not implemented, which is why we * define them here rather than with the rest of the AT ops. */ @@ -5671,7 +5738,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_W, .accessfn =3D at_s1e2_access, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, .writefn =3D ats_write64 }, - /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + /* + * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se * to behave as if SCR.NS was 1. @@ -5684,7 +5752,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the + /* + * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the * reset values as IMPDEF. We choose to reset to 3 to comply with * both ARMv7 and ARMv8. */ @@ -5767,7 +5836,8 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { - /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. + /* + * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. * At Secure EL1 it traps to EL3 or EL2. */ if (arm_current_el(env) =3D=3D 3) { @@ -6571,7 +6641,8 @@ static void define_pmu_regs(ARMCPU *cpu) } } =20 -/* We don't know until after realize whether there's a GICv3 +/* + * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 * at runtime. @@ -6600,7 +6671,8 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) } #endif =20 -/* Shared logic between LORID and the rest of the LOR* registers. +/* + * Shared logic between LORID and the rest of the LOR* registers. * Secure state exclusion has already been dealt with. */ static CPAccessResult access_lor_ns(CPUARMState *env, @@ -7427,7 +7499,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 define_arm_cp_regs(cpu, cp_reginfo); if (!arm_feature(env, ARM_FEATURE_V8)) { - /* Must go early as it is full of wildcards that may be + /* + * Must go early as it is full of wildcards that may be * overridden by later definitions. */ define_arm_cp_regs(cpu, not_v8_cp_reginfo); @@ -7441,7 +7514,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_pfr0 }, - /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know + /* + * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. */ { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, @@ -7975,7 +8049,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 define_arm_cp_regs(cpu, el3_regs); } - /* The behaviour of NSACR is sufficiently various that we don't + /* + * The behaviour of NSACR is sufficiently various that we don't * try to describe it in a single reginfo: * if EL3 is 64 bit, then trap to EL3 from S EL1, * reads as constant 0xc00 from NS EL1 and NS EL2 @@ -8067,13 +8142,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } - /* Slightly awkwardly, the OMAP and StrongARM cores need all of + /* + * Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld * be read-only (ie write causes UNDEF exception). */ { ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { - /* Pre-v8 MIDR space. + /* + * Pre-v8 MIDR space. * Note that the MIDR isn't a simple constant register because * of the TI925 behaviour where writes to another register can * cause the MIDR value to change. @@ -8173,7 +8250,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { size_t i; - /* Register the blanket "writes ignored" value first to cover = the + /* + * Register the blanket "writes ignored" value first to cover = the * whole space. Then update the specific ID registers to allow= write * access, so that they ignore writes rather than causing them= to * UNDEF. @@ -8310,7 +8388,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .raw_writefn =3D raw_write, }; if (arm_feature(env, ARM_FEATURE_XSCALE)) { - /* Normally we would always end the TB on an SCTLR write, but = Linux + /* + * Normally we would always end the TB on an SCTLR write, but = Linux * arch/arm/mach-pxa/sleep.S expects two instructions following * an MMU enable to execute from cache. Imitate this behaviou= r. */ @@ -8705,7 +8784,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque) { - /* Define implementations of coprocessor registers. + /* + * Define implementations of coprocessor registers. * We store these in a hashtable because typically * there are less than 150 registers in a space which * is 16*16*16*8*8 =3D 262144 in size. @@ -8772,7 +8852,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, default: g_assert_not_reached(); } - /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 + /* + * The AArch64 pseudocode CheckSystemAccess() specifies that op1 * encodes a minimum access level for the register. We roll this * runtime check into our general permission check code, so check * here that the reginfo's specified permissions are strict enough @@ -8814,7 +8895,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, assert((r->access & ~mask) =3D=3D 0); } =20 - /* Check that the register definition has enough info to handle + /* + * Check that the register definition has enough info to handle * reads and writes if they are permitted. */ if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { @@ -8839,7 +8921,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, continue; } if (state =3D=3D ARM_CP_STATE_AA32) { - /* Under AArch32 CP registers can be common + /* + * Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ char *name; @@ -8865,8 +8948,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, g_assert_not_reached(); } } else { - /* AArch64 registers get mapped to non-secure inst= ance - * of AArch32 */ + /* + * AArch64 registers get mapped to non-secure inst= ance + * of AArch32 + */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); @@ -8952,7 +9037,8 @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMC= PRegInfo *opaque) =20 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) { - /* Return true if it is not valid for us to switch to + /* + * Return true if it is not valid for us to switch to * this CPU mode (ie all the UNPREDICTABLE cases in * the ARM ARM CPSRWriteByInstr pseudocode). */ @@ -8973,10 +9059,12 @@ static int bad_mode_switch(CPUARMState *env, int mo= de, CPSRWriteType write_type) case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: case ARM_CPU_MODE_FIQ: - /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + /* + * Note that we don't implement the IMPDEF NSACR.RFR which in v7 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) */ - /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR + /* + * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR * and CPS are treated as illegal mode changes. */ if (write_type =3D=3D CPSRWriteByInstr && @@ -9034,7 +9122,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, env->GE =3D (val >> 16) & 0xf; } =20 - /* In a V7 implementation that includes the security extensions but do= es + /* + * In a V7 implementation that includes the security extensions but do= es * not include Virtualization Extensions the SCR.FW and SCR.AW bits co= ntrol * whether non-secure software is allowed to change the CPSR_F and CPS= R_A * bits respectively. @@ -9050,7 +9139,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, changed_daif =3D (env->daif ^ val) & mask; =20 if (changed_daif & CPSR_A) { - /* Check to see if we are allowed to change the masking of asy= nc + /* + * Check to see if we are allowed to change the masking of asy= nc * abort exceptions from a non-secure state. */ if (!(env->cp15.scr_el3 & SCR_AW)) { @@ -9062,7 +9152,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, } =20 if (changed_daif & CPSR_F) { - /* Check to see if we are allowed to change the masking of FIQ + /* + * Check to see if we are allowed to change the masking of FIQ * exceptions from a non-secure state. */ if (!(env->cp15.scr_el3 & SCR_FW)) { @@ -9072,7 +9163,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, mask &=3D ~CPSR_F; } =20 - /* Check whether non-maskable FIQ (NMFI) support is enabled. + /* + * Check whether non-maskable FIQ (NMFI) support is enabled. * If this bit is set software is not allowed to mask * FIQs, but is allowed to set CPSR_F to 0. */ @@ -9092,7 +9184,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, if (write_type !=3D CPSRWriteRaw && ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR) { - /* Note that we can only get here in USR mode if this is a + /* + * Note that we can only get here in USR mode if this is a * gdb stub write; for this case we follow the architectural * behaviour for guest writes in USR mode of ignoring an attem= pt * to switch mode. (Those are caught by translate.c for writes @@ -9100,7 +9193,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, */ mask &=3D ~CPSR_M; } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { - /* Attempt to switch to an invalid mode: this is UNPREDICTABLE= in + /* + * Attempt to switch to an invalid mode: this is UNPREDICTABLE= in * v7, and has defined behaviour in v8: * + leave CPSR.M untouched * + allow changes to the other CPSR fields @@ -9243,7 +9337,8 @@ static void switch_mode(CPUARMState *env, int mode) env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; } =20 -/* Physical Interrupt Target EL Lookup Table +/* + * Physical Interrupt Target EL Lookup Table * * [ From ARM ARM section G1.13.4 (Table G1-15) ] * @@ -9317,7 +9412,8 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32= _t excp_idx, if (arm_feature(env, ARM_FEATURE_EL3)) { rw =3D ((env->cp15.scr_el3 & SCR_RW) =3D=3D SCR_RW); } else { - /* Either EL2 is the highest EL (and so the EL2 register width + /* + * Either EL2 is the highest EL (and so the EL2 register width * is given by is64); or there is no EL2 or EL3, in which case * the value of 'rw' does not affect the table lookup anyway. */ @@ -9592,7 +9688,8 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; } =20 - /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ * mode, then we can copy to r8-r14. Otherwise, we copy to the * FIQ bank for r8-r14. */ @@ -9938,7 +10035,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) /* High vectors. When enabled, base address cannot be remapped. */ addr +=3D 0xffff0000; } else { - /* ARM v7 architectures provide a vector base address register to = remap + /* + * ARM v7 architectures provide a vector base address register to = remap * the interrupt vector table. * This register is only followed in non-monitor mode, and is bank= ed. * Note: only bits 31:5 are valid. @@ -10072,7 +10170,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { - /* Entry vector offset depends on whether the implemented EL + /* + * Entry vector offset depends on whether the implemented EL * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; @@ -10273,7 +10372,8 @@ static void handle_semihosting(CPUState *cs) } #endif =20 -/* Handle a CPU exception for A and R profile CPUs. +/* + * Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. @@ -10318,7 +10418,8 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif =20 - /* Hooks may change global state so BQL should be held, also the + /* + * Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of * cs->interrupt_request. */ @@ -10599,9 +10700,11 @@ ARMVAParameters aa64_va_parameters(CPUARMState *en= v, uint64_t va, }; } =20 -/* Note that signed overflow is undefined in C. The following routines are - careful to use unsigned types where modulo arithmetic is required. - Failure to do so _will_ break on newer gcc. */ +/* + * Note that signed overflow is undefined in C. The following routines are + * careful to use unsigned types where modulo arithmetic is required. + * Failure to do so _will_ break on newer gcc. + */ =20 /* Signed saturating arithmetic. */ =20 @@ -10843,7 +10946,8 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t= a, uint32_t b) return (a & mask) | (b & ~mask); } =20 -/* CRC helpers. +/* + * CRC helpers. * The upper bytes of val (above the number specified by 'bytes') must have * been zeroed out by the caller. */ @@ -10867,7 +10971,8 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Return the exception level to which FP-disabled exceptions should +/* + * Return the exception level to which FP-disabled exceptions should * be taken, or 0 if FP is enabled. */ int fp_exception_el(CPUARMState *env, int cur_el) @@ -10875,7 +10980,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) #ifndef CONFIG_USER_ONLY uint64_t hcr_el2; =20 - /* CPACR and the CPTR registers don't exist before v6, so FP is + /* + * CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ if (!arm_feature(env, ARM_FEATURE_V6)) { @@ -10900,7 +11006,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) =20 hcr_el2 =3D arm_hcr_el2_eff(env); =20 - /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: + /* + * The CPACR controls traps to EL1, or PL1 if we're 32 bit: * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses --=20 2.35.3 From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1670958603; cv=none; d=zohomail.com; s=zohoarc; b=DS7iqGEEm60nBJh6/10jqtcSMTvXOGs31P3SGqmx+GmORnii/SONwmaxEDz4YkL9NUxtOh/2BcNwmfsz4LLrbWRNqSAlppETrxPSywosNb3iZXtIGVw1HCCN+sutryxrenvKW7DQTxEx7kjFl6Di0b+M/zoY54If3hfxhl/jVXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670958603; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1c; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1670958603546100001 Content-Type: text/plain; charset="utf-8" Fix the following: ERROR: spaces required around that '|' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '+' (ctx:VxB) ERROR: space prohibited between function name and open parenthesis '(' (the last two still have some occurrences in macros which I left behind because it might impact readability) Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck --- target/arm/helper.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 77da24b0e8..b240dcf12f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -205,7 +205,7 @@ static void add_cpreg_to_list(gpointer key, gpointer op= aque) uint32_t regidx =3D (uintptr_t)key; const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); /* The value array need not be initialized at this point */ cpu->cpreg_array_len++; @@ -219,7 +219,7 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 ri =3D g_hash_table_lookup(cpu->cp_regs, key); =20 - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_array_len++; } } @@ -2325,11 +2325,11 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, - .access =3D PL0_R|PL1_W, + .access =3D PL0_R | PL1_W, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), .resetvalue =3D 0}, { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, - .access =3D PL0_R|PL1_W, + .access =3D PL0_R | PL1_W, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, .resetfn =3D arm_cp_reset_ignore }, @@ -4074,17 +4074,17 @@ static const ARMCPRegInfo cache_block_ops_cp_reginf= o[] =3D { .resetvalue =3D 0 }, /* The cache ops themselves: these all NOP for QEMU */ { .name =3D "IICR", .cp =3D 15, .crm =3D 5, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "IDCR", .cp =3D 15, .crm =3D 6, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "CDCR", .cp =3D 15, .crm =3D 12, .opc1 =3D 0, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL0_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "PIR", .cp =3D 15, .crm =3D 12, .opc1 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL0_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "PDR", .cp =3D 15, .crm =3D 12, .opc1 =3D 2, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL0_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_64BIT }, }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { @@ -8351,7 +8351,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo cbar =3D { .name =3D "CBAR", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, - .access =3D PL1_R|PL3_W, .resetvalue =3D cpu->reset_cbar, + .access =3D PL1_R | PL3_W, .resetvalue =3D cpu->reset_cbar, .fieldoffset =3D offsetof(CPUARMState, cp15.c15_config_base_address) }; @@ -9318,11 +9318,11 @@ static void switch_mode(CPUARMState *env, int mode) return; =20 if (old_mode =3D=3D ARM_CPU_MODE_FIQ) { - memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); - memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); + memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); + memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); } else if (mode =3D=3D ARM_CPU_MODE_FIQ) { - memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); - memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); + memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); + memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); } =20 i =3D bank_number(old_mode); @@ -10826,7 +10826,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 16); \ if (sum >=3D 0) \ ge |=3D 3 << (n * 2); \ - } while(0) + } while (0) =20 #define SARITH8(a, b, n, op) do { \ int32_t sum; \ @@ -10834,7 +10834,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 8); \ if (sum >=3D 0) \ ge |=3D 1 << n; \ - } while(0) + } while (0) =20 =20 #define ADD16(a, b, n) SARITH16(a, b, n, +) @@ -10853,7 +10853,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 16); \ if ((sum >> 16) =3D=3D 1) \ ge |=3D 3 << (n * 2); \ - } while(0) + } while (0) =20 #define ADD8(a, b, n) do { \ uint32_t sum; \ @@ -10861,7 +10861,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 8); \ if ((sum >> 8) =3D=3D 1) \ ge |=3D 1 << n; \ - } while(0) + } while (0) =20 #define SUB16(a, b, n) do { \ uint32_t sum; \ @@ -10869,7 +10869,7 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t = b) RESULT(sum, n, 16); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1670958569522100003 Content-Type: text/plain; charset="utf-8" Fix this: ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck --- target/arm/helper.c | 67 ++++++++++++++++++++++++++++----------------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b240dcf12f..3cf978bb93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9106,10 +9106,12 @@ void cpsr_write(CPUARMState *env, uint32_t val, uin= t32_t mask, env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; } - if (mask & CPSR_Q) + if (mask & CPSR_Q) { env->QF =3D ((val & CPSR_Q) !=3D 0); - if (mask & CPSR_T) + } + if (mask & CPSR_T) { env->thumb =3D ((val & CPSR_T) !=3D 0); + } if (mask & CPSR_IT_0_1) { env->condexec_bits &=3D ~3; env->condexec_bits |=3D (val >> 25) & 3; @@ -9314,8 +9316,9 @@ static void switch_mode(CPUARMState *env, int mode) int i; =20 old_mode =3D env->uncached_cpsr & CPSR_M; - if (mode =3D=3D old_mode) + if (mode =3D=3D old_mode) { return; + } =20 if (old_mode =3D=3D ARM_CPU_MODE_FIQ) { memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); @@ -9921,10 +9924,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *= cs) new_mode =3D ARM_CPU_MODE_UND; addr =3D 0x04; mask =3D CPSR_I; - if (env->thumb) + if (env->thumb) { offset =3D 2; - else + } else { offset =3D 4; + } break; case EXCP_SWI: new_mode =3D ARM_CPU_MODE_SVC; @@ -10715,10 +10719,11 @@ static inline uint16_t add16_sat(uint16_t a, uint= 16_t b) =20 res =3D a + b; if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { - if (a & 0x8000) + if (a & 0x8000) { res =3D 0x8000; - else + } else { res =3D 0x7fff; + } } return res; } @@ -10730,10 +10735,11 @@ static inline uint8_t add8_sat(uint8_t a, uint8_t= b) =20 res =3D a + b; if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { - if (a & 0x80) + if (a & 0x80) { res =3D 0x80; - else + } else { res =3D 0x7f; + } } return res; } @@ -10745,10 +10751,11 @@ static inline uint16_t sub16_sat(uint16_t a, uint= 16_t b) =20 res =3D a - b; if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { - if (a & 0x8000) + if (a & 0x8000) { res =3D 0x8000; - else + } else { res =3D 0x7fff; + } } return res; } @@ -10760,10 +10767,11 @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t= b) =20 res =3D a - b; if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { - if (a & 0x80) + if (a & 0x80) { res =3D 0x80; - else + } else { res =3D 0x7f; + } } return res; } @@ -10781,34 +10789,38 @@ static inline uint16_t add16_usat(uint16_t a, uin= t16_t b) { uint16_t res; res =3D a + b; - if (res < a) + if (res < a) { res =3D 0xffff; + } return res; } =20 static inline uint16_t sub16_usat(uint16_t a, uint16_t b) { - if (a > b) + if (a > b) { return a - b; - else + } else { return 0; + } } =20 static inline uint8_t add8_usat(uint8_t a, uint8_t b) { uint8_t res; res =3D a + b; - if (res < a) + if (res < a) { res =3D 0xff; + } return res; } =20 static inline uint8_t sub8_usat(uint8_t a, uint8_t b) { - if (a > b) + if (a > b) { return a - b; - else + } else { return 0; + } } =20 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); @@ -10912,10 +10924,11 @@ static inline uint8_t sub8_usat(uint8_t a, uint8_= t b) =20 static inline uint8_t do_usad(uint8_t a, uint8_t b) { - if (a > b) + if (a > b) { return a - b; - else + } else { return b - a; + } } =20 /* Unsigned sum of absolute byte differences. */ @@ -10935,14 +10948,18 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32= _t a, uint32_t b) uint32_t mask; =20 mask =3D 0; - if (flags & 1) + if (flags & 1) { mask |=3D 0xff; - if (flags & 2) + } + if (flags & 2) { mask |=3D 0xff00; - if (flags & 4) + } + if (flags & 4) { mask |=3D 0xff0000; - if (flags & 8) + } + if (flags & 8) { mask |=3D 0xff000000; + } return (a & mask) | (b & ~mask); } =20 --=20 2.35.3 From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=suse.de ARC-Seal: i=1; a=rsa-sha256; t=1670958623; cv=none; d=zohomail.com; s=zohoarc; b=n27qD4zovdMxeYXwenrqim5lupkgWRMUPjOWtr9VcN7jNlNskImN1AdxbwekLcdumeBOxYKEaiaa0uAdN8wvBURxpCMGDAbsFQsOq1I5CAxF4QbmeeC8gwXWwq/eYJOA3MBDelf4p/W8mBMh5GHA5vFIj5OQSLqUP2f72obiSXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670958623; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aVAE2JUy6EcxWtpDuGqmi0x4GKXnpAsfErWxU7vEXJ0=; b=C9S4Wnkq6doBK6/cQY7WWzypTdXYXDBGccyYQ2o64P7fvMXO4UP+1kVs60e9JfdetJSg3f1R3U+zLg+EzDPUUXCL8P3/NouzLZFJKqMxa7Vjs9I6SheJoVR6af/dkADZgb/+/EtLVX8IDQQc03KLzrlYZVJtyai7ucVd6wWFd7M= ARC-Authentication-Results: i=1; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1670958514; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aVAE2JUy6EcxWtpDuGqmi0x4GKXnpAsfErWxU7vEXJ0=; b=+q5kgEO+vrsJfN6MnnLCejBz02JY8nCuEYkIS9Zo3JEwn8maplt9HSVIn6Mhd95j/ndtQ2 EEkCQ9JUu5DiUsDw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost Subject: [PATCH 4/6] target/arm: Remove unused includes from m_helper.c Date: Tue, 13 Dec 2022 16:05:35 -0300 Message-Id: <20221213190537.511-5-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221213190537.511-1-farosas@suse.de> References: <20221213190537.511-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1670958623618100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck --- This was extracted from the following patch in the series https://lore.kernel.org/r/20210416162824.25131-1-cfontana@suse.de [RFC v14 08/80] target/arm: tcg: split m_helper user-only and sysemu-only parts --- target/arm/m_helper.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 355cd4d60a..033a4d9261 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -7,30 +7,14 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" -#include "target/arm/idau.h" -#include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" -#include "qemu/crc32c.h" -#include "qemu/qemu-print.h" #include "qemu/log.h" #include "exec/exec-all.h" -#include /* For crc32 */ -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" -#include "sysemu/kvm.h" -#include "qemu/range.h" -#include "qapi/qapi-commands-machine-target.h" -#include "qapi/error.h" -#include "qemu/guest-random.h" #ifdef CONFIG_TCG -#include "arm_ldst.h" #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif --=20 2.35.3 From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1670958517; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=H6/ZaorSex3TZvFckQlmMo2I6cmRd34OrBEGNHWWxIY=; b=/o+lec2cUtpPlhtbHTC9vSlk04SuxeD1/p2KVx/WN1jgZXzvPY7jTgrGawzn+lqPSTUWUT XfxMIBhaVuBQRtBA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost Subject: [PATCH 5/6] target/arm: Remove unused includes from helper.c Date: Tue, 13 Dec 2022 16:05:36 -0300 Message-Id: <20221213190537.511-6-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221213190537.511-1-farosas@suse.de> References: <20221213190537.511-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:67c:2178:6::1d; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1670958577363100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck --- This was extracted from the following patch in the series https://lore.kernel.org/r/20210416162824.25131-1-cfontana@suse.de [RFC v14 37/80] target/arm: move exception code out of tcg/helper.c --- target/arm/helper.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3cf978bb93..7baa94e42b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7,13 +7,11 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" #include "qemu/log.h" #include "trace.h" #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" #include "qemu/main-loop.h" #include "qemu/timer.h" #include "qemu/bitops.h" @@ -22,17 +20,12 @@ #include "exec/exec-all.h" #include /* For crc32 */ #include "hw/irq.h" -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/kvm.h" -#include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" #include "qemu/guest-random.h" #ifdef CONFIG_TCG -#include "arm_ldst.h" -#include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif #include "cpregs.h" --=20 2.35.3 From nobody Sun May 19 16:27:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1670958520; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wRXZFTKL9nLSzPS9nIZA64DhKhT1iA29WEygE2gGquk=; b=o4JPFhvfEs3IRxko/uVzsRgMk3H4vMueku7d3RSmzG/TGUyJSMwbJYcGWEvR9J7xaIfPMT VqC5g/+Ns2SLTIAw== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost Subject: [PATCH 6/6] target/arm: cleanup cpu includes Date: Tue, 13 Dec 2022 16:05:37 -0300 Message-Id: <20221213190537.511-7-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221213190537.511-1-farosas@suse.de> References: <20221213190537.511-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.29; envelope-from=farosas@suse.de; helo=smtp-out2.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1670958796431100003 Content-Type: text/plain; charset="utf-8" From: Claudio Fontana Remove some unused headers. Signed-off-by: Claudio Fontana Acked-by: Richard Henderson [added back some includes that are still needed at this point] Signed-off-by: Fabiano Rosas Reviewed-by: Claudio Fontana Reviewed-by: Cornelia Huck --- Originally from https://lore.kernel.org/r/20210416162824.25131-1-cfontana@s= use.de [RFC v14 46/80] target/arm: cleanup cpu includes --- target/arm/cpu.c | 1 - target/arm/cpu64.c | 6 ------ 2 files changed, 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 38d066c294..2e59d16529 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -26,7 +26,6 @@ #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" -#include "qapi/visitor.h" #include "cpu.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3d74f134f5..fe231f3d7d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,13 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" -#ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" -#endif /* CONFIG_TCG */ #include "qemu/module.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#endif #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "kvm_arm.h" --=20 2.35.3