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bh=zvr7qteM6KPWgU+0yfMSh31RnTlgr9tnlKItVVdHqj0=; b=Vz3dzyfpTIbuvycmfznd4kRmDzCrmJfEaktI3hlsfK+4YmRvdkwXo/B90QYK0yV7ZFG0gl jSAeHH9e55k4s6R+IbCC1aQktoweHGxsrUkZk3PEEJKNBguNNB7lqGdOmE5frVIw8Qipr7 NMm7+Aa8Y+h1M9hfEnTZpUNHW1EGFPM= X-MC-Unique: hT43HFBwPwibPJP3gicswg-1 From: Markus Armbruster To: qemu-devel@nongnu.org Cc: clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH 1/4] include/hw/ppc: Split pnv_chip.h off pnv.h Date: Sat, 10 Dec 2022 12:21:37 +0100 Message-Id: <20221210112140.4057731-2-armbru@redhat.com> In-Reply-To: <20221210112140.4057731-1-armbru@redhat.com> References: <20221210112140.4057731-1-armbru@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1670671366502100003 Content-Type: text/plain; charset="utf-8" PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined in pnv.h. Many users of the header don't actually need them. One instance is this inclusion loop: hw/ppc/pnv_homer.h includes hw/ppc/pnv.h for typedef PnvChip, and vice versa for struct PnvHomer. Similar structs live in their own headers: PnvHomerClass and PnvHomer in pnv_homer.h, PnvLpcClass and PnvLpcController in pci_lpc.h, PnvPsiClass, PnvPsi, Pnv8Psi, Pnv9Psi, Pnv10Psi in pnv_psi.h, ... Move PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip to new pnv_chip.h, and adjust include directives. This breaks the inclusion loop mentioned above. Signed-off-by: Markus Armbruster Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Daniel Henrique Barboza --- include/hw/ppc/pnv.h | 143 +----------------------------------- include/hw/ppc/pnv_chip.h | 147 +++++++++++++++++++++++++++++++++++++ hw/intc/pnv_xive.c | 1 + hw/intc/pnv_xive2.c | 1 + hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb4_pec.c | 1 + hw/ppc/pnv.c | 3 + hw/ppc/pnv_core.c | 1 + hw/ppc/pnv_homer.c | 1 + hw/ppc/pnv_lpc.c | 1 + hw/ppc/pnv_xscom.c | 1 + 11 files changed, 160 insertions(+), 141 deletions(-) create mode 100644 include/hw/ppc/pnv_chip.h diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 9ef7e2d0dc..ca49e4281d 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -20,158 +20,19 @@ #ifndef PPC_PNV_H #define PPC_PNV_H =20 +#include "cpu.h" #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/ipmi/ipmi.h" -#include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_pnor.h" -#include "hw/ppc/pnv_psi.h" -#include "hw/ppc/pnv_occ.h" -#include "hw/ppc/pnv_sbe.h" -#include "hw/ppc/pnv_homer.h" -#include "hw/ppc/pnv_xive.h" -#include "hw/ppc/pnv_core.h" -#include "hw/pci-host/pnv_phb3.h" -#include "hw/pci-host/pnv_phb4.h" #include "hw/pci-host/pnv_phb.h" -#include "qom/object.h" =20 #define TYPE_PNV_CHIP "pnv-chip" -OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, - PNV_CHIP) =20 -struct PnvChip { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - uint32_t chip_id; - uint64_t ram_start; - uint64_t ram_size; - - uint32_t nr_cores; - uint32_t nr_threads; - uint64_t cores_mask; - PnvCore **cores; - - uint32_t num_pecs; - - MemoryRegion xscom_mmio; - MemoryRegion xscom; - AddressSpace xscom_as; - - MemoryRegion *fw_mr; - gchar *dt_isa_nodename; -}; - -#define TYPE_PNV8_CHIP "pnv8-chip" +typedef struct PnvChip PnvChip; typedef struct Pnv8Chip Pnv8Chip; -DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, - TYPE_PNV8_CHIP) - -struct Pnv8Chip { - /*< private >*/ - PnvChip parent_obj; - - /*< public >*/ - MemoryRegion icp_mmio; - - PnvLpcController lpc; - Pnv8Psi psi; - PnvOCC occ; - PnvHomer homer; - -#define PNV8_CHIP_PHB3_MAX 4 - /* - * The array is used to allow quick access to the phbs by - * pnv_ics_get_child() and pnv_ics_resend_child(). - */ - PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; - uint32_t num_phbs; - - XICSFabric *xics; -}; - -#define TYPE_PNV9_CHIP "pnv9-chip" typedef struct Pnv9Chip Pnv9Chip; -DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, - TYPE_PNV9_CHIP) - -struct Pnv9Chip { - /*< private >*/ - PnvChip parent_obj; - - /*< public >*/ - PnvXive xive; - Pnv9Psi psi; - PnvLpcController lpc; - PnvOCC occ; - PnvSBE sbe; - PnvHomer homer; - - uint32_t nr_quads; - PnvQuad *quads; - -#define PNV9_CHIP_MAX_PEC 3 - PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; -}; - -/* - * A SMT8 fused core is a pair of SMT4 cores. - */ -#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) - -#define TYPE_PNV10_CHIP "pnv10-chip" typedef struct Pnv10Chip Pnv10Chip; -DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, - TYPE_PNV10_CHIP) - -struct Pnv10Chip { - /*< private >*/ - PnvChip parent_obj; - - /*< public >*/ - PnvXive2 xive; - Pnv9Psi psi; - PnvLpcController lpc; - PnvOCC occ; - PnvSBE sbe; - PnvHomer homer; - - uint32_t nr_quads; - PnvQuad *quads; - -#define PNV10_CHIP_MAX_PEC 2 - PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; -}; - -#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) -#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) - -struct PnvChipClass { - /*< private >*/ - SysBusDeviceClass parent_class; - - /*< public >*/ - uint64_t chip_cfam_id; - uint64_t cores_mask; - uint32_t num_pecs; - uint32_t num_phbs; - - DeviceRealize parent_realize; - - uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); - void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); - void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); - void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); - void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); - ISABus *(*isa_create)(PnvChip *chip, Error **errp); - void (*dt_populate)(PnvChip *chip, void *fdt); - void (*pic_print_info)(PnvChip *chip, Monitor *mon); - uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); - uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); -}; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h new file mode 100644 index 0000000000..53e1d921d7 --- /dev/null +++ b/include/hw/ppc/pnv_chip.h @@ -0,0 +1,147 @@ +#ifndef PPC_PNV_CHIP_H +#define PPC_PNV_CHIP_H + +#include "hw/pci-host/pnv_phb4.h" +#include "hw/ppc/pnv_core.h" +#include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_lpc.h" +#include "hw/ppc/pnv_occ.h" +#include "hw/ppc/pnv_psi.h" +#include "hw/ppc/pnv_sbe.h" +#include "hw/ppc/pnv_xive.h" +#include "hw/sysbus.h" + +OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, + PNV_CHIP) + +struct PnvChip { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + uint32_t chip_id; + uint64_t ram_start; + uint64_t ram_size; + + uint32_t nr_cores; + uint32_t nr_threads; + uint64_t cores_mask; + PnvCore **cores; + + uint32_t num_pecs; + + MemoryRegion xscom_mmio; + MemoryRegion xscom; + AddressSpace xscom_as; + + MemoryRegion *fw_mr; + gchar *dt_isa_nodename; +}; + +#define TYPE_PNV8_CHIP "pnv8-chip" +DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, + TYPE_PNV8_CHIP) + +struct Pnv8Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ + MemoryRegion icp_mmio; + + PnvLpcController lpc; + Pnv8Psi psi; + PnvOCC occ; + PnvHomer homer; + +#define PNV8_CHIP_PHB3_MAX 4 + /* + * The array is used to allow quick access to the phbs by + * pnv_ics_get_child() and pnv_ics_resend_child(). + */ + PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; + uint32_t num_phbs; + + XICSFabric *xics; +}; + +#define TYPE_PNV9_CHIP "pnv9-chip" +DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, + TYPE_PNV9_CHIP) + +struct Pnv9Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ + PnvXive xive; + Pnv9Psi psi; + PnvLpcController lpc; + PnvOCC occ; + PnvSBE sbe; + PnvHomer homer; + + uint32_t nr_quads; + PnvQuad *quads; + +#define PNV9_CHIP_MAX_PEC 3 + PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; +}; + +/* + * A SMT8 fused core is a pair of SMT4 cores. + */ +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) + +#define TYPE_PNV10_CHIP "pnv10-chip" +DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, + TYPE_PNV10_CHIP) + +struct Pnv10Chip { + /*< private >*/ + PnvChip parent_obj; + + /*< public >*/ + PnvXive2 xive; + Pnv9Psi psi; + PnvLpcController lpc; + PnvOCC occ; + PnvSBE sbe; + PnvHomer homer; + + uint32_t nr_quads; + PnvQuad *quads; + +#define PNV10_CHIP_MAX_PEC 2 + PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; +}; + +#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) + +struct PnvChipClass { + /*< private >*/ + SysBusDeviceClass parent_class; + + /*< public >*/ + uint64_t chip_cfam_id; + uint64_t cores_mask; + uint32_t num_pecs; + uint32_t num_phbs; + + DeviceRealize parent_realize; + + uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); + void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); + void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); + ISABus *(*isa_create)(PnvChip *chip, Error **errp); + void (*dt_populate)(PnvChip *chip, void *fdt); + void (*pic_print_info)(PnvChip *chip, Monitor *mon); + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); +}; + +#endif diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index c7b75ed12e..622f9d28b7 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -18,6 +18,7 @@ #include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_xive.h" diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index f22ce5ca59..7176d70234 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -16,6 +16,7 @@ #include "monitor/monitor.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xive2.h" diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 9054c393a2..7a21497cf8 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -16,6 +16,7 @@ #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qom/object.h" diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 9871f462cd..43267a428f 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -17,6 +17,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" =20 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3d01e26f84..44b1fbbc93 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -44,9 +44,12 @@ #include "target/ppc/mmu-hash64.h" #include "hw/pci/msi.h" #include "hw/pci-host/pnv_phb.h" +#include "hw/pci-host/pnv_phb3.h" +#include "hw/pci-host/pnv_phb4.h" =20 #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_pnor.h" =20 diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 9ee79192dd..410f31bdf8 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -25,6 +25,7 @@ #include "target/ppc/cpu.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index ea73919e54..f9a203d11d 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -25,6 +25,7 @@ #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_xscom.h" =20 diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index ee890e7ab4..71143b7692 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -26,6 +26,7 @@ #include "hw/isa/isa.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/fdt.h" diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 79f10de57f..d820e05e40 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -26,6 +26,7 @@ =20 #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_xscom.h" =20 #include --=20 2.37.3 From nobody Sat May 18 23:14:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=BCK67qEWoS6wlbSxD7ZJcjy8yDv84CsBBrKiFhfHmrQ=; b=iBIkZR+4cuvnQB5ZBQ4sAcVLeVw5HjInfzBrofvcfEqiivpxJLKmeZ5eK/qbUxKPuMtkE1 EtZo/wVURwpc2B/sYVlehX1rAvQRPvfPv2bpXi0yeYoFBujVLhWqEImn1GNVbJYDam7lYe 6Gv2uHcpFwrsYrLV8g8GwRzrA95+Vmk= X-MC-Unique: t3bEPtlYONaONLfHkiTXVg-1 From: Markus Armbruster To: qemu-devel@nongnu.org Cc: clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH 2/4] include/hw/ppc: Supply a few missing includes Date: Sat, 10 Dec 2022 12:21:38 +0100 Message-Id: <20221210112140.4057731-3-armbru@redhat.com> In-Reply-To: <20221210112140.4057731-1-armbru@redhat.com> References: <20221210112140.4057731-1-armbru@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1670671404145100001 Content-Type: text/plain; charset="utf-8" A few headers neglect to include headers they need. They compile only if something else includes the required header(s) first. Fix that. Signed-off-by: Markus Armbruster Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Daniel Henrique Barboza --- include/hw/ppc/pnv_lpc.h | 3 ++- include/hw/ppc/pnv_occ.h | 3 ++- include/hw/ppc/pnv_pnor.h | 2 +- include/hw/ppc/pnv_sbe.h | 3 ++- include/hw/ppc/pnv_xscom.h | 3 ++- include/hw/ppc/xive2.h | 2 ++ include/hw/ppc/xive2_regs.h | 2 ++ 7 files changed, 13 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 8a8d1a3d42..001eee27d7 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -20,7 +20,8 @@ #ifndef PPC_PNV_LPC_H #define PPC_PNV_LPC_H =20 -#include "qom/object.h" +#include "exec/memory.h" +#include "hw/qdev-core.h" =20 #define TYPE_PNV_LPC "pnv-lpc" typedef struct PnvLpcClass PnvLpcClass; diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h index 90a81dae2b..df321244e3 100644 --- a/include/hw/ppc/pnv_occ.h +++ b/include/hw/ppc/pnv_occ.h @@ -20,7 +20,8 @@ #ifndef PPC_PNV_OCC_H #define PPC_PNV_OCC_H =20 -#include "qom/object.h" +#include "exec/memory.h" +#include "hw/qdev-core.h" =20 #define TYPE_PNV_OCC "pnv-occ" OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass, diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h index bab2f79844..2e37ac88bf 100644 --- a/include/hw/ppc/pnv_pnor.h +++ b/include/hw/ppc/pnv_pnor.h @@ -10,7 +10,7 @@ #ifndef PPC_PNV_PNOR_H #define PPC_PNV_PNOR_H =20 -#include "qom/object.h" +#include "hw/sysbus.h" =20 /* * PNOR offset on the LPC FW address space diff --git a/include/hw/ppc/pnv_sbe.h b/include/hw/ppc/pnv_sbe.h index f54a3ae9ba..b6b378ad14 100644 --- a/include/hw/ppc/pnv_sbe.h +++ b/include/hw/ppc/pnv_sbe.h @@ -20,7 +20,8 @@ #ifndef PPC_PNV_SBE_H #define PPC_PNV_SBE_H =20 -#include "qom/object.h" +#include "exec/memory.h" +#include "hw/qdev-core.h" =20 #define TYPE_PNV_SBE "pnv-sbe" OBJECT_DECLARE_TYPE(PnvSBE, PnvSBEClass, PNV_SBE) diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index c6e9ef8dd2..cbe848d27b 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -20,7 +20,8 @@ #ifndef PPC_PNV_XSCOM_H #define PPC_PNV_XSCOM_H =20 -#include "qom/object.h" +#include "exec/memory.h" +#include "hw/ppc/pnv.h" =20 typedef struct PnvXScomInterface PnvXScomInterface; =20 diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h index e9e3ea135e..ab68f8d157 100644 --- a/include/hw/ppc/xive2.h +++ b/include/hw/ppc/xive2.h @@ -11,7 +11,9 @@ #ifndef PPC_XIVE2_H #define PPC_XIVE2_H =20 +#include "hw/ppc/xive.h" #include "hw/ppc/xive2_regs.h" +#include "hw/sysbus.h" =20 /* * XIVE2 Router (POWER10) diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index 14605bd458..b7adbdb7b9 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -10,6 +10,8 @@ #ifndef PPC_XIVE2_REGS_H #define PPC_XIVE2_REGS_H =20 +#include "cpu.h" + /* * Thread Interrupt Management Area (TIMA) * --=20 2.37.3 From nobody Sat May 18 23:14:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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Sat, 10 Dec 2022 11:21:43 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.195.144]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 53893492CA2; Sat, 10 Dec 2022 11:21:43 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4A05A21E688F; Sat, 10 Dec 2022 12:21:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1670671305; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tnZjqXI+8QgKLYjU1tlfbJS3WbJYFVogopxlgXsVa90=; b=WuVQzIS4VVeeSb4OR+2xXqxVbW53ro1KMHE/e0aWSKExORol6yuXsTYelZKsqiZ51Kv6EU nJGWYCv499tBbXVtX8gxrCHnXp5JpSlqH2P1PEJKUG177kfILJCWu2y0vei5G5kq6zo9yN tPVgle9XlZ30KfeSHWENcaWWibN7qfk= X-MC-Unique: fRBEWjF3Mneg-iC6gJ8JKw-1 From: Markus Armbruster To: qemu-devel@nongnu.org Cc: clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH 3/4] include/hw/ppc: Don't include hw/pci-host/pnv_phb.h from pnv.h Date: Sat, 10 Dec 2022 12:21:39 +0100 Message-Id: <20221210112140.4057731-4-armbru@redhat.com> In-Reply-To: <20221210112140.4057731-1-armbru@redhat.com> References: <20221210112140.4057731-1-armbru@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1670671367928100011 Content-Type: text/plain; charset="utf-8" The next commit needs to include hw/ppc/pnv.h from hw/pci-host/pnv_phb.h. Avoid an inclusion loop. Signed-off-by: Markus Armbruster Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.h | 1 + include/hw/pci-host/pnv_phb4.h | 3 ++- include/hw/ppc/pnv.h | 3 ++- hw/ppc/pnv_psi.c | 1 + 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h index 58ebd6dd0f..202de8796c 100644 --- a/hw/pci-host/pnv_phb.h +++ b/hw/pci-host/pnv_phb.h @@ -12,6 +12,7 @@ =20 #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" +#include "hw/ppc/pnv.h" #include "qom/object.h" =20 typedef struct PnvChip PnvChip; diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index d9cea3f952..b4f2b29fb5 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -10,14 +10,15 @@ #ifndef PCI_HOST_PNV_PHB4_H #define PCI_HOST_PNV_PHB4_H =20 +#include "hw/pci-host/pnv_phb.h" #include "hw/pci/pci_bus.h" +#include "hw/ppc/pnv.h" #include "hw/ppc/xive.h" #include "qom/object.h" =20 typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; typedef struct PnvPHB4 PnvPHB4; -typedef struct PnvPHB PnvPHB; typedef struct PnvChip PnvChip; =20 /* diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index ca49e4281d..96fb850419 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -25,7 +25,6 @@ #include "hw/sysbus.h" #include "hw/ipmi/ipmi.h" #include "hw/ppc/pnv_pnor.h" -#include "hw/pci-host/pnv_phb.h" =20 #define TYPE_PNV_CHIP "pnv-chip" =20 @@ -59,6 +58,8 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, =20 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); =20 +typedef struct PnvPHB PnvPHB; + #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") typedef struct PnvMachineClass PnvMachineClass; typedef struct PnvMachineState PnvMachineState; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 98045ed3d2..8aa09ab26b 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "exec/address-spaces.h" #include "hw/irq.h" #include "target/ppc/cpu.h" #include "qemu/log.h" --=20 2.37.3 From nobody Sat May 18 23:14:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sat, 10 Dec 2022 06:22:03 -0500 Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-172-e2AcyroPMNWCYvcDMT83Sg-1; Sat, 10 Dec 2022 06:21:43 -0500 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9A54A3C025C2; Sat, 10 Dec 2022 11:21:43 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.195.144]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 53768C15BB1; Sat, 10 Dec 2022 11:21:43 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4C85F21E66CB; Sat, 10 Dec 2022 12:21:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1670671321; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=00/J5VGRYZGRVKtf+4XQ1b5g2OtTI0SBZf5sT9ERSQI=; b=W0tYEHybb/DsWjghRGhc9N0qzxBgui4sBbgrDXkLM6k1zPLUzIGZqESXvKszvpzP7QuvYK r2H8zlnFYc7+tdmPGUJJqHdtCSjGijnaIe62wodY7YQo1OSAWAinUv9sD5BFXZA2TJI71z rahrR7tKq56yV+XiEGuSenTJ6pMZe2g= X-MC-Unique: e2AcyroPMNWCYvcDMT83Sg-1 From: Markus Armbruster To: qemu-devel@nongnu.org Cc: clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH 4/4] include/hw/ppc include/hw/pci-host: Drop extra typedefs Date: Sat, 10 Dec 2022 12:21:40 +0100 Message-Id: <20221210112140.4057731-5-armbru@redhat.com> In-Reply-To: <20221210112140.4057731-1-armbru@redhat.com> References: <20221210112140.4057731-1-armbru@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1670671366343100001 Content-Type: text/plain; charset="utf-8" PnvChip is typedef'ed in five places, and PnvPhb4PecState in two. Keep one, drop the others. Signed-off-by: Markus Armbruster Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/pnv_phb.h | 1 - include/hw/pci-host/pnv_phb3.h | 1 - include/hw/pci-host/pnv_phb4.h | 2 -- include/hw/ppc/pnv_core.h | 3 +-- include/hw/ppc/pnv_homer.h | 2 +- include/hw/ppc/pnv_lpc.h | 8 ++------ include/hw/ppc/pnv_xive.h | 7 +++---- 7 files changed, 7 insertions(+), 17 deletions(-) diff --git a/hw/pci-host/pnv_phb.h b/hw/pci-host/pnv_phb.h index 202de8796c..eb429d529f 100644 --- a/hw/pci-host/pnv_phb.h +++ b/hw/pci-host/pnv_phb.h @@ -15,7 +15,6 @@ #include "hw/ppc/pnv.h" #include "qom/object.h" =20 -typedef struct PnvChip PnvChip; typedef struct PnvPhb4PecState PnvPhb4PecState; =20 struct PnvPHB { diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index f791ebda9b..d62b3091ac 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -15,7 +15,6 @@ #include "hw/pci-host/pnv_phb.h" =20 typedef struct PnvPHB3 PnvPHB3; -typedef struct PnvChip PnvChip; =20 /* * PHB3 XICS Source for MSIs diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index b4f2b29fb5..1f3237c9d5 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -16,10 +16,8 @@ #include "hw/ppc/xive.h" #include "qom/object.h" =20 -typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; typedef struct PnvPHB4 PnvPHB4; -typedef struct PnvChip PnvChip; =20 /* * We have one such address space wrapper per possible device under diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index c22eab2e1f..3d75706e95 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -22,14 +22,13 @@ =20 #include "hw/cpu/core.h" #include "target/ppc/cpu.h" +#include "hw/ppc/pnv.h" #include "qom/object.h" =20 #define TYPE_PNV_CORE "powernv-cpu-core" OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass, PNV_CORE) =20 -typedef struct PnvChip PnvChip; - struct PnvCore { /*< private >*/ CPUCore parent_obj; diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h index 07e8b19311..b1c5d498dc 100644 --- a/include/hw/ppc/pnv_homer.h +++ b/include/hw/ppc/pnv_homer.h @@ -39,7 +39,7 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER, struct PnvHomer { DeviceState parent; =20 - struct PnvChip *chip; + PnvChip *chip; MemoryRegion pba_regs; MemoryRegion regs; }; diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 001eee27d7..5d22c45570 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -21,6 +21,7 @@ #define PPC_PNV_LPC_H =20 #include "exec/memory.h" +#include "hw/ppc/pnv.h" #include "hw/qdev-core.h" =20 #define TYPE_PNV_LPC "pnv-lpc" @@ -93,13 +94,8 @@ struct PnvLpcClass { DeviceRealize parent_realize; }; =20 -/* - * Old compilers error on typdef forward declarations. Keep them happy. - */ -struct PnvChip; - ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **e= rrp); -int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset, +int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, uint64_t lpcm_size); =20 #endif /* PPC_PNV_LPC_H */ diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index b5d91505e5..9c48430ee4 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -10,12 +10,11 @@ #ifndef PPC_PNV_XIVE_H #define PPC_PNV_XIVE_H =20 +#include "hw/ppc/pnv.h" #include "hw/ppc/xive.h" #include "qom/object.h" #include "hw/ppc/xive2.h" =20 -struct PnvChip; - #define TYPE_PNV_XIVE "pnv-xive" OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass, PNV_XIVE) @@ -31,7 +30,7 @@ struct PnvXive { XiveRouter parent_obj; =20 /* Owning chip */ - struct PnvChip *chip; + PnvChip *chip; =20 /* XSCOM addresses giving access to the controller registers */ MemoryRegion xscom_regs; @@ -106,7 +105,7 @@ typedef struct PnvXive2 { Xive2Router parent_obj; =20 /* Owning chip */ - struct PnvChip *chip; + PnvChip *chip; =20 /* XSCOM addresses giving access to the controller registers */ MemoryRegion xscom_regs; --=20 2.37.3