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Thu, 08 Dec 2022 02:19:08 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:05 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:19:03 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483947; x=1702019947; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qf0GNk59NHI7jyBhbQufqfXZz6fUEohFJIgaFuYpNM8=; b=jqhuzjzsc0zrGh8Bg1jZQafnpNU5oIbyH/YUyu8MpYtd+WLifMt9Y1tY Pj/Q3M7dLxr3NbrDEe0s2TqPYnnC0zA73srbOHM/BY33nSCjaZDfcDHZf KT2xJRuKryhlOjJwVu4rlaugKlneqZJQKX3oS9dAQ/uoy1VaJC2PC/sDr Gq/ef8ov6I/Lv/mKwCsckPPCIr58TK3uIHQFexsjLlUY4bhYxvcWcxfla rneva4L/zmYmDltRif+Qi0krdraTWPeBb7G42Tl/rvjuBFYPb2B7ainep 7WRKnjhpBhwCkHYc5+Ok5sXcf0paSbF7NmT6gNdTwY0aGyWhLrJIuUC8s A==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263823" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263823" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771381001" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771381001" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 4/6] target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:15 +0800 Message-Id: <20221208071917.1923093-5-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484021633100001 Content-Type: text/plain; charset="utf-8" AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform Sierra Forest, aims for the platform to have superior AI capabilities. This instruction multiplies the individual bytes of two unsigned or unsigned source operands, then adds and accumulates the results into the destination dword element size operand. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EDX[bit 4] AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word FEAT_7_1_EDX for this leaf. Add CPUID definition for AVX-VNNI-INT8. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 22 +++++++++++++++++++++- target/i386/cpu.h | 4 ++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5ba0fc61d2..ea1daf6b7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -663,6 +663,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo= r1, CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES) #define TCG_7_0_EDX_FEATURES 0 #define TCG_7_1_EAX_FEATURES 0 +#define TCG_7_1_EDX_FEATURES 0 #define TCG_APM_FEATURES 0 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) @@ -886,6 +887,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { }, .tcg_features =3D TCG_7_1_EAX_FEATURES, }, + [FEAT_7_1_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + "avx-vnni-int8", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EDX, + }, + .tcg_features =3D TCG_7_1_EDX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -5387,9 +5407,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } } else if (count =3D=3D 1) { *eax =3D env->features[FEAT_7_1_EAX]; + *edx =3D env->features[FEAT_7_1_EDX]; *ebx =3D 0; *ecx =3D 0; - *edx =3D 0; } else { *eax =3D 0; *ebx =3D 0; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1223f0018b..da4fb1cfca 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -623,6 +623,7 @@ typedef enum FeatureWord { FEAT_SGX_12_1_EAX, /* CPUID[EAX=3D0x12,ECX=3D1].EAX (SGX ATTRIBUTES[3= 1:0]) */ FEAT_XSAVE_XSS_LO, /* CPUID[EAX=3D0xd,ECX=3D1].ECX */ FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ + FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEATURE_WORDS, } FeatureWord; =20 @@ -907,6 +908,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, /* Support for VPMADD52[H,L]UQ */ #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) =20 +/* Support for VPDPB[SU,UU,SS]D[,S] */ +#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) + /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) =20 --=20 2.27.0