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Thu, 08 Dec 2022 02:19:06 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:00 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:18:58 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483943; x=1702019943; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5P4u8pc/P3y8YT4F9M/OpcvLjyeo01HCojexn+arJpM=; b=LkOsqvh9d5YWVi3JW5E4wg+CVhVswWaLRRcP/ZfoOX6bRhVwQXWKTgr+ lhOYe19WlJ1WGY/RFWgsxzZmPAThWollYuo14iNvXCkIIsqRt79qmdOhh HTzQwAlnPfQ4rXKQXCZQrEJU7dYs1nRcxp5+cwOccgtq63eW3B1LtxzTh /MEskTPQQpjaNR1+eGkP7SCC5tJ6ZzDBk1OzjKPcpJafsfgGlm34CZJ9Y j6bhj4c3V0GnurXfFheC6wpcmnqnilTCKFwEhLlm9LNeQOS/u282E94fu BOdCKcdAlt1VISoGqkrn+rnsWB5SrNpPz1bNxUCSGehLSFuwlIyDuEm1H w==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263797" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263797" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771380966" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771380966" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 1/6] target/i386: Add support for CMPCCXADD in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:12 +0800 Message-Id: <20221208071917.1923093-2-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484021701100005 Content-Type: text/plain; charset="utf-8" CMPccXADD is a new set of instructions in the latest Intel platform Sierra Forest. This new instruction set includes a semaphore operation that can compare and add the operands if condition is met, which can improve database performance. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[bit 7] Add CPUID definition for CMPCCXADD. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 22b681ca37..a61f936eef 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -871,7 +871,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, - "avx-vnni", "avx512-bf16", NULL, NULL, + "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a..3391b99456 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -900,6 +900,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* CMPCCXADD Instructions */ +#define CPUID_7_1_EAX_CMPCCXADD (1U << 7) + /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) =20 --=20 2.27.0