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Thu, 08 Dec 2022 02:19:06 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:00 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:18:58 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483943; x=1702019943; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5P4u8pc/P3y8YT4F9M/OpcvLjyeo01HCojexn+arJpM=; b=LkOsqvh9d5YWVi3JW5E4wg+CVhVswWaLRRcP/ZfoOX6bRhVwQXWKTgr+ lhOYe19WlJ1WGY/RFWgsxzZmPAThWollYuo14iNvXCkIIsqRt79qmdOhh HTzQwAlnPfQ4rXKQXCZQrEJU7dYs1nRcxp5+cwOccgtq63eW3B1LtxzTh /MEskTPQQpjaNR1+eGkP7SCC5tJ6ZzDBk1OzjKPcpJafsfgGlm34CZJ9Y j6bhj4c3V0GnurXfFheC6wpcmnqnilTCKFwEhLlm9LNeQOS/u282E94fu BOdCKcdAlt1VISoGqkrn+rnsWB5SrNpPz1bNxUCSGehLSFuwlIyDuEm1H w==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263797" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263797" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771380966" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771380966" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 1/6] target/i386: Add support for CMPCCXADD in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:12 +0800 Message-Id: <20221208071917.1923093-2-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484021701100005 Content-Type: text/plain; charset="utf-8" CMPccXADD is a new set of instructions in the latest Intel platform Sierra Forest. This new instruction set includes a semaphore operation that can compare and add the operands if condition is met, which can improve database performance. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[bit 7] Add CPUID definition for CMPCCXADD. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 22b681ca37..a61f936eef 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -871,7 +871,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, - "avx-vnni", "avx512-bf16", NULL, NULL, + "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a..3391b99456 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -900,6 +900,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* CMPCCXADD Instructions */ +#define CPUID_7_1_EAX_CMPCCXADD (1U << 7) + /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) =20 --=20 2.27.0 From nobody Tue May 21 04:16:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 08 Dec 2022 02:19:05 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:02 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:19:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483943; x=1702019943; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aAKPvvdkThcSw9GRG1GBVerUpb+6XelTv1ChgCwcr7Y=; b=hBP9nK5I1kWaDAVNCvwUwd/PnCftPetb3q5eKXQq/56mL8Ab/tDV94k6 hY+nojF5flGUygTQL+LnOg+jVnkyIMeYdfClKb8wWAwxue3HSTSmxqSQR OxdMW8z7CcnniXlJB1/6G3MFHKGnsEyocxPOg7DG3IhXCKNA9khxzobDj Rf1nNL95/rkyTix4RQYy/zhGalSjDFugBNLZOk47YQKJibaF1LiAcvhNV wae7fyAYgJITmZPV4mB/bWv9h3ZaSTdYrg9XzKI3/nbwMIJ8VKEhGz7Kx OZ8AU1K6J8vHxfmoSrg8p/gDDSdVV9q+IOZMC5/S3Snw2VUXi2JhSWhX1 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263801" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263801" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771380978" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771380978" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 2/6] target/i386: Add support for AMX-FP16 in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:13 +0800 Message-Id: <20221208071917.1923093-3-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484023629100021 Content-Type: text/plain; charset="utf-8" Latest Intel platform Granite Rapids has introduced a new instruction - AMX-FP16, which performs dot-products of two FP16 tiles and accumulates the results into a packed single precision tile. AMX-FP16 adds FP16 capability and allows a FP16 GPU trained model to run faster without loss of accuracy or added SW overhead. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[bit 21] Add CPUID definition for AMX-FP16. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a61f936eef..cd787b3d97 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -875,7 +875,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "amx-fp16", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3391b99456..d2e3079dfb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -902,6 +902,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* CMPCCXADD Instructions */ #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) +/* Support Tile Computational Operations on FP16 Numbers */ +#define CPUID_7_1_EAX_AMX_FP16 (1U << 21) =20 /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) --=20 2.27.0 From nobody Tue May 21 04:16:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 08 Dec 2022 02:19:07 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:03 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:19:02 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483946; x=1702019946; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MkFFo4rJwEOR9p5BWB5id/CYu+DNnKqymXPoq4ZpBXk=; b=kHiLYfx2ZOhbmo+Dk1OuHMauB98vR0LVFEXT3l/ADG3oBtIOwqrdWU0N Yknwu0+piXdD7V7uGuc37h+o83+XITKjUkkoVfdQx2qzI7ldklV3eKkgw mzLaWCVN3wBF7LWnk1lRwZBsQvuUURI4INCk+4iWyLCnP4u3N8hUR07kJ 3Y6wae53Wzx1eIw69MHYgavHBDWXCA+U+JJWk/RjM3HSv8yBfMKfz3jhT ESIIVixPadMtlYw0yDJ6ja1beiNLhHZMNxX9VcmOmi4fH8zl7SZxPz2eR muh6FKBOASVXuczPSRHjKuxiE8ZWzdf70RwXI80kG9kJUJY15AsXNAWwG A==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263805" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263805" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771380991" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771380991" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 3/6] target/i386: Add support for AVX-IFMA in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:14 +0800 Message-Id: <20221208071917.1923093-4-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484021638100002 Content-Type: text/plain; charset="utf-8" AVX-IFMA is a new instruction in the latest Intel platform Sierra Forest. This instruction packed multiplies unsigned 52-bit integers and adds the low/high 52-bit products to Qword Accumulators. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[bit 23] Add CPUID definition for AVX-IFMA. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cd787b3d97..5ba0fc61d2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -875,7 +875,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, "amx-fp16", NULL, NULL, + NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d2e3079dfb..1223f0018b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -904,6 +904,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) /* Support Tile Computational Operations on FP16 Numbers */ #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) +/* Support for VPMADD52[H,L]UQ */ +#define CPUID_7_1_EAX_AVX_IFMA (1U << 23) =20 /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) --=20 2.27.0 From nobody Tue May 21 04:16:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 08 Dec 2022 02:19:08 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:05 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:19:03 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483947; x=1702019947; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qf0GNk59NHI7jyBhbQufqfXZz6fUEohFJIgaFuYpNM8=; b=jqhuzjzsc0zrGh8Bg1jZQafnpNU5oIbyH/YUyu8MpYtd+WLifMt9Y1tY Pj/Q3M7dLxr3NbrDEe0s2TqPYnnC0zA73srbOHM/BY33nSCjaZDfcDHZf KT2xJRuKryhlOjJwVu4rlaugKlneqZJQKX3oS9dAQ/uoy1VaJC2PC/sDr Gq/ef8ov6I/Lv/mKwCsckPPCIr58TK3uIHQFexsjLlUY4bhYxvcWcxfla rneva4L/zmYmDltRif+Qi0krdraTWPeBb7G42Tl/rvjuBFYPb2B7ainep 7WRKnjhpBhwCkHYc5+Ok5sXcf0paSbF7NmT6gNdTwY0aGyWhLrJIuUC8s A==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263823" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263823" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771381001" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771381001" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 4/6] target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:15 +0800 Message-Id: <20221208071917.1923093-5-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484021633100001 Content-Type: text/plain; charset="utf-8" AVX-VNNI-INT8 is a new set of instructions in the latest Intel platform Sierra Forest, aims for the platform to have superior AI capabilities. This instruction multiplies the individual bytes of two unsigned or unsigned source operands, then adds and accumulates the results into the destination dword element size operand. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EDX[bit 4] AVX-VNNI-INT8 is on a new feature bits leaf. Add a CPUID feature word FEAT_7_1_EDX for this leaf. Add CPUID definition for AVX-VNNI-INT8. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 22 +++++++++++++++++++++- target/i386/cpu.h | 4 ++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5ba0fc61d2..ea1daf6b7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -663,6 +663,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo= r1, CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES) #define TCG_7_0_EDX_FEATURES 0 #define TCG_7_1_EAX_FEATURES 0 +#define TCG_7_1_EDX_FEATURES 0 #define TCG_APM_FEATURES 0 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) @@ -886,6 +887,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { }, .tcg_features =3D TCG_7_1_EAX_FEATURES, }, + [FEAT_7_1_EDX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + "avx-vnni-int8", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 7, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EDX, + }, + .tcg_features =3D TCG_7_1_EDX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -5387,9 +5407,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } } else if (count =3D=3D 1) { *eax =3D env->features[FEAT_7_1_EAX]; + *edx =3D env->features[FEAT_7_1_EDX]; *ebx =3D 0; *ecx =3D 0; - *edx =3D 0; } else { *eax =3D 0; *ebx =3D 0; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1223f0018b..da4fb1cfca 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -623,6 +623,7 @@ typedef enum FeatureWord { FEAT_SGX_12_1_EAX, /* CPUID[EAX=3D0x12,ECX=3D1].EAX (SGX ATTRIBUTES[3= 1:0]) */ FEAT_XSAVE_XSS_LO, /* CPUID[EAX=3D0xd,ECX=3D1].ECX */ FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ + FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEATURE_WORDS, } FeatureWord; =20 @@ -907,6 +908,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, /* Support for VPMADD52[H,L]UQ */ #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) =20 +/* Support for VPDPB[SU,UU,SS]D[,S] */ +#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) + /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) =20 --=20 2.27.0 From nobody Tue May 21 04:16:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 08 Dec 2022 02:19:11 -0500 Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 23:19:08 -0800 Received: from jiaxichen-precision-3650-tower.sh.intel.com ([10.239.159.75]) by orsmga004.jf.intel.com with ESMTP; 07 Dec 2022 23:19:05 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670483949; x=1702019949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A6hTx64n7tysQkie6LmQ+Wxh4q4wBOtCQDsxN+oT8PA=; b=AooR8ynNtEtQ042guiQyEkyvFi0iuahNxI5osC4ePsonxkNrg5eglZ6i 1EMlbYc1pow3SB2SxCP0kQ9rKBP0f42Da13WbGBr1ptFMfHIt1BRbqRi3 T6upWPqETo8PdptorvGp714S0LgOE/a5ZMg5eOoUHf463WLGvSN+tbbyX mgqNWyuv1U8XOsFR1hktQPjn+B9DbojKjA8p+h4sGfMXHrjEaAGW97qdY W6ytKXvhnhODbRR5cI7FupbAiDz3AMSvlkT9Of8wtiOld7N3fUKsfT7mX 0KndbijEKC2AXrR2yxoEIcK1Jih130KcWX0cmfgVtau2hgtqF3p2qQTnZ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="379263846" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263846" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771381005" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771381005" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 5/6] target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:16 +0800 Message-Id: <20221208071917.1923093-6-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484023624100020 Content-Type: text/plain; charset="utf-8" AVX-NE-CONVERT is a new set of instructions which can convert low precision floating point like BF16/FP16 to high precision floating point FP32, as well as convert FP32 elements to BF16. This instruction allows the platform to have improved AI capabilities and better compatibility. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EDX[bit 5] Add CPUID definition for AVX-NE-CONVERT. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ea1daf6b7e..4aca5360cc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -891,7 +891,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, NULL, NULL, NULL, - "avx-vnni-int8", NULL, NULL, NULL, + "avx-vnni-int8", "avx-ne-convert", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index da4fb1cfca..c4571d726c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -910,6 +910,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, =20 /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) +/* AVX NE CONVERT Instructions */ +#define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) =20 /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) --=20 2.27.0 From nobody Tue May 21 04:16:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="379263853" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="379263853" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="771381013" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="771381013" From: Jiaxi Chen To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, richard.henderson@linaro.org, yang.zhong@intel.com, jing2.liu@intel.com, vkuznets@redhat.com Subject: [PATCH 6/6] target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration Date: Thu, 8 Dec 2022 15:19:17 +0800 Message-Id: <20221208071917.1923093-7-jiaxi.chen@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> References: <20221208071917.1923093-1-jiaxi.chen@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.31; envelope-from=jiaxi.chen@linux.intel.com; helo=mga06.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670484023612100019 Content-Type: text/plain; charset="utf-8" Latest Intel platform Granite Rapids has introduced a new instruction - PREFETCHIT0/1, which moves code to memory (cache) closer to the processor depending on specific hints. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EDX[bit 14] Add CPUID definition for PREFETCHIT0/1. Signed-off-by: Jiaxi Chen --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4aca5360cc..81d13800db 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -893,7 +893,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, NULL, NULL, NULL, "avx-vnni-int8", "avx-ne-convert", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "prefetchiti", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c4571d726c..7b55ef289d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -912,6 +912,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) /* AVX NE CONVERT Instructions */ #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) +/* PREFETCHIT0/1 Instructions */ +#define CPUID_7_1_EDX_PREFETCHITI (1U << 14) =20 /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) --=20 2.27.0