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d="scan'208";a="297444481" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413421" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413421" From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 5/8] target/i386/intel-pt: Rework/rename the default INTEL-PT feature set Date: Thu, 8 Dec 2022 14:25:10 +0800 Message-Id: <20221208062513.2589476-6-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xiaoyao.li@intel.com; helo=mga17.intel.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.999, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670480878215100009 Content-Type: text/plain; charset="utf-8" Historically the Intel PT feature set reported from ICX silicon was chosen as the fixed feature set for Intel PT. If want to enable and expose INTEL-PT to guest, the supported Intel PT reported by host must cover the fixed feature set, which are named with MINIMAL in INTEL_PT_MINIMAL_EBX and INTEL_PT_MINIMAL_ECX. However, it's not accurate that it's more as default than minimal since SPR has less capabilities regarding CPUID(0x14,1):EBX[15:0]. Rename the feature set name to avoid future confusion and opportunistically define each feature bit. No functional change intended. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 70 ++++++++++++++++++++++------------------------- target/i386/cpu.h | 34 ++++++++++++++++++++++- 2 files changed, 65 insertions(+), 39 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4d7beccc0af7..e302cbbebfc5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -546,34 +546,29 @@ static CPUCacheInfo legacy_l3_cache =3D { #define L2_ITLB_4K_ASSOC 4 #define L2_ITLB_4K_ENTRIES 512 =20 -/* CPUID Leaf 0x14 constants: */ -#define INTEL_PT_MAX_SUBLEAF 0x1 -/* - * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MAT= CH - * MSR can be accessed; - * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; - * bit[02]: Support IP Filtering, TraceStop filtering, and preservation - * of Intel PT MSRs across warm reset; - * bit[03]: Support MTC timing packet and suppression of COFI-based packet= s; - */ -#define INTEL_PT_MINIMAL_EBX 0xf -/* - * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA =3D 1 and - * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can = be - * accessed; - * bit[01]: ToPA tables can hold any number of output entries, up to the - * maximum allowed by the MaskOrTableOffset field of - * IA32_RTIT_OUTPUT_MASK_PTRS; - * bit[02]: Support Single-Range Output scheme; - */ -#define INTEL_PT_MINIMAL_ECX 0x7 -/* generated packets which contain IP payloads have LIP values */ -#define INTEL_PT_IP_LIP (1 << 31) -#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ran= ges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 -#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ -#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ -#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ +/* INTEL PT definitions: */ + +#define INTEL_PT_MAX_SUBLEAF 0x1 + +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 +#define INTEL_PT_DEFAULT_ADDR_RANGES_NUM 0x2 + +/* Support ART(0,3,6,9) */ +#define INTEL_PT_DEFAULT_MTC_BITMAP (0x0249 << 16) +/* Support 0,2^(0~11) */ +#define INTEL_PT_DEFAULT_CYCLE_BITMAP 0x1fff +/* Support 2K,4K,8K,16K,32K,64K */ +#define INTEL_PT_DEFAULT_PSB_BITMAP (0x003f << 16) + +#define INTEL_PT_DEFAULT_0_EBX (CPUID_14_0_EBX_CR3_FILTER | CPUID_14_0_EB= X_PSB | \ + CPUID_14_0_EBX_IP_FILTER | CPUID_14_0_EBX= _MTC) + +#define INTEL_PT_DEFAULT_0_ECX (CPUID_14_0_ECX_TOPA | CPUID_14_0_ECX_MULT= I_ENTRIES | \ + CPUID_14_0_ECX_SINGLE_RANGE) + +#define INTEL_PT_DEFAULT_1_EAX (INTEL_PT_DEFAULT_MTC_BITMAP | INTEL_PT_DE= FAULT_ADDR_RANGES_NUM) + +#define INTEL_PT_DEFAULT_1_EBX (INTEL_PT_DEFAULT_PSB_BITMAP | INTEL_PT_DE= FAULT_CYCLE_BITMAP) =20 /* CPUID Leaf 0x1D constants: */ #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 @@ -5721,14 +5716,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 if (count =3D=3D 0) { *eax =3D INTEL_PT_MAX_SUBLEAF; - *ebx =3D INTEL_PT_MINIMAL_EBX; - *ecx =3D INTEL_PT_MINIMAL_ECX; + *ebx =3D INTEL_PT_DEFAULT_0_EBX; + *ecx =3D INTEL_PT_DEFAULT_0_ECX; if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { *ecx |=3D CPUID_14_0_ECX_LIP; } } else if (count =3D=3D 1) { - *eax =3D INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; - *ebx =3D INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; + *eax =3D INTEL_PT_DEFAULT_1_EAX; + *ebx =3D INTEL_PT_DEFAULT_1_EBX; } break; } @@ -6473,13 +6468,12 @@ static void x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) uint32_t ebx_1 =3D kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); =20 if (!eax_0 || - ((ebx_0 & INTEL_PT_MINIMAL_EBX) !=3D INTEL_PT_MINIMAL_EBX) || - ((ecx_0 & INTEL_PT_MINIMAL_ECX) !=3D INTEL_PT_MINIMAL_ECX) || - ((eax_1 & INTEL_PT_MTC_BITMAP) !=3D INTEL_PT_MTC_BITMAP) || + ((ebx_0 & INTEL_PT_DEFAULT_0_EBX) !=3D INTEL_PT_DEFAULT_0_EBX) = || + ((ecx_0 & INTEL_PT_DEFAULT_0_ECX) !=3D INTEL_PT_DEFAULT_0_ECX) = || + ((eax_1 & INTEL_PT_DEFAULT_MTC_BITMAP) !=3D INTEL_PT_DEFAULT_MT= C_BITMAP) || ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < - INTEL_PT_ADDR_RANGES_NUM) || - ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=3D - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || + INTEL_PT_DEFAULT_ADDR_RANGES_NUM) || + ((ebx_1 & INTEL_PT_DEFAULT_1_EBX) !=3D INTEL_PT_DEFAULT_1_EBX) = || ((ecx_0 & CPUID_14_0_ECX_LIP) !=3D (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { /* diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d8b3535d5aa7..93fb5a87b40e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -906,8 +906,40 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWor= d w, /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) =20 +/* + * IA32_RTIT_CTL.CR3 filter can be set to 1 and + * IA32_RTIT_CR3_MATCH can be accessed + */ +#define CPUID_14_0_EBX_CR3_FILTER (1U << 0) +/* Support Configurable PSB and Cycle-Accurate Mode */ +#define CPUID_14_0_EBX_PSB (1U << 1) +/* + * Support IP Filtering, IP TraceStop, and preservation + * of Intel PT MSRs across warm reset + */ +#define CPUID_14_0_EBX_IP_FILTER (1U << 2) +/* Support MTC timing packet */ +#define CPUID_14_0_EBX_MTC (1U << 3) +/* Support PTWRITE */ +#define CPUID_14_0_EBX_PTWRITE (1U << 4) +/* Support Power Event Trace packet generation */ +#define CPUID_14_0_EBX_POWER_EVENT (1U << 5) +/* Support PSB and PMI Preservation */ +#define CPUID_14_0_EBX_PSB_PMI_PRESERVATION (1U << 6) + +/* Tracing can be enabled with IA32_RTIT_CTL.ToPA =3D 1 */ +#define CPUID_14_0_ECX_TOPA (1U << 0) +/* + * ToPA tables can hold any number of output entries, up to the maximum al= lowed + * by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS + */ +#define CPUID_14_0_ECX_MULTI_ENTRIES (1U << 1) +/* Support Single-Range Output scheme */ +#define CPUID_14_0_ECX_SINGLE_RANGE (1U << 2) +/* Support IA32_RTIT_CTL.FabricEn */ +#define CPUID_14_0_ECX_TRACE_TRANS_SUBSYSTEM (1U << 3) /* Packets which contain IP payload have LIP values */ -#define CPUID_14_0_ECX_LIP (1U << 31) +#define CPUID_14_0_ECX_LIP (1U << 31) =20 /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) --=20 2.27.0