From nobody Mon Feb 9 22:38:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1670480801; cv=none; d=zohomail.com; s=zohoarc; b=oAggBXVBgQAYUv7dUp7Fx0r90bWM2+N9ruBW3gd5bAHp5tFLpgQzY9nUEBWtNh7WeE7sQbuORg8QS0neJsqrWeeKL0NJWFg7GBlKN5rpEHw0oqjJ6hG6SQxm+o0mmuxEnwipBjqeWswyOmkHeGsWdZPtqQULYCenAKZ2cq47z7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670480801; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XRx1oTVe3t2EejrwSbuYDUFAlm2ZtZ5m6dAn+gsVS9o=; b=GsjQp6ICs+C33wD0VG0IDSzU1kKioAEHGDvI4+PEOwcCF8BkpArtQvPmCLXhFqR5J+OhYNxinNgAA4XBY6jtB2GgNMBKzd+NT8KhuD+xuwGQHwk5kFYTWc+GOnvWHb7f+9kp2vPYD7jCqpgkRHBI46INTczcqTTxH7ez4vJuKoI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1670480801824354.15765480210916; Wed, 7 Dec 2022 22:26:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p3ALn-0000jP-9u; Thu, 08 Dec 2022 01:25:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p3ALa-0000iA-7p for qemu-devel@nongnu.org; Thu, 08 Dec 2022 01:25:31 -0500 Received: from mga17.intel.com ([192.55.52.151]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p3ALX-0005MN-Hy for qemu-devel@nongnu.org; Thu, 08 Dec 2022 01:25:29 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2022 22:25:20 -0800 Received: from lxy-dell.sh.intel.com ([10.239.48.100]) by orsmga001.jf.intel.com with ESMTP; 07 Dec 2022 22:25:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670480727; x=1702016727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qqDomaWAedABch5XRX7qa2ftKhkbEh7yFAQLtdbNsts=; b=h9Fi482cJV9pPwwEqmT8zlz7w/ilUlMt87/bT0c1fWeKbmnKaH1yEcbK ImTRpAoqNmMXf0zCm6nooyD+eWaOZVvGO/Jc04X8AFgTHxsuihO/vBp8v vfqAk5cw62E/AtHt2IPXLVi9OrwpulkKNzmZGXKNnu11g3AQzHbp+8j0o SwmMHlMGBdtFR2Md/TWpVPCeqHoHHzGOTX3RLhC2f7t+JZofW3n3+btle 3IXF47ME9bexyFr9XwPEqIT35REHLukppQb+nSDgh4KytjD3RUo6qmVEv 2aLJ6bVYjxEGG3sOnfr4ZUDIKgmE0aObKy3RU8++CjqnZ6a7dwElj+bg3 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="297444458" X-IronPort-AV: E=Sophos;i="5.96,226,1665471600"; d="scan'208";a="297444458" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10554"; a="679413402" X-IronPort-AV: E=Sophos;i="5.96,227,1665471600"; d="scan'208";a="679413402" From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, xiaoyao.li@intel.com Subject: [PATCH v3 3/8] target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0x14 Date: Thu, 8 Dec 2022 14:25:08 +0800 Message-Id: <20221208062513.2589476-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221208062513.2589476-1-xiaoyao.li@intel.com> References: <20221208062513.2589476-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.151; envelope-from=xiaoyao.li@intel.com; helo=mga17.intel.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.999, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1670480803773100003 Content-Type: text/plain; charset="utf-8" CPUID leaf 0x14 subleaf 0x0 and 0x1 enumerate the resource and capability of Intel PT. Introduce FeatureWord FEAT_14_0_EBX, FEAT_14_1_EAX and FEAT_14_1_EBX, and complete FEAT_14_0_ECX. Thus all the features of Intel PT can be expanded when "-cpu host/max" and can be configured in named CPU model. Signed-off-by: Xiaoyao Li --- v3: - Add bit 7 and 8 of FEAT_14_0_EBX --- target/i386/cpu.c | 138 +++++++++++++++++++++++++++++++++++++++++++--- target/i386/cpu.h | 3 + 2 files changed, 132 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9ae36639d380..65c6f8ae771a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1208,17 +1208,34 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = =3D { } }, =20 + [FEAT_14_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [0] =3D "intel-pt-cr3-filter", + [1] =3D "intel-pt-psb", + [2] =3D "intel-pt-ip-filter", + [3] =3D "intel-pt-mtc", + [4] =3D "intel-pt-ptwrite", + [5] =3D "intel-pt-power-event", + [6] =3D "intel-pt-psb-pmi-preservation", + [7] =3D "intel-pt-event-trace", + [8] =3D "intel-pt-tnt-disable", + }, + .cpuid =3D { + .eax =3D 0x14, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, + }, + }, + [FEAT_14_0_ECX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, - NULL, NULL, NULL, "intel-pt-lip", + [0] =3D "intel-pt-topa", + [1] =3D "intel-pt-multi-topa-entries", + [2] =3D "intel-pt-single-range", + [3] =3D "intel-pt-trace-transport-subsystem", + [31] =3D "intel-pt-lip", }, .cpuid =3D { .eax =3D 0x14, @@ -1228,6 +1245,79 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { .tcg_features =3D TCG_14_0_ECX_FEATURES, }, =20 + [FEAT_14_1_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [0] =3D "intel-pt-addr-range-num-bit0", + [1] =3D "intel-pt-addr-range-num-bit1", + [2] =3D "intel-pt-addr-range-num-bit2", + [16] =3D "intel-pt-mtc-period-encoding-0", + [17] =3D "intel-pt-mtc-period-encoding-1", + [18] =3D "intel-pt-mtc-period-encoding-2", + [19] =3D "intel-pt-mtc-period-encoding-3", + [20] =3D "intel-pt-mtc-period-encoding-4", + [21] =3D "intel-pt-mtc-period-encoding-5", + [22] =3D "intel-pt-mtc-period-encoding-6", + [23] =3D "intel-pt-mtc-period-encoding-7", + [24] =3D "intel-pt-mtc-period-encoding-8", + [25] =3D "intel-pt-mtc-period-encoding-9", + [26] =3D "intel-pt-mtc-period-encoding-10", + [27] =3D "intel-pt-mtc-period-encoding-11", + [28] =3D "intel-pt-mtc-period-encoding-12", + [29] =3D "intel-pt-mtc-period-encoding-13", + [30] =3D "intel-pt-mtc-period-encoding-14", + [31] =3D "intel-pt-mtc-period-encoding-15", + }, + .cpuid =3D { + .eax =3D 0x14, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, + }, + }, + + [FEAT_14_1_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [0] =3D "intel-pt-cyc-thresh-0", + [1] =3D "intel-pt-cyc-thresh-1", + [2] =3D "intel-pt-cyc-thresh-2", + [3] =3D "intel-pt-cyc-thresh-4", + [4] =3D "intel-pt-cyc-thresh-8", + [5] =3D "intel-pt-cyc-thresh-16", + [6] =3D "intel-pt-cyc-thresh-32", + [7] =3D "intel-pt-cyc-thresh-64", + [8] =3D "intel-pt-cyc-thresh-128", + [9] =3D "intel-pt-cyc-thresh-256", + [10] =3D "intel-pt-cyc-thresh-512", + [11] =3D "intel-pt-cyc-thresh-1024", + [12] =3D "intel-pt-cyc-thresh-2048", + [13] =3D "intel-pt-cyc-thresh-4096", + [14] =3D "intel-pt-cyc-thresh-8192", + [15] =3D "intel-pt-cyc-thresh-16384", + [16] =3D "intel-pt-psb-freq-2k", + [17] =3D "intel-pt-psb-freq-4k", + [18] =3D "intel-pt-psb-freq-8k", + [19] =3D "intel-pt-psb-freq-16k", + [20] =3D "intel-pt-psb-freq-32k", + [21] =3D "intel-pt-psb-freq-64k", + [22] =3D "intel-pt-psb-freq-128k", + [23] =3D "intel-pt-psb-freq-256k", + [24] =3D "intel-pt-psb-freq-512k", + [25] =3D "intel-pt-psb-freq-1m", + [26] =3D "intel-pt-psb-freq-2m", + [27] =3D "intel-pt-psb-freq-4m", + [28] =3D "intel-pt-psb-freq-8m", + [29] =3D "intel-pt-psb-freq-16m", + [30] =3D "intel-pt-psb-freq-32m", + [31] =3D "intel-pt-psb-freq-64m", + }, + .cpuid =3D { + .eax =3D 0x14, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EBX, + }, + }, + [FEAT_SGX_12_0_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1367,10 +1457,22 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, .to =3D { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EX= ITING }, }, + { + .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to =3D { FEAT_14_0_EBX, ~0ull }, + }, { .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, .to =3D { FEAT_14_0_ECX, ~0ull }, }, + { + .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to =3D { FEAT_14_1_EAX, ~0ull }, + }, + { + .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to =3D { FEAT_14_1_EBX, ~0ull }, + }, { .from =3D { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, .to =3D { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, @@ -6332,7 +6434,25 @@ static void x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) uint64_t host_feat =3D x86_cpu_get_supported_feature_word(w, false); uint64_t requested_features =3D env->features[w]; - uint64_t unavailable_features =3D requested_features & ~host_feat; + uint64_t unavailable_features; + + switch (w) { + case FEAT_14_1_EAX: + /* Handling the bits except INTEL_PT_ADDR_RANGES_NUM_MASK */ + unavailable_features =3D (requested_features & ~host_feat) & + ~INTEL_PT_ADDR_RANGES_NUM_MASK; + /* Bits 2:0 are as a whole to represent INTEL_PT_ADDR_RANGES */ + if ((requested_features & INTEL_PT_ADDR_RANGES_NUM_MASK) > + (host_feat & INTEL_PT_ADDR_RANGES_NUM_MASK)) { + unavailable_features |=3D requested_features & + INTEL_PT_ADDR_RANGES_NUM_MASK; + } + break; + default: + unavailable_features =3D requested_features & ~host_feat; + break; + } + mark_unavailable_features(cpu, w, unavailable_features, prefix); } =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a21..d8b3535d5aa7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -617,7 +617,10 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_14_0_EBX, FEAT_14_0_ECX, + FEAT_14_1_EAX, + FEAT_14_1_EBX, FEAT_SGX_12_0_EAX, /* CPUID[EAX=3D0x12,ECX=3D0].EAX (SGX) */ FEAT_SGX_12_0_EBX, /* CPUID[EAX=3D0x12,ECX=3D0].EBX (SGX MISCSELECT[3= 1:0]) */ FEAT_SGX_12_1_EAX, /* CPUID[EAX=3D0x12,ECX=3D1].EAX (SGX ATTRIBUTES[3= 1:0]) */ --=20 2.27.0