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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Ani Sinha , Jiaxun Yang , Bernhard Beschow Subject: [PATCH 15/32] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Date: Sun, 4 Dec 2022 20:05:36 +0100 Message-Id: <20221204190553.3274-16-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221204190553.3274-1-shentey@gmail.com> References: <20221204190553.3274-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1670181083269100001 Content-Type: text/plain; charset="utf-8" PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise inconsistencies can occur. Signed-off-by: Bernhard Beschow Message-Id: <20221022150508.26830-21-shentey@gmail.com> --- hw/isa/piix3.c | 8 ++++---- include/hw/southbridge/piix.h | 5 ++--- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 0341284199..7ee706243a 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix= 3, int pirq, int level) uint64_t mask; =20 pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { + if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 @@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pi= rq, int level) int pic_irq; =20 pic_irq =3D piix3->dev.config[PIIX_PIRQCA + pirq]; - if (pic_irq >=3D PIIX_NUM_PIC_IRQS) { + if (pic_irq >=3D ISA_NUM_IRQS) { return; } =20 @@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opa= que, int pin) int irq =3D piix3->dev.config[PIIX_PIRQCA + pin]; PCIINTxRoute route; =20 - if (irq < PIIX_NUM_PIC_IRQS) { + if (irq < ISA_NUM_IRQS) { route.mode =3D PCI_INTX_ENABLED; route.irq =3D irq; } else { @@ -130,7 +130,7 @@ static void piix3_write_config(PCIDevice *dev, =20 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev)); piix3_update_irq_levels(piix3); - for (pic_irq =3D 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { + for (pic_irq =3D 0; pic_irq < ISA_NUM_IRQS; pic_irq++) { piix3_set_irq_pic(piix3, pic_irq); } } diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index c4e6e9f827..39c31da9ad 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -32,7 +32,6 @@ */ #define PIIX_RCR_IOPORT 0xcf9 =20 -#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ =20 struct PIIXState { @@ -44,10 +43,10 @@ struct PIIXState { * So one PIC level is tracked by PIIX_NUM_PIRQS bits. * * PIRQ is mapped to PIC pins, we track it by - * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS =3D 64 bits with + * PIIX_NUM_PIRQS * ISA_NUM_IRQS =3D 64 bits with * pic_irq * PIIX_NUM_PIRQS + pirq */ -#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 +#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64 #error "unable to encode pic state in 64bit in pic_levels." #endif uint64_t pic_levels; --=20 2.38.1