From nobody Mon Feb 9 20:32:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1670109702; cv=none; d=zohomail.com; s=zohoarc; b=FN9VDZOFimH6sHlWV/sXUCJYbja79QjW7ypu+mhwI2Ocyn6WcdOa/D+RXhMaYSs/TKq+YdkVsL8mh9zFADTKCj2thG7mgLocMRYdbHfA3fgkpldINDgRQTh7KzXxxwIcVUloZLnqlXiO76JJKAuRnnMVsKdFP1okQGuwxlfcqQI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1670109702; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OwV0IdsvFUwiwgonjdaaaLXb1o1stWZ7D+ZfqdOotso=; b=dFPMONptcPASuVwybLZTqiNtyf3oPszVEVFtCJ0cZKnxmkKz1ci/yvPUmNp+zkV19Gq5CH3U8ejaexfneNUEUZGxAPGHpcVo/hwcDG16A0zjgB6nZ58YkFa16nnJzcLvp2U2cVrrtzqrl8qv1lgco8cZ6W8QsmtJqEA543F1QC0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1670109702792621.1502243020058; Sat, 3 Dec 2022 15:21:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p1bnL-00006l-LY; Sat, 03 Dec 2022 18:19:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p1bnJ-000050-Li; Sat, 03 Dec 2022 18:19:41 -0500 Received: from mail-lj1-x22e.google.com ([2a00:1450:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p1bnE-0001Zp-2w; Sat, 03 Dec 2022 18:19:41 -0500 Received: by mail-lj1-x22e.google.com with SMTP id z24so9415794ljn.4; Sat, 03 Dec 2022 15:19:35 -0800 (PST) Received: from penguin.lxd (213-67-202-254-no43.tbcn.telia.com. [213.67.202.254]) by smtp.googlemail.com with ESMTPSA id b27-20020a05651c033b00b002770e6c620bsm22623ljp.106.2022.12.03.15.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Dec 2022 15:19:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OwV0IdsvFUwiwgonjdaaaLXb1o1stWZ7D+ZfqdOotso=; b=DfNyQFZDAacO/eEk9RCnkYagW3UuKBOK7L+EIdeL1DxIjGPswjub5mXjmW0gDjEwvq CQCqpFMXpVktK6I/TzzFRfkYorT5HRHfIjIlCx3P3FZu320fJ8Sy/TprnTfATTCDeY9w t6EIx2fAMBd/BVVLJK4fUdtjL7VrbEq6of/IWk+bAZfVERFjIM2tlaYhKbg8X6zJVOco O9/Umyd8zfRdUaj7AxMyHtnSZaod9p/NapkFVzhvqYrpdHLpiVFlGPscwW+cg2F7AV0d QmKNXK61AShj+CD2nhvxkV5sL8rotYnsGDjm2PLVn4EMC+LaYlIuLTLQTNJ9mv59nS1e mXIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OwV0IdsvFUwiwgonjdaaaLXb1o1stWZ7D+ZfqdOotso=; b=bb8lakH8V/1qF8D7RlJbA4vJfcOkOheoTCa7ZDx1CFir/W1JJLUH06yONTT2Fi/gwI t56NLp7JVkvlusiwFkOhvmDjTl16CDgglIppyldnmT5JMxpDryzgCHRP/cJiqDM5KQ5H u8wHnziHvcc8Aa+QTObMejsd4XcIwh5EXJ/UYaYpsgPvnfvftvkoSfVKxrcT8/T+4Kls wWarcWatsZ5tAwLcwk2xz5Mi34CIVH7TI4+CD3x9+avJgpDhVYxJJPlL9D/nSl4l5bTR bL80nb+DZ5JMIOMrkm3bLIotXfiV0Ef4W1d5WElIi7pVgZBmSiv5YkPI587DLH0F6wGM ncHw== X-Gm-Message-State: ANoB5pk9d6MfosfzjvLQLXESKPG3gC+eUBAVb0FxHhhNFEi8HYi7uEfL RbBZGzZSo710JCp2d7ZjbC8= X-Google-Smtp-Source: AA0mqf4GPTZCd7c/tbfjFbXvL6lcZUflF3jLynX1e/eVz0c50GCUpfZ9qYzBQIIsxVnly0rrsjAv+A== X-Received: by 2002:a2e:6812:0:b0:279:4159:ab79 with SMTP id c18-20020a2e6812000000b002794159ab79mr19974345lja.144.1670109574001; Sat, 03 Dec 2022 15:19:34 -0800 (PST) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: Peter Maydell Cc: Beniamino Galvani , Niek Linnenbank , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Strahinja Jankovic Subject: [PATCH 4/6] hw/misc: Allwinner AXP-209 Emulation Date: Sun, 4 Dec 2022 00:19:02 +0100 Message-Id: <20221203231904.25155-5-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221203231904.25155-1-strahinja.p.jankovic@gmail.com> References: <20221203231904.25155-1-strahinja.p.jankovic@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22e; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lj1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1670109703593100005 Content-Type: text/plain; charset="utf-8" This patch adds minimal support for AXP-209 PMU. Most important is chip ID since U-Boot SPL expects version 0x1. Besides the chip ID register, reset values for two more registers used by A10 U-Boot SPL are covered. Signed-off-by: Strahinja Jankovic --- hw/arm/Kconfig | 1 + hw/misc/Kconfig | 4 + hw/misc/allwinner-axp-209.c | 263 ++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 4 files changed, 269 insertions(+) create mode 100644 hw/misc/allwinner-axp-209.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index eefe1fd134..67c6e83fe6 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -323,6 +323,7 @@ config ALLWINNER_A10 select ALLWINNER_A10_DRAMC select ALLWINNER_EMAC select ALLWINNER_I2C + select ALLWINNER_AXP_209 select SERIAL select UNIMP =20 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 052fb54310..3855d937fd 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -180,4 +180,8 @@ config ALLWINNER_A10_CCM config ALLWINNER_A10_DRAMC bool =20 +config ALLWINNER_AXP_209 + bool + depends on I2C + source macio/Kconfig diff --git a/hw/misc/allwinner-axp-209.c b/hw/misc/allwinner-axp-209.c new file mode 100644 index 0000000000..229e3961b6 --- /dev/null +++ b/hw/misc/allwinner-axp-209.c @@ -0,0 +1,263 @@ +/* + * AXP-209 Emulation + * + * Written by Strahinja Jankovic + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software= "), + * to deal in the Software without restriction, including without limitati= on + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL= THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/i2c/i2c.h" +#include "migration/vmstate.h" + +#ifndef AXP_209_ERR_DEBUG +#define AXP_209_ERR_DEBUG 0 +#endif + +#define TYPE_AXP_209 "allwinner.axp209" + +#define AXP_209(obj) \ + OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP_209) + +#define DB_PRINT(fmt, args...) do { \ + if (AXP_209_ERR_DEBUG) { \ + fprintf(stderr, "%s: " fmt, __func__, ## args); \ + } \ +} while (0) + +/* registers */ +enum { + REG_POWER_STATUS =3D 0x0u, + REG_OPERATING_MODE, + REG_OTG_VBUS_STATUS, + REG_CHIP_VERSION, + REG_DATA_CACHE_0, + REG_DATA_CACHE_1, + REG_DATA_CACHE_2, + REG_DATA_CACHE_3, + REG_DATA_CACHE_4, + REG_DATA_CACHE_5, + REG_DATA_CACHE_6, + REG_DATA_CACHE_7, + REG_DATA_CACHE_8, + REG_DATA_CACHE_9, + REG_DATA_CACHE_A, + REG_DATA_CACHE_B, + REG_POWER_OUTPUT_CTRL =3D 0x12u, + REG_DC_DC2_OUT_V_CTRL =3D 0x23u, + REG_DC_DC2_DVS_CTRL =3D 0x25u, + REG_DC_DC3_OUT_V_CTRL =3D 0x27u, + REG_LDO2_4_OUT_V_CTRL, + REG_LDO3_OUT_V_CTRL, + REG_VBUS_CH_MGMT =3D 0x30u, + REG_SHUTDOWN_V_CTRL, + REG_SHUTDOWN_CTRL, + REG_CHARGE_CTRL_1, + REG_CHARGE_CTRL_2, + REG_SPARE_CHARGE_CTRL, + REG_PEK_KEY_CTRL, + REG_DC_DC_FREQ_SET, + REG_CHR_TEMP_TH_SET, + REG_CHR_HIGH_TEMP_TH_CTRL, + REG_IPSOUT_WARN_L1, + REG_IPSOUT_WARN_L2, + REG_DISCHR_TEMP_TH_SET, + REG_DISCHR_HIGH_TEMP_TH_CTRL, + REG_IRQ_BANK_1_CTRL =3D 0x40u, + REG_IRQ_BANK_2_CTRL, + REG_IRQ_BANK_3_CTRL, + REG_IRQ_BANK_4_CTRL, + REG_IRQ_BANK_5_CTRL, + REG_IRQ_BANK_1_STAT =3D 0x48u, + REG_IRQ_BANK_2_STAT, + REG_IRQ_BANK_3_STAT, + REG_IRQ_BANK_4_STAT, + REG_IRQ_BANK_5_STAT, + REG_ADC_ACIN_V_H =3D 0x56u, + REG_ADC_ACIN_V_L, + REG_ADC_ACIN_CURR_H, + REG_ADC_ACIN_CURR_L, + REG_ADC_VBUS_V_H, + REG_ADC_VBUS_V_L, + REG_ADC_VBUS_CURR_H, + REG_ADC_VBUS_CURR_L, + REG_ADC_INT_TEMP_H, + REG_ADC_INT_TEMP_L, + REG_ADC_TEMP_SENS_V_H =3D 0x62u, + REG_ADC_TEMP_SENS_V_L, + REG_ADC_BAT_V_H =3D 0x78u, + REG_ADC_BAT_V_L, + REG_ADC_BAT_DISCHR_CURR_H, + REG_ADC_BAT_DISCHR_CURR_L, + REG_ADC_BAT_CHR_CURR_H, + REG_ADC_BAT_CHR_CURR_L, + REG_ADC_IPSOUT_V_H, + REG_ADC_IPSOUT_V_L, + REG_DC_DC_MOD_SEL =3D 0x80u, + REG_ADC_EN_1, + REG_ADC_EN_2, + REG_ADC_SR_CTRL, + REG_ADC_IN_RANGE, + REG_GPIO1_ADC_IRQ_RISING_TH, + REG_GPIO1_ADC_IRQ_FALLING_TH, + REG_TIMER_CTRL =3D 0x8au, + REG_VBUS_CTRL_MON_SRP, + REG_OVER_TEMP_SHUTDOWN =3D 0x8fu, + REG_GPIO0_FEAT_SET, + REG_GPIO_OUT_HIGH_SET, + REG_GPIO1_FEAT_SET, + REG_GPIO2_FEAT_SET, + REG_GPIO_SIG_STATE_SET_MON, + REG_GPIO3_SET, + REG_COULOMB_CNTR_CTRL =3D 0xb8u, + REG_POWER_MEAS_RES, + NR_REGS +}; + +#define AXP_209_CHIP_VERSION_ID (0x01) +#define AXP_209_DC_DC2_OUT_V_CTRL_RESET (0x16) +#define AXP_209_IRQ_BANK_1_CTRL_RESET (0xd8) + +/* A simple I2C slave which returns values of ID or CNT register. */ +typedef struct AXP209I2CState { + /*< private >*/ + I2CSlave i2c; + /*< public >*/ + uint8_t regs[NR_REGS]; /* peripheral registers */ + uint8_t ptr; /* current register index */ + uint8_t count; /* counter used for tx/rx */ +} AXP209I2CState; + +/* Reset all counters and load ID register */ +static void axp_209_reset_enter(Object *obj, ResetType type) +{ + AXP209I2CState *s =3D AXP_209(obj); + + memset(s->regs, 0, NR_REGS); + s->ptr =3D 0; + s->count =3D 0; + s->regs[REG_CHIP_VERSION] =3D AXP_209_CHIP_VERSION_ID; + s->regs[REG_DC_DC2_OUT_V_CTRL] =3D AXP_209_DC_DC2_OUT_V_CTRL_RESET; + s->regs[REG_IRQ_BANK_1_CTRL] =3D AXP_209_IRQ_BANK_1_CTRL_RESET; +} + +/* Handle events from master. */ +static int axp_209_event(I2CSlave *i2c, enum i2c_event event) +{ + AXP209I2CState *s =3D AXP_209(i2c); + + s->count =3D 0; + + return 0; +} + +/* Called when master requests read */ +static uint8_t axp_209_rx(I2CSlave *i2c) +{ + AXP209I2CState *s =3D AXP_209(i2c); + uint8_t ret =3D 0xff; + + if (s->ptr < NR_REGS) { + ret =3D s->regs[s->ptr++]; + } + + DB_PRINT("Reading from %d : %d\n", s->ptr - 1, ret); + + return ret; +} + +/* + * Called when master sends write. + * Update ptr with byte 0, then perform write with second byte. + */ +static int axp_209_tx(I2CSlave *i2c, uint8_t data) +{ + AXP209I2CState *s =3D AXP_209(i2c); + + if (s->count =3D=3D 0) { + /* Store register address */ + s->ptr =3D data; + s->count++; + DB_PRINT("Register to access %d\n", data); + } else { + DB_PRINT("Writing to register %d : %d\n", s->ptr, data); + if (s->ptr =3D=3D REG_DC_DC2_OUT_V_CTRL) { + s->regs[s->ptr++] =3D data; + } + } + + return 0; +} + +/* Initialization */ +static void axp_209_init(Object *obj) +{ + AXP209I2CState *s =3D AXP_209(obj); + + s->count =3D 0; + s->ptr =3D 0; + memset(s->regs, 0, NR_REGS); + s->regs[REG_CHIP_VERSION] =3D AXP_209_CHIP_VERSION_ID; + s->regs[REG_DC_DC2_OUT_V_CTRL] =3D 0x16; + s->regs[REG_IRQ_BANK_1_CTRL] =3D 0xd8; + + DB_PRINT("INIT AXP209\n"); + + return; +} + +static const VMStateDescription vmstate_axp_209 =3D { + .name =3D TYPE_AXP_209, + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS), + VMSTATE_UINT8(count, AXP209I2CState), + VMSTATE_UINT8(ptr, AXP209I2CState), + VMSTATE_END_OF_LIST() + } +}; + +static void axp_209_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + I2CSlaveClass *isc =3D I2C_SLAVE_CLASS(oc); + ResettableClass *rc =3D RESETTABLE_CLASS(oc); + + rc->phases.enter =3D axp_209_reset_enter; + dc->vmsd =3D &vmstate_axp_209; + isc->event =3D axp_209_event; + isc->recv =3D axp_209_rx; + isc->send =3D axp_209_tx; +} + +static const TypeInfo axp_209_info =3D { + .name =3D TYPE_AXP_209, + .parent =3D TYPE_I2C_SLAVE, + .instance_size =3D sizeof(AXP209I2CState), + .instance_init =3D axp_209_init, + .class_init =3D axp_209_class_init +}; + +static void axp_209_register_devices(void) +{ + type_register_static(&axp_209_info); +} + +type_init(axp_209_register_devices); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index d7f49f0f81..c85a0127fe 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -40,6 +40,7 @@ softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: fi= les('ivshmem.c')) =20 softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner= -a10-ccm.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinn= er-a10-dramc.c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_AXP_209', if_true: files('allwinner= -axp-209.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-c= cu.c')) specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpu= cfg.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-d= ramc.c')) --=20 2.30.2