From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669963963; cv=none; d=zohomail.com; s=zohoarc; b=bcYp4qUoYEJmFXJlZpzqqRNdlUzbm4YHD/OG+lFhV5GPbfp349AFOPUsb1efmMEkquUKF2qjqjuCMNUa3TvqVlSipgREHXztg/ufkt5Ne78fNd/El2J18nbD3sfi5rq/LmP/f/jQmSXd+cL19OxEAoN0a42/LHnoP2hthvcp8NA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669963963; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UrI6q1gXGjCLU/ugzjf2mM2L+vv/WF4h7OD1AmvhVf4=; b=TL69uH+9PQLICjXzSxoyBthEp3d2phkXIR3hxBjf+y4a/3UbT2p9YknepFev9RKNQ61Q9Q882sbE+TaiT46O5hwaxxImyIXFgvdWu0LpihDLS667HNyzAMXe1EDeSftnMm8ZvYGr2dG3p8Yf6QVN14WA9zq7bOgpI9ej/sB6wZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669963963506275.39928047026694; Thu, 1 Dec 2022 22:52:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zu4-0007YR-L6; Fri, 02 Dec 2022 01:52:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zu2-0007Y0-P1 for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:06 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu0-0003dF-SP for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:06 -0500 Received: by mail-pf1-x431.google.com with SMTP id l127so3448550pfl.2 for ; Thu, 01 Dec 2022 22:52:03 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UrI6q1gXGjCLU/ugzjf2mM2L+vv/WF4h7OD1AmvhVf4=; b=EXFSyKS+duHe4AOyVBPq4qLyR53xR0oZpnOHWRZeFTwwdIK/ipUzmco4ynwVNWh8Qa mGEowMyrht7S/ulGOPF9xqjZqZQAv0IQ1G/2lPmcODM2PUgNCdpl0oW2OlKPpQfUcbzQ M6vWe6m4HW1qyynqlju6IB9aBAwJPoVJyWc6tmaaIbJD/tvRtwHJ7exsmQHtSyQu5A1+ NNawneC9nB4G7xQNpK+L1PULP2KznpVSJ5ayK0sQF6CDqrMyM2D5UKb1+L3P7BdbSL5s w61dKKhHCv2enBxljqTTUy2vWdURVxsw/c5s530B3MiHR0nlbywEVjKtP3lz+eTGd3rv 0egA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UrI6q1gXGjCLU/ugzjf2mM2L+vv/WF4h7OD1AmvhVf4=; b=aRJMWDcf5l9PTh2O84gfXRYs0GlQEThVk281eYDn74kcPLCyMfG/hk8G1URR22asgG LgqJAMxAkYooLQCeUxFWv6Lrv4+EaeyjTOx1bghT86h09x7vTrDU5Fr6RoUPjG6VZJVL LyRY5FAatrhTw3SbCwjSkkyd+ro0F9E0Q0LSywsOXMhMKZAr8ypyfTS3zFu4j8zYCl23 qsG8N8NDLqai6qcyoCeV//SxUsZ5YGGCjywwzlHiOK3Ig79vauI6ycDhzYaQLtjowTgm By2OIMlEVZoQ1X11LF0wFh8T69FgDdfudNFFefrGW7iywqcT3fYahhqKEr/dL6jcMozy WKNg== X-Gm-Message-State: ANoB5pmSLXkKFwM0EMnRH/j2tvO48g+45pZef9IP0WxjVJGpaOnMzIGv sQn0zfm2cC+HRKZDgmMlLMLPeoSL4e+6+eCi X-Google-Smtp-Source: AA0mqf7eqw3jDX4lPiM5PXXFNDymRw8rqQ+3mDnZjtiEaJFcljVIqok/Q3hOVqONf8LAlRqUJDeSNg== X-Received: by 2002:a63:2584:0:b0:478:5d6b:d1fd with SMTP id l126-20020a632584000000b004785d6bd1fdmr9910494pgl.249.1669963922633; Thu, 01 Dec 2022 22:52:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 01/13] tcg/s390x: Use register pair allocation for div and mulu2 Date: Thu, 1 Dec 2022 22:51:48 -0800 Message-Id: <20221202065200.224537-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669963965855100003 Content-Type: text/plain; charset="utf-8" Previously we hard-coded R2 and R3. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target-con-set.h | 4 ++-- tcg/s390x/tcg-target-con-str.h | 8 +------ tcg/s390x/tcg-target.c.inc | 43 +++++++++++++++++++++++++--------- 3 files changed, 35 insertions(+), 20 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 426dd92e51..00ba727b70 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -29,8 +29,8 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) -C_O2_I2(b, a, 0, r) -C_O2_I3(b, a, 0, 1, r) +C_O2_I2(o, m, 0, r) +C_O2_I3(o, m, 0, 1, r) C_O2_I4(r, r, 0, 1, rA, r) C_O2_I4(r, r, 0, 1, ri, r) C_O2_I4(r, r, 0, 1, r, r) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 8bb0358ae5..76446aecae 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -11,13 +11,7 @@ REGS('r', ALL_GENERAL_REGS) REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) -/* - * A (single) even/odd pair for division. - * TODO: Add something to the register allocator to allow - * this kind of regno+1 pairing to be done more generally. - */ -REGS('a', 1u << TCG_REG_R2) -REGS('b', 1u << TCG_REG_R3) +REGS('o', 0xaaaa) /* odd numbered general regs */ =20 /* * Define constraint letters for constants: diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b9ba7b605e..cb00bb6999 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2264,10 +2264,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_div2_i32: - tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); + tcg_debug_assert(args[0] =3D=3D args[2]); + tcg_debug_assert(args[1] =3D=3D args[3]); + tcg_debug_assert((args[1] & 1) =3D=3D 0); + tcg_debug_assert(args[0] =3D=3D args[1] + 1); + tcg_out_insn(s, RR, DR, args[1], args[4]); break; case INDEX_op_divu2_i32: - tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); + tcg_debug_assert(args[0] =3D=3D args[2]); + tcg_debug_assert(args[1] =3D=3D args[3]); + tcg_debug_assert((args[1] & 1) =3D=3D 0); + tcg_debug_assert(args[0] =3D=3D args[1] + 1); + tcg_out_insn(s, RRE, DLR, args[1], args[4]); break; =20 case INDEX_op_shl_i32: @@ -2521,17 +2529,30 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_div2_i64: - /* ??? We get an unnecessary sign-extension of the dividend - into R3 with this definition, but as we do in fact always - produce both quotient and remainder using INDEX_op_div_i64 - instead requires jumping through even more hoops. */ - tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); + /* + * ??? We get an unnecessary sign-extension of the dividend + * into op0 with this definition, but as we do in fact always + * produce both quotient and remainder using INDEX_op_div_i64 + * instead requires jumping through even more hoops. + */ + tcg_debug_assert(args[0] =3D=3D args[2]); + tcg_debug_assert(args[1] =3D=3D args[3]); + tcg_debug_assert((args[1] & 1) =3D=3D 0); + tcg_debug_assert(args[0] =3D=3D args[1] + 1); + tcg_out_insn(s, RRE, DSGR, args[1], args[4]); break; case INDEX_op_divu2_i64: - tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); + tcg_debug_assert(args[0] =3D=3D args[2]); + tcg_debug_assert(args[1] =3D=3D args[3]); + tcg_debug_assert((args[1] & 1) =3D=3D 0); + tcg_debug_assert(args[0] =3D=3D args[1] + 1); + tcg_out_insn(s, RRE, DLGR, args[1], args[4]); break; case INDEX_op_mulu2_i64: - tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]); + tcg_debug_assert(args[0] =3D=3D args[2]); + tcg_debug_assert((args[1] & 1) =3D=3D 0); + tcg_debug_assert(args[0] =3D=3D args[1] + 1); + tcg_out_insn(s, RRE, MLGR, args[1], args[3]); break; =20 case INDEX_op_shl_i64: @@ -3226,10 +3247,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_div2_i64: case INDEX_op_divu2_i32: case INDEX_op_divu2_i64: - return C_O2_I3(b, a, 0, 1, r); + return C_O2_I3(o, m, 0, 1, r); =20 case INDEX_op_mulu2_i64: - return C_O2_I2(b, a, 0, r); + return C_O2_I2(o, m, 0, r); =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964108; cv=none; d=zohomail.com; s=zohoarc; b=OXZKjUvSQNIUSK35xPFIWY/zvWJfY8079WvGbwanZBCrYbVKmwbHbvEXrkoPTWBAuzNpmWz8c+bGk+G2NE3CaFiXR1GbWpJrTSBxPGL4sHxjemLfiwprkFXwtu3wfiC+4TIYTcSYQt1JDPzJCO5yg2GZLgZNtnSYb5AMAMexLgY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964108; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vkxAHU1OpV8djiv/f6/tmq1e3ZfaO5uGqO8j36dYmss=; b=eRxNrTuHGlU+Xhg/CdYNWFkOT7ZPc9OFFWl7hkDsaAJS/dOMVlsh3I1O22xQxenKfDGpfLkWmgudSOrXO6RjRLNiviX1dkUVk4Wmjq0JutuV/gVzMDSCi5OF3FtNs64dEVLL4MgIrUz2DYi9VkrbO2BV8FYJK2hQQOflnxsnoo4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964108794526.5357632036065; Thu, 1 Dec 2022 22:55:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zu6-0007ZI-9J; Fri, 02 Dec 2022 01:52:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zu4-0007YO-DU for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:08 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu1-0003ec-FA for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:08 -0500 Received: by mail-pl1-x630.google.com with SMTP id y4so3841683plb.2 for ; Thu, 01 Dec 2022 22:52:04 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vkxAHU1OpV8djiv/f6/tmq1e3ZfaO5uGqO8j36dYmss=; b=yqFXIgdtJESf6rmW8QTMI+rFj4EfVw9niTSw0LsBbkfFClcG9NRsTVKqQawT55rehM H6NEKoH0tgCEWVu5T02Z/035eBcE4MRbBAJN8Kf+YOpyZNZaWg0pvtmVFgXSPSBu4EuI x7Ez+zg+8MVy1KUMcwH7ZymgBi4fehj2j9zrNc2Et1foODQF/kIJkX1rfChg07OKsWgl 1yLBOLfJOLSK7htc9gLLKSGk+RTT941ERHLIQrtvPjmCgzoYpJ+c+Wto+O7Q18oK6hR5 XOtT+Lt0yGJfNGPb2oYFeJyivH7NCoFTsn264ZKwOZsyLRpnQA54SrrxsBNlAyT7xryw a2vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vkxAHU1OpV8djiv/f6/tmq1e3ZfaO5uGqO8j36dYmss=; b=chAtFrK2vCtoY3c5YzKhuD6wDThl2G5tVqbiQJo9AgINyo4K7uy9O/LWKmaX6DTD4n jKsGHSoOpjdplppHGo4PNYMJwR0xmZ8/KDbb4GYuLTT/WQDWIAe5OcU89I5fz+jhrVV4 4UGbCb3T4EfnKiIgVVR7Jr7wnq+7V68/cmsgyDwQZQLBd+RNAUMTxkBSzbUokGxqcyqe h6o3EcTQGmVAm+tKhmn7T36FIIs5DnJ2KtQbklxNTx8zL4n0wNC6lOrl3NTfJxaEm3Ur h28pUsPREYJkLH72UnS/e2ayLD31pua7Ou1IezjhKUpurjiB3xu7zuxEct91lQQW7CSp yjNw== X-Gm-Message-State: ANoB5pkRTsDTgSx792zpu1k0O7feQNnZddySi20Q06lJkhYx40gNEW5v Rwck/xYJgTFFuUs5eeZwdx+cOATkcqO5SZud X-Google-Smtp-Source: AA0mqf6yTWz1MIYyZEUcta+K93ZtlhnbN736J7bkkrs1RGOi+T5i0NI0Yg8SKX4+69GrWN9smtXrOA== X-Received: by 2002:a17:902:8d93:b0:17f:8042:7223 with SMTP id v19-20020a1709028d9300b0017f80427223mr56338393plo.38.1669963923649; Thu, 01 Dec 2022 22:52:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 02/13] tcg/s390x: Remove TCG_REG_TB Date: Thu, 1 Dec 2022 22:51:49 -0800 Message-Id: <20221202065200.224537-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964110433100003 Content-Type: text/plain; charset="utf-8" This reverts 829e1376d940 ("tcg/s390: Introduce TCG_REG_TB"), and several follow-up patches. The primary motivation is to reduce the less-tested code paths, pre-z10. Secondarily, this allows the unconditional use of TCG_TARGET_HAS_direct_jump, which might be more important for performance than any slight increase in code size. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 176 +++++-------------------------------- 2 files changed, 23 insertions(+), 155 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 22d70d431b..645f522058 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -103,7 +103,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_direct_jump 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 #define TCG_TARGET_HAS_div2_i64 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index cb00bb6999..8a4bec0a28 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -65,12 +65,6 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 =20 -/* A scratch register that holds a pointer to the beginning of the TB. - We don't need this when we have pc-relative loads with the general - instructions extension facility. */ -#define TCG_REG_TB TCG_REG_R12 -#define USE_REG_TB (!HAVE_FACILITY(GEN_INST_EXT)) - #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 #endif @@ -813,8 +807,8 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType= type, } =20 /* load a register with an immediate value */ -static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long sval, bool in_prologue) +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) { tcg_target_ulong uval; =20 @@ -853,14 +847,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, tcg_out_insn(s, RIL, LARL, ret, off); return; } - } else if (USE_REG_TB && !in_prologue) { - ptrdiff_t off =3D tcg_tbrel_diff(s, (void *)sval); - if (off =3D=3D sextract64(off, 0, 20)) { - /* This is certain to be an address within TB, and therefore - OFF will be negative; don't try RX_LA. */ - tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); - return; - } } =20 /* A 32-bit unsigned value can be loaded in 2 insns. And given @@ -876,10 +862,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, if (HAVE_FACILITY(GEN_INST_EXT)) { tcg_out_insn(s, RIL, LGRL, ret, 0); new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); - } else if (USE_REG_TB && !in_prologue) { - tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, sval, R_390_20, s->code_ptr - 2, - tcg_tbrel_diff(s, NULL)); } else { TCGReg base =3D ret ? ret : TCG_TMP0; tcg_out_insn(s, RIL, LARL, base, 0); @@ -888,12 +870,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, } } =20 -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) -{ - tcg_out_movi_int(s, type, ret, sval, false); -} - /* Emit a load/store type instruction. Inputs are: DATA: The register to be loaded or stored. BASE+OFS: The effective address. @@ -1020,35 +996,6 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType= type, TCGArg val, return false; } =20 -/* load data from an absolute host address */ -static void tcg_out_ld_abs(TCGContext *s, TCGType type, - TCGReg dest, const void *abs) -{ - intptr_t addr =3D (intptr_t)abs; - - if (HAVE_FACILITY(GEN_INST_EXT) && !(addr & 1)) { - ptrdiff_t disp =3D tcg_pcrel_diff(s, abs) >> 1; - if (disp =3D=3D (int32_t)disp) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, LRL, dest, disp); - } else { - tcg_out_insn(s, RIL, LGRL, dest, disp); - } - return; - } - } - if (USE_REG_TB) { - ptrdiff_t disp =3D tcg_tbrel_diff(s, abs); - if (disp =3D=3D sextract64(disp, 0, 20)) { - tcg_out_ld(s, type, dest, TCG_REG_TB, disp); - return; - } - } - - tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); - tcg_out_ld(s, type, dest, dest, addr & 0xffff); -} - static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, int msb, int lsb, int ofs, int z) { @@ -1243,17 +1190,7 @@ static void tgen_andi(TCGContext *s, TCGType type, T= CGReg dest, uint64_t val) return; } =20 - /* Use the constant pool if USE_REG_TB, but not for small constants. = */ - if (USE_REG_TB) { - if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { - tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, - tcg_tbrel_diff(s, NULL)); - return; - } - } else { - tcg_out_movi(s, type, TCG_TMP0, val); - } + tcg_out_movi(s, type, TCG_TMP0, val); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RR, NR, dest, TCG_TMP0); } else { @@ -1297,24 +1234,11 @@ static void tgen_ori(TCGContext *s, TCGType type, T= CGReg dest, uint64_t val) } } =20 - /* Use the constant pool if USE_REG_TB, but not for small constants. = */ - if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, OR, dest, TCG_TMP0); - } else { - tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); - } - } else if (USE_REG_TB) { - tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, val, R_390_20, s->code_ptr - 2, - tcg_tbrel_diff(s, NULL)); + tcg_out_movi(s, type, TCG_TMP0, val); + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RR, OR, dest, TCG_TMP0); } else { - /* Perform the OR via sequential modifications to the high and - low parts. Do this via recursion to handle 16-bit vs 32-bit - masks in each half. */ - tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); - tgen_ori(s, type, dest, val & 0x00000000ffffffffull); - tgen_ori(s, type, dest, val & 0xffffffff00000000ull); + tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); } } =20 @@ -1332,26 +1256,11 @@ static void tgen_xori(TCGContext *s, TCGType type, = TCGReg dest, uint64_t val) } } =20 - /* Use the constant pool if USE_REG_TB, but not for small constants. = */ - if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, XR, dest, TCG_TMP0); - } else { - tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0); - } - } else if (USE_REG_TB) { - tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, val, R_390_20, s->code_ptr - 2, - tcg_tbrel_diff(s, NULL)); + tcg_out_movi(s, type, TCG_TMP0, val); + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RR, XR, dest, TCG_TMP0); } else { - /* Perform the xor by parts. */ - tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); - if (val & 0xffffffff) { - tcg_out_insn(s, RIL, XILF, dest, val); - } - if (val > 0xffffffff) { - tcg_out_insn(s, RIL, XIHF, dest, val >> 32); - } + tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0); } } =20 @@ -1395,19 +1304,6 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCG= Cond c, TCGReg r1, if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) { c2 =3D TCG_TMP0; /* fall through to reg-reg */ - } else if (USE_REG_TB) { - if (type =3D=3D TCG_TYPE_I32) { - op =3D (is_unsigned ? RXY_CLY : RXY_CY); - tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, - 4 - tcg_tbrel_diff(s, NULL)); - } else { - op =3D (is_unsigned ? RXY_CLG : RXY_CG); - tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, c2, R_390_20, s->code_ptr - 2, - tcg_tbrel_diff(s, NULL)); - } - goto exit; } else { if (type =3D=3D TCG_TYPE_I32) { op =3D (is_unsigned ? RIL_CLRL : RIL_CRL); @@ -2101,43 +1997,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 case INDEX_op_goto_tb: a0 =3D args[0]; - if (s->tb_jmp_insn_offset) { - /* - * branch displacement must be aligned for atomic patching; - * see if we need to add extra nop before branch - */ - if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { - tcg_out16(s, NOP); - } - tcg_debug_assert(!USE_REG_TB); - tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - s->code_ptr +=3D 2; - } else { - /* load address stored at s->tb_jmp_target_addr + a0 */ - tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, - tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0)); - /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); + tcg_debug_assert(s->tb_jmp_insn_offset); + /* + * branch displacement must be aligned for atomic patching; + * see if we need to add extra nop before branch + */ + if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { + tcg_out16(s, NOP); } + tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + tcg_out32(s, 0); set_jmp_reset_offset(s, a0); - - /* For the unlinked path of goto_tb, we need to reset - TCG_REG_TB to the beginning of this TB. */ - if (USE_REG_TB) { - int ofs =3D -tcg_current_code_size(s); - /* All TB are restricted to 64KiB by unwind info. */ - tcg_debug_assert(ofs =3D=3D sextract64(ofs, 0, 20)); - tcg_out_insn(s, RXY, LAY, TCG_REG_TB, - TCG_REG_TB, TCG_REG_NONE, ofs); - } break; =20 case INDEX_op_goto_ptr: a0 =3D args[0]; - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); - } tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); break; =20 @@ -3405,9 +3280,6 @@ static void tcg_target_init(TCGContext *s) /* XXX many insns can't be used with R0, so we better avoid it for now= */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); - if (USE_REG_TB) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); - } } =20 #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ @@ -3428,16 +3300,12 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base >=3D 0x80000) { - tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, - tcg_target_call_iarg_regs[1]); - } =20 /* br %r3 (go to TB) */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tv/8rjnBa1lQCKggJRD9/FDpkd6opAc1OcPOojf8ueg=; b=s/9SlTRAiHj+FLgJerGqkfrwBk63xbvPcrjzMGtdD1S12LzVZOwzOnCIYyQg4AC7On n+1ylS/y7XIehRF4Kw0JMQItLPFKlAl8oG1vjHf0g4WbnnAIW/i7XiKrnMP+Wpl9SsX2 b9Gp3SP5nJJ6VkHoDfXaFkvuaBNu0s+JMbMVQugc6AsHjtez8DpcfW19H5e7AZxgYilR zjHgy+7zA6wxXfrlJ55Gf9TjwGgMYvOzf6rzcj1hPmK1LzZ/rmENeXHEQ0nDZeWYHmng X9LlJYBNXvyIXOo7VvvNZonix+RiwhW/FzxvWKNUC/ZkuEaqSnvx7QKmcxxf+/88uoK3 IcEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tv/8rjnBa1lQCKggJRD9/FDpkd6opAc1OcPOojf8ueg=; b=5RY6UQ2gsmyoVu9n4R/z2CJoQF3iN/CX0uqx2FZvouK3cz1+QgIeNq7Cx9YG0MOw4s WnW56J9nonX77qjku9q9suI3HA/gxROIPqaZgovFlBE9o/LnVqPDiyvxa1T/xE6BOpug ari54IuaWuKikiJj1M0TEvzE7keU+GR60YUxfGVsxVR2WU7O1L7MJPBYt6QPu4qY6Lcz VYOvVqjSb8VXampEUlAw6fmXp5COHrYKlBAOjHbGRbABMYBXjz9N5wRJAXxKQY+NkybG 2qmHFIWmmEoQO7DFTfUinBuym13O0J60a/Ndo4G+SF9ZL01JO1MoZiv9R9FIMB8NZgpE Q55g== X-Gm-Message-State: ANoB5pk2cvbdyIazbB31bC8ULY9FjL6kDt9HvnG7Gy39DPG9DuVeOcUc dLlepxe3zdu25ZX1xDmDSP5Wz4IjWQ28r90L X-Google-Smtp-Source: AA0mqf6TJer94d44vMksMpCawa3bCb1kK25u5KIvOEjU5KLmIHRpwHanXFuzH3/yDJsXG6p8unv4KQ== X-Received: by 2002:a63:ec07:0:b0:470:90f1:6216 with SMTP id j7-20020a63ec07000000b0047090f16216mr62050623pgh.42.1669963924674; Thu, 01 Dec 2022 22:52:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 03/13] tcg/s390x: Use LARL+AGHI for odd addresses Date: Thu, 1 Dec 2022 22:51:50 -0800 Message-Id: <20221202065200.224537-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964289704100001 Content-Type: text/plain; charset="utf-8" Add one instead of dropping odd addresses to the constant pool. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.c.inc | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 8a4bec0a28..34de5c5ebe 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -811,6 +811,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long sval) { tcg_target_ulong uval; + ptrdiff_t pc_off; =20 /* Try all 32-bit insns that can load it in one go. */ if (maybe_out_small_movi(s, type, ret, sval)) { @@ -839,14 +840,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 - /* Try for PC-relative address load. For odd addresses, - attempt to use an offset from the start of the TB. */ - if ((sval & 1) =3D=3D 0) { - ptrdiff_t off =3D tcg_pcrel_diff(s, (void *)sval) >> 1; - if (off =3D=3D (int32_t)off) { - tcg_out_insn(s, RIL, LARL, ret, off); - return; + /* Try for PC-relative address load. For odd addresses, add one. */ + pc_off =3D tcg_pcrel_diff(s, (void *)sval) >> 1; + if (pc_off =3D=3D (int32_t)pc_off) { + tcg_out_insn(s, RIL, LARL, ret, pc_off); + if (sval & 1) { + tcg_out_insn(s, RI, AGHI, ret, 1); } + return; } =20 /* A 32-bit unsigned value can be loaded in 2 insns. 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([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v1xf2gNMoqab1oZCQR0m3ylYe6c4vcDw62EIKnNwJnY=; b=UVs7saXIuxyfE8d3opEcaFF9Ky0va9GyKzKNvK0K3xQPYFx84dJuPNDgB0+LfwZ0T0 H2CbHfBtpMpJdKSKtk2nFNymAGPSS2VTn+dXE9abhgLukt6aHYz4KtLO0er3s+Z0dyvn iFS978uOj69R4WxvuXo1Dr88NOjsWR2JcF3Agnng3HA8X9UvTYe2vlLevN8M7XZktrTg c6pA0qjkISmeBp5XpU+KhZ/S3JmCx/mMrb0mspV5/PtFkOLEd68vPp16w1JRfz80jabD +pEPJIV+Xdy/8uX/m6MGvLgcWa1YZSHrlAgg39ON+3dvFH4U9O+bTIBpQh0XnocxtWfz +gcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v1xf2gNMoqab1oZCQR0m3ylYe6c4vcDw62EIKnNwJnY=; b=wLS0Gy530IXlfbrdL0xCGv+xBB/JG1d9IszBLf0aotE3hy0LRvikIijzob/EP4Oa9D gWtyJq9QGf9ACA6fUVtpjVOXSe0o/HNUQ4qbpxZLVoO2GWtXb7HBrUlC89J82zn8jGk0 Jsnob95q8QuIY43AiTk9vHFwZ4iwkwJqTIhwT/jd81uCf7fV3NCDHdtRN41+Hpa7SGos wPASMtctfAcUqEca4S0TwHU6NuQPlnDmKlC/B8HNDZhSa0D1YkkhK0HquFZx6MWawCW0 cQtzIf5+hk3WsRRivXYBGMPXniJcrTrx05e2+9JvDx9K8pz7wszve0tHgMKCTcy39IBt QV/A== X-Gm-Message-State: ANoB5pl4rAJFr9i0KaQ4djIzNnBS5iwZsd7BXjNOjrlRv0cfR4d2f+pc bTpvJMV0E7pjD5pOgLGPIJip4cXMAM77HLd0 X-Google-Smtp-Source: AA0mqf7bclJrXdtpK8D1frDlBY94LYfchXK6aOUPAUZBzljvlerAcUn8Hu3DkekVxhELLWKbsrB9Jw== X-Received: by 2002:a63:e404:0:b0:477:f6be:b65b with SMTP id a4-20020a63e404000000b00477f6beb65bmr26864015pgi.362.1669963925635; Thu, 01 Dec 2022 22:52:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 04/13] tcg/s390x: Distinguish RRF-a and RRF-c formats Date: Thu, 1 Dec 2022 22:51:51 -0800 Message-Id: <20221202065200.224537-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964032047100002 Content-Type: text/plain; charset="utf-8" One has 3 register arguments; the other has 2 plus an m3 field. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.c.inc | 57 +++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 34de5c5ebe..a489b3359e 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -177,18 +177,19 @@ typedef enum S390Opcode { RRE_SLBGR =3D 0xb989, RRE_XGR =3D 0xb982, =20 - RRF_LOCR =3D 0xb9f2, - RRF_LOCGR =3D 0xb9e2, - RRF_NRK =3D 0xb9f4, - RRF_NGRK =3D 0xb9e4, - RRF_ORK =3D 0xb9f6, - RRF_OGRK =3D 0xb9e6, - RRF_SRK =3D 0xb9f9, - RRF_SGRK =3D 0xb9e9, - RRF_SLRK =3D 0xb9fb, - RRF_SLGRK =3D 0xb9eb, - RRF_XRK =3D 0xb9f7, - RRF_XGRK =3D 0xb9e7, + RRFa_NRK =3D 0xb9f4, + RRFa_NGRK =3D 0xb9e4, + RRFa_ORK =3D 0xb9f6, + RRFa_OGRK =3D 0xb9e6, + RRFa_SRK =3D 0xb9f9, + RRFa_SGRK =3D 0xb9e9, + RRFa_SLRK =3D 0xb9fb, + RRFa_SLGRK =3D 0xb9eb, + RRFa_XRK =3D 0xb9f7, + RRFa_XGRK =3D 0xb9e7, + + RRFc_LOCR =3D 0xb9f2, + RRFc_LOCGR =3D 0xb9e2, =20 RR_AR =3D 0x1a, RR_ALR =3D 0x1e, @@ -543,8 +544,14 @@ static void tcg_out_insn_RRE(TCGContext *s, S390Opcode= op, tcg_out32(s, (op << 16) | (r1 << 4) | r2); } =20 -static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op, - TCGReg r1, TCGReg r2, int m3) +static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, + TCGReg r1, TCGReg r2, TCGReg r3) +{ + tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); +} + +static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, + TCGReg r1, TCGReg r2, int m3) { tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2); } @@ -1419,7 +1426,7 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ tcg_out_movi(s, TCG_TYPE_I64, dest, 0); tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); } else { /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ tcg_out_movi(s, type, dest, 1); @@ -1438,7 +1445,7 @@ static void tgen_movcond(TCGContext *s, TCGType type,= TCGCond c, TCGReg dest, if (v3const) { tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); } else { - tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); + tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc); } } else { c =3D tcg_invert_cond(c); @@ -1468,7 +1475,7 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGR= eg a1, } if (HAVE_FACILITY(LOAD_ON_COND)) { /* Emit: if (one bit found) dest =3D r0. */ - tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); + tcg_out_insn(s, RRFc, LOCGR, dest, TCG_REG_R0, 2); } else { /* Emit: if (no one bit found) goto over; dest =3D r0; over: = */ tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1); @@ -2085,7 +2092,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, SR, a0, a2); } else { - tcg_out_insn(s, RRF, SRK, a0, a1, a2); + tcg_out_insn(s, RRFa, SRK, a0, a1, a2); } break; =20 @@ -2097,7 +2104,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, NR, a0, a2); } else { - tcg_out_insn(s, RRF, NRK, a0, a1, a2); + tcg_out_insn(s, RRFa, NRK, a0, a1, a2); } break; case INDEX_op_or_i32: @@ -2108,7 +2115,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, OR, a0, a2); } else { - tcg_out_insn(s, RRF, ORK, a0, a1, a2); + tcg_out_insn(s, RRFa, ORK, a0, a1, a2); } break; case INDEX_op_xor_i32: @@ -2119,7 +2126,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); } else { - tcg_out_insn(s, RRF, XRK, a0, a1, a2); + tcg_out_insn(s, RRFa, XRK, a0, a1, a2); } break; =20 @@ -2347,7 +2354,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, SGR, a0, a2); } else { - tcg_out_insn(s, RRF, SGRK, a0, a1, a2); + tcg_out_insn(s, RRFa, SGRK, a0, a1, a2); } break; =20 @@ -2359,7 +2366,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, NGR, args[0], args[2]); } else { - tcg_out_insn(s, RRF, NGRK, a0, a1, a2); + tcg_out_insn(s, RRFa, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: @@ -2370,7 +2377,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, OGR, a0, a2); } else { - tcg_out_insn(s, RRF, OGRK, a0, a1, a2); + tcg_out_insn(s, RRFa, OGRK, a0, a1, a2); } break; case INDEX_op_xor_i64: @@ -2381,7 +2388,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, XGR, a0, a2); } else { - tcg_out_insn(s, RRF, XGRK, a0, a1, a2); + tcg_out_insn(s, RRFa, XGRK, a0, a1, a2); } break; =20 --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964051; cv=none; d=zohomail.com; s=zohoarc; b=JMFxQnzF+hTCCHE4U0bRtnH4+Azw7oWvSzS4YeNhRV04MpCqWjjxx5diEHd06PxrNDj3dmiLMj5UJkDo4pfS5TjDhxySlxBuFP8K+l+AEZxi+LiDLkE8TO8mu7muzAZ93/9RPlSi9JNj0PRR0ggom9sALRX/6T696OgmOp3MqQA= ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.c.inc | 47 +++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a489b3359e..d02b433271 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -133,16 +133,19 @@ typedef enum S390Opcode { RI_OILL =3D 0xa50b, RI_TMLL =3D 0xa701, =20 - RIE_CGIJ =3D 0xec7c, - RIE_CGRJ =3D 0xec64, - RIE_CIJ =3D 0xec7e, - RIE_CLGRJ =3D 0xec65, - RIE_CLIJ =3D 0xec7f, - RIE_CLGIJ =3D 0xec7d, - RIE_CLRJ =3D 0xec77, - RIE_CRJ =3D 0xec76, - RIE_LOCGHI =3D 0xec46, - RIE_RISBG =3D 0xec55, + RIEb_CGRJ =3D 0xec64, + RIEb_CLGRJ =3D 0xec65, + RIEb_CLRJ =3D 0xec77, + RIEb_CRJ =3D 0xec76, + + RIEc_CGIJ =3D 0xec7c, + RIEc_CIJ =3D 0xec7e, + RIEc_CLGIJ =3D 0xec7d, + RIEc_CLIJ =3D 0xec7f, + + RIEf_RISBG =3D 0xec55, + + RIEg_LOCGHI =3D 0xec46, =20 RRE_AGR =3D 0xb908, RRE_ALGR =3D 0xb90a, @@ -561,7 +564,7 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode o= p, TCGReg r1, int i2) tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); } =20 -static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, +static void tcg_out_insn_RIEg(TCGContext *s, S390Opcode op, TCGReg r1, int i2, int m3) { tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); @@ -1008,9 +1011,9 @@ static inline void tcg_out_risbg(TCGContext *s, TCGRe= g dest, TCGReg src, int msb, int lsb, int ofs, int z) { /* Format RIE-f */ - tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src); + tcg_out16(s, (RIEf_RISBG & 0xff00) | (dest << 4) | src); tcg_out16(s, (msb << 8) | (z << 7) | lsb); - tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff)); + tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); } =20 static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg sr= c) @@ -1350,7 +1353,7 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, /* Emit: d =3D 0, d =3D (cc ? 1 : d). */ cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); + tcg_out_insn(s, RIEg, LOCGHI, dest, 1, cc); return; } =20 @@ -1443,7 +1446,7 @@ static void tgen_movcond(TCGContext *s, TCGType type,= TCGCond c, TCGReg dest, if (HAVE_FACILITY(LOAD_ON_COND)) { cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); if (v3const) { - tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); + tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); } else { tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc); } @@ -1530,6 +1533,7 @@ static void tgen_compare_branch(TCGContext *s, S390Op= code opc, int cc, TCGReg r1, TCGReg r2, TCGLabel *l) { tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); + /* Format RIE-b */ tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); tcg_out16(s, 0); tcg_out16(s, cc << 12 | (opc & 0xff)); @@ -1539,6 +1543,7 @@ static void tgen_compare_imm_branch(TCGContext *s, S3= 90Opcode opc, int cc, TCGReg r1, int i2, TCGLabel *l) { tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); + /* Format RIE-c */ tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); tcg_out16(s, 0); tcg_out16(s, (i2 << 8) | (opc & 0xff)); @@ -1558,8 +1563,8 @@ static void tgen_brcond(TCGContext *s, TCGType type, = TCGCond c, =20 if (!c2const) { opc =3D (type =3D=3D TCG_TYPE_I32 - ? (is_unsigned ? RIE_CLRJ : RIE_CRJ) - : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ)); + ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) + : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); tgen_compare_branch(s, opc, cc, r1, c2, l); return; } @@ -1570,18 +1575,18 @@ static void tgen_brcond(TCGContext *s, TCGType type= , TCGCond c, larger comparison range afforded by COMPARE IMMEDIATE. */ if (type =3D=3D TCG_TYPE_I32) { if (is_unsigned) { - opc =3D RIE_CLIJ; + opc =3D RIEc_CLIJ; in_range =3D (uint32_t)c2 =3D=3D (uint8_t)c2; } else { - opc =3D RIE_CIJ; + opc =3D RIEc_CIJ; in_range =3D (int32_t)c2 =3D=3D (int8_t)c2; } } else { if (is_unsigned) { - opc =3D RIE_CLGIJ; + opc =3D RIEc_CLGIJ; in_range =3D (uint64_t)c2 =3D=3D (uint8_t)c2; } else { - opc =3D RIE_CGIJ; + opc =3D RIEc_CGIJ; in_range =3D (int64_t)c2 =3D=3D (int8_t)c2; } } --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964319; cv=none; d=zohomail.com; s=zohoarc; b=j8Mkmf3dmOClUh4rgEdVqHaXsQKV3wpkZnDkbjHDU1TnzwWpoosf3qAQd+KCCoOPCORli7I9JlBRH46UTvHG0OSN4GibgcBzu9A/YWWFPaP/ymHndlqUFuub9s2xbR0cN8irt5kqny/ovtvA3w357nWNN1FTWoVKh8ZFfC41mK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964319; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SALIZINGdn2w7on0H3KHxyUtfANKPc/CHhJmhj36m1o=; b=EsEZBxYFDFf3Q9SV7dNEB/tcX5AwrLahRJpI0rx43l8lY2rRTjimejV3xdr1wZnCVJYBgIZrsCgbvY89xgYd1yHpXduS7Eq5JpoFM9CDMAy5P/G3Zfb5zs/0lh3ofDCxIsJLpHT6QKSfobyIDnlLYqqQsjKMNtjhwR2etxAFnlA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964319362569.7587578851148; Thu, 1 Dec 2022 22:58:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuA-0007aa-JY; Fri, 02 Dec 2022 01:52:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zu6-0007ZD-5c for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:10 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu4-0003d6-2n for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:09 -0500 Received: by mail-pf1-x432.google.com with SMTP id w129so4088808pfb.5 for ; Thu, 01 Dec 2022 22:52:07 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SALIZINGdn2w7on0H3KHxyUtfANKPc/CHhJmhj36m1o=; b=M0Bx5ZwM2t4t1qjazItnFCJoLSeRr8MKfN+8Hacjp01i0sHc4jzdcavwTSeYJyUFN9 Zuq5eKgPsecICFPaiabCzXvza2ILY7Sr2HeCu+qFMKG6vFhRgAgeCGQbhN2x/fp76CQf VkfrGYwNRBEkmNeHcvXsYqhb4kMdNOMwOFcIBM5moQW/6nsbDzBtrQ53yuanZ+Xz3rSI zFwTPHzLRLWox9He7KudQNVpYU+CZd1XvlE+IxGXqt8SD5V6NTJL08WdTCiq0K6WGRi3 7CP0iDTtRXWgj93ibU9thN9tzTHCWDJwJrWNgEz71Ur580NQBI2UcMT851p0OdoZ7nSj E9Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SALIZINGdn2w7on0H3KHxyUtfANKPc/CHhJmhj36m1o=; b=jGnKnbYbd/I/Him/U5wcEZWAXTFWdv3SoaKnXVywfFDQi0k5OiPeJRguLrhr21N8fx 8Koh1CgW9DnLyQXWt2D82gz2lq6quaQYjr++SHuiUn7ygwBm0j510coLiHyTawJJhcFO 0M3kWcU2AVT0yW7EkD4hIeFQaaiUeHJdiMva14ixXTDGRnwdGmhZ2y3cEywp+gEti4jO Oh5gYqXWtOZksHn83zEiN188uXDwbSSGkVlwLdk7BlHbMd66GjVj/EPGBhcQRpk/u/8P CEKUsNENNv1MQPTIaaGuEu1RJRrp41/c7XEcegOCbkFCnxyImpgGJY0AHA29+0hI4D3H wa1g== X-Gm-Message-State: ANoB5pnEcHvithMYeJD4HGTVcq+kyNcZWO1EguoETbG34QTjXweFNpI4 82qkwsfMKV7ON6sgNuRsgkgR1wZiYEq6MAHy X-Google-Smtp-Source: AA0mqf75a2xuSRqIr8gPZW4ozmO6oP+fnXjUQTDD8voTEWRAIanY1QXoKFrB5MntccX21oyBPH1H6w== X-Received: by 2002:a63:f003:0:b0:45f:bf86:c917 with SMTP id k3-20020a63f003000000b0045fbf86c917mr62244632pgh.201.1669963927372; Thu, 01 Dec 2022 22:52:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 06/13] tcg/s390x: Support MIE2 multiply single instructions Date: Thu, 1 Dec 2022 22:51:53 -0800 Message-Id: <20221202065200.224537-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964319744100003 Content-Type: text/plain; charset="utf-8" The MIE2 facility adds 3-operand versions of multiply. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 1 + tcg/s390x/tcg-target.c.inc | 34 ++++++++++++++++++++++++---------- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 00ba727b70..33a82e3286 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -23,6 +23,7 @@ C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) +C_O1_I2(r, r, rJ) C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) C_O1_I2(v, v, v) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 645f522058..bfd623a639 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -63,6 +63,7 @@ typedef enum TCGReg { #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND #define FACILITY_LOAD_ON_COND2 53 +#define FACILITY_MISC_INSN_EXT2 58 #define FACILITY_VECTOR 129 #define FACILITY_VECTOR_ENH1 135 =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d02b433271..cd39b2a208 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -180,6 +180,8 @@ typedef enum S390Opcode { RRE_SLBGR =3D 0xb989, RRE_XGR =3D 0xb982, =20 + RRFa_MSRKC =3D 0xb9fd, + RRFa_MSGRKC =3D 0xb9ed, RRFa_NRK =3D 0xb9f4, RRFa_NGRK =3D 0xb9e4, RRFa_ORK =3D 0xb9f6, @@ -2140,14 +2142,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_mul_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; if (const_args[2]) { - if ((int32_t)args[2] =3D=3D (int16_t)args[2]) { - tcg_out_insn(s, RI, MHI, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + if (a2 =3D=3D (int16_t)a2) { + tcg_out_insn(s, RI, MHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSFI, a0, a2); } + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, MSR, a0, a2); } else { - tcg_out_insn(s, RRE, MSR, args[0], args[2]); + tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2); } break; =20 @@ -2405,14 +2411,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_mul_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - if (args[2] =3D=3D (int16_t)args[2]) { - tcg_out_insn(s, RI, MGHI, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + if (a2 =3D=3D (int16_t)a2) { + tcg_out_insn(s, RI, MGHI, a0, a2); } else { - tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); + tcg_out_insn(s, RIL, MSGFI, a0, a2); } + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, MSGR, a0, a2); } else { - tcg_out_insn(s, RRE, MSGR, args[0], args[2]); + tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2); } break; =20 @@ -3072,12 +3082,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ return (HAVE_FACILITY(GEN_INST_EXT) - ? C_O1_I2(r, 0, ri) + ? (HAVE_FACILITY(MISC_INSN_EXT2) + ? C_O1_I2(r, r, ri) + : C_O1_I2(r, 0, ri)) : C_O1_I2(r, 0, rI)); =20 case INDEX_op_mul_i64: return (HAVE_FACILITY(GEN_INST_EXT) - ? C_O1_I2(r, 0, rJ) + ? (HAVE_FACILITY(MISC_INSN_EXT2) + ? C_O1_I2(r, r, rJ) + : C_O1_I2(r, 0, rJ)) : C_O1_I2(r, 0, rI)); =20 case INDEX_op_shl_i32: --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669963964; cv=none; d=zohomail.com; s=zohoarc; b=lwFB37PIOzL3L9iyYVLc15++IoV/mIqXpUUOl3slCyRhtkjlNf8bLfWwJIhEjIi53FSk/nmj7J8PKBZhd8iJYrEbqSnmPuvb5zUibnnWKw81iJJuIdGxdUYb7s5gRBy8mhKg7seaWmQnOSt7xtOJ3c1W0LuKxBCOQB6yNG/HllE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669963964; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q81nlbrOY0/jS8UUTYcxCThqSVtNPQMY+4Mx529BC3o=; b=XwXgn58CK25FrhvTulqoCgEKuD5phbZufVqsKzQflbtLGdgoVWxvO01NG/BG9bnE/EYImUWUy1fsUrS4/NkP7FfI+wI8GexeNe0VJKrEarwQH6omhcacGKHNzG7PYevu7gtpPvjbNRdaCfd8Wn2Tpoa0zpsGiYy/4dcKAiITHF4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669963964106177.61757640137034; Thu, 1 Dec 2022 22:52:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuB-0007b4-MD; Fri, 02 Dec 2022 01:52:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zu7-0007Zo-BP for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:14 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu5-0003ge-N4 for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:11 -0500 Received: by mail-pg1-x529.google.com with SMTP id q1so3641613pgl.11 for ; Thu, 01 Dec 2022 22:52:09 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q81nlbrOY0/jS8UUTYcxCThqSVtNPQMY+4Mx529BC3o=; b=iDhjqUN54CStq6t1HNNRH35y8F5nXksPKzPtro03e0DfpdXMVvoBSXNaD/3xFflgYA 8lygD5I4CKni2gaNHr4QVPFAAzcBz0YcbwUGCa6WvSUYDUu+nvfcrsuE1M0bnZLqVqJ/ 5q5yyLtGLQro4FzF5dcLbOjD6HZgriTb+QoNmMSBAnyvy2aU0K7GFWEV8N+LLHLbqRYq F2+k9LIn//v5JBFXrx1owolwG3mmN9+3uDxUYLW3PVVpiwdJIgqL8u0fjA6Z3/bxwsdK p4g8k/Qsh+uxMWphPvmrksvWpeobZl2F6EDJLTv1PE+jiJmkvHKRSYNthLFqQzAxnVo8 r/+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q81nlbrOY0/jS8UUTYcxCThqSVtNPQMY+4Mx529BC3o=; b=IkcZMCxHFOJnI7Fj0gExLbntaUGLXXSPMQZmb0/qNeLp9eHCAJDnlsXAfi7+wedTjS inSicb3VS1t68anShksTu+eo+OvbFOPNGhFHyfypAJm9JRT2L7rJxnSJKPFBWqgirIu9 wLG/ywYiXYllrt3nkoqz8cD494aoqb/dF3eKWrVv8F0JHkOTXpobr3OqIj7VzpRXppq/ mKeYdPa2Ky3vXUjsAq3XrsnyyHU0s9mqWQ9lUzoj4itFW7jQmgShY+/Rv+SvKC8/GKD8 fzVAg3x4SZjtxTN4ua+chLYnUtGRPtPmuiLuNXGRofxmC7MqmVH0iSG5sLIMKaNO+rix AmJA== X-Gm-Message-State: ANoB5pkDNxNf6j5TVTOV/h/5j9O13ABtoy01vxGaWpIZ70offP+0RfKo 1SjY5U35oC2ICQPoosPU5P8F7q57S+esKhe6 X-Google-Smtp-Source: AA0mqf6wYCHaiSYsLj6TdZKcxEdcsTkXCocnQEBZsFF3bF7DRlP/iVav+FiKRw/BNHdijrwN8jbTKA== X-Received: by 2002:aa7:810e:0:b0:56b:f23a:7854 with SMTP id b14-20020aa7810e000000b0056bf23a7854mr56128081pfi.66.1669963928411; Thu, 01 Dec 2022 22:52:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 07/13] tcg/s390x: Support MIE2 MGRK instruction Date: Thu, 1 Dec 2022 22:51:54 -0800 Message-Id: <20221202065200.224537-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669963965939100005 Content-Type: text/plain; charset="utf-8" The MIE2 facility adds a 3-operand signed 64x64->128 multiply. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 33a82e3286..b1a89a88ba 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -31,6 +31,7 @@ C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(o, m, 0, r) +C_O2_I2(o, m, r, r) C_O2_I3(o, m, 0, 1, r) C_O2_I4(r, r, 0, 1, rA, r) C_O2_I4(r, r, 0, 1, ri, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index bfd623a639..09cf6e60fc 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -136,7 +136,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2) #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index cd39b2a208..7315602331 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -180,6 +180,7 @@ typedef enum S390Opcode { RRE_SLBGR =3D 0xb989, RRE_XGR =3D 0xb982, =20 + RRFa_MGRK =3D 0xb9ec, RRFa_MSRKC =3D 0xb9fd, RRFa_MSGRKC =3D 0xb9ed, RRFa_NRK =3D 0xb9f4, @@ -2452,6 +2453,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tcg_debug_assert(args[0] =3D=3D args[1] + 1); tcg_out_insn(s, RRE, MLGR, args[1], args[3]); break; + case INDEX_op_muls2_i64: + tcg_debug_assert((args[1] & 1) =3D=3D 0); + tcg_debug_assert(args[0] =3D=3D args[1] + 1); + tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); + break; =20 case INDEX_op_shl_i64: op =3D RSY_SLLG; @@ -3153,6 +3159,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_mulu2_i64: return C_O2_I2(o, m, 0, r); + case INDEX_op_muls2_i64: + return C_O2_I2(o, m, r, r); =20 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964289; cv=none; d=zohomail.com; s=zohoarc; b=idH/A61/W4wT5DX8Wuk4yiQB5IZnd11Vrlk/iBzmWEyOnpcliYTb3URGExTSQKpC/Oacg/rPiSuCI/6Ii2lEWHek3mW/two3X/YDqG2/+w2Zg3cV09hI5Tl9nBKoMMyp5X49OQUgz4l0o5BqqPsTpY18Pk+UrbRA5uOm/Rhkg0E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964289; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BRN4OmSigAXOy9GNtbEG61WfbotphHHEPBF4z7Ca8UY=; b=BOY+IpQVchppYYGgrUNwDDz49nTXUuchzc0Gjf8ODXR/BEkLgHG6eA3fH1O3GIrXnRoPgSyBTjYsCQEpaeY1QC2kcDNLuYVdBmsxoiiip75luISiApeBqu2r4ItcJ39/dpAjPiwyErWtrhPVlPHiHh4HRfPjGY1T5DFxY0IbxI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964289044824.8607848673867; Thu, 1 Dec 2022 22:58:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuD-0007cI-85; Fri, 02 Dec 2022 01:52:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zu8-0007Zp-HF for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:14 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu6-0003hA-LT for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:12 -0500 Received: by mail-pf1-x435.google.com with SMTP id z14so177639pfr.11 for ; Thu, 01 Dec 2022 22:52:10 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BRN4OmSigAXOy9GNtbEG61WfbotphHHEPBF4z7Ca8UY=; b=CVVQ+P/xLMznRtfQW+wwrtARrLk09lpu1VnQ7PUfPfxn1ymYl/bxIxfXKlQ8YMhHpG 06dY9WNNFW+BkNr2zF2OEaSDzWd5FiR5Ewtbgojub+mMJXkEzNGYihSgs39U5aOo9kEP 3Ss57c4xAQr/Nii6mL43JYVP5p4MhoyQ1ZA192jNi+msOk7nukQkVkeVVTfJcLMyDF58 jQwPZlsswTRbvBouIG4Q/YNcfKLpDftt9ipjcRhpvxNIKaYQtxFORHGmFVdBOo5EnyVA int0977D2HDRbM2i6hW/1UPcxShTpMMSom/WncZPgwzwZPvC4rUsuhEPNbL/fFhgGxJC eG1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BRN4OmSigAXOy9GNtbEG61WfbotphHHEPBF4z7Ca8UY=; b=OLbtkG/I4jLQwIwuOQzzS4aqDNUFsfMQS4b8TjtpelU6tFEbAm8sUh4DkXlgZl9j10 +C1cH35ltEOhaz2E3PXz3QnztlmYmKiP4/vPMndelxk8/BA/9yfMNx0q+4r53gvS4bjz TrvWGPYjfIQMCE7j/StEznX7amT/nQWUX3UExDE+s2rsXvLjO0IwtFHf9cqS2JahXc+W 5B0jpBLF4R9D312zqZpzHMIpVGMnuUOky7FPTVhGbP0l0Bez3pEQIlhpNvTiA0PsbMqN 9qBat9N/fB3C6Rx5+msTVvxXMIw6femoXVzPnhnCxXH4qzLTiNS9ZYggQZTxkhMSJizp v8Vw== X-Gm-Message-State: ANoB5pl5e978gBPNnC53VVPKNwR+4ETrF+EXHBhviHpioeV1StZ4iYWQ Ha5yOSEEZ+0plcYvpOSxjkxvD8UX4r19fj0D X-Google-Smtp-Source: AA0mqf7lkLtQ2c1Cf1p8b17i0Dx/vhp3CP3aB/cr/U+YqDVV+5iSz61hsdDzBRzv6vD2Al2hLxSanQ== X-Received: by 2002:a63:580a:0:b0:477:12e3:6e1c with SMTP id m10-20020a63580a000000b0047712e36e1cmr46165624pgb.126.1669963929381; Thu, 01 Dec 2022 22:52:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 08/13] tcg/s390x: Support MIE3 logical operations Date: Thu, 1 Dec 2022 22:51:55 -0800 Message-Id: <20221202065200.224537-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964289739100002 Content-Type: text/plain; charset="utf-8" This is andc, orc, nand, nor, eqv. We can use nor for implementing not. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 25 +++++---- tcg/s390x/tcg-target.c.inc | 100 +++++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+), 12 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index b1a89a88ba..dc271a6d11 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -22,6 +22,7 @@ C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rJ) C_O1_I2(r, rZ, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 09cf6e60fc..191c6a073e 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -64,6 +64,7 @@ typedef enum TCGReg { #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND #define FACILITY_LOAD_ON_COND2 53 #define FACILITY_MISC_INSN_EXT2 58 +#define FACILITY_MISC_INSN_EXT3 61 #define FACILITY_VECTOR 129 #define FACILITY_VECTOR_ENH1 135 =20 @@ -81,13 +82,13 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_not_i32 0 +#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_neg_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 -#define TCG_TARGET_HAS_orc_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_andc_i32 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_orc_i32 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_nand_i32 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_nor_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 @@ -118,13 +119,13 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 -#define TCG_TARGET_HAS_not_i64 0 +#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_neg_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_orc_i64 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_nand_i64 HAVE_FACILITY(MISC_INSN_EXT3) +#define TCG_TARGET_HAS_nor_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM) #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 7315602331..4dcdad04c5 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -183,8 +183,18 @@ typedef enum S390Opcode { RRFa_MGRK =3D 0xb9ec, RRFa_MSRKC =3D 0xb9fd, RRFa_MSGRKC =3D 0xb9ed, + RRFa_NCRK =3D 0xb9f5, + RRFa_NCGRK =3D 0xb9e5, + RRFa_NNRK =3D 0xb974, + RRFa_NNGRK =3D 0xb964, + RRFa_NORK =3D 0xb976, + RRFa_NOGRK =3D 0xb966, RRFa_NRK =3D 0xb9f4, RRFa_NGRK =3D 0xb9e4, + RRFa_NXRK =3D 0xb977, + RRFa_NXGRK =3D 0xb967, + RRFa_OCRK =3D 0xb975, + RRFa_OCGRK =3D 0xb965, RRFa_ORK =3D 0xb9f6, RRFa_OGRK =3D 0xb9e6, RRFa_SRK =3D 0xb9f9, @@ -2138,9 +2148,46 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, } break; =20 + case INDEX_op_andc_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, ~a2); + } else { + tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); + } + break; + case INDEX_op_orc_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_ori(s, TCG_TYPE_I32, a0, ~a2); + } else { + tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); + } + break; + case INDEX_op_eqv_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_xori(s, TCG_TYPE_I32, a0, ~a2); + } else { + tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); + } + break; + case INDEX_op_nand_i32: + tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); + break; + case INDEX_op_nor_i32: + tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]); + break; + case INDEX_op_neg_i32: tcg_out_insn(s, RR, LCR, args[0], args[1]); break; + case INDEX_op_not_i32: + tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[1]); + break; =20 case INDEX_op_mul_i32: a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; @@ -2404,9 +2451,46 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, } break; =20 + case INDEX_op_andc_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen_andi(s, TCG_TYPE_I64, a0, ~a2); + } else { + tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); + } + break; + case INDEX_op_orc_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen_ori(s, TCG_TYPE_I64, a0, ~a2); + } else { + tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); + } + break; + case INDEX_op_eqv_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; + if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen_xori(s, TCG_TYPE_I64, a0, ~a2); + } else { + tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); + } + break; + case INDEX_op_nand_i64: + tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); + break; + case INDEX_op_nor_i64: + tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]); + break; + case INDEX_op_neg_i64: tcg_out_insn(s, RRE, LCGR, args[0], args[1]); break; + case INDEX_op_not_i64: + tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[1]); + break; case INDEX_op_bswap64_i64: tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); break; @@ -3083,6 +3167,20 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); =20 + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + return C_O1_I2(r, r, ri); + + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + return C_O1_I2(r, r, r); + case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we @@ -3118,6 +3216,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_bswap64_i64: case INDEX_op_neg_i32: case INDEX_op_neg_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964317; cv=none; d=zohomail.com; s=zohoarc; b=ME4xeL8fTjChPSPgdZpUqW0s8mXbl2lnh46DmBRdqncRTI8bqiYMrZWOsPtUDDWrfOCFhY/VYTmsmVr61sTSNTLwb4Y5NaQi6kRM0KxJrWBbNgmdWxyi3lGdZxwPRV3Z4dOoetIUwYS6Jnb119PSKV97sWQbpQzlDijiDM8p/WQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964317; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4sFX9yZOyM3r1MgjgBiirAQT8v3uQu+8pCAPlCWzIFM=; b=Fo3lK4NWO9xMHkVFp1MNwUgn7RPZCIbdLZ2PIgbFlStBv0zkQozMHiIu+bUSInfN7OMKPQfo3+OfjzFxALl07KLV6SASzPk8e94RR8urQnFQg4giZgqisWNf1WnRVi12vlOR9rtn2npOsEJ/BMhJfg61kthT8qKbBz38QqqsP3Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964317632100.10987050224492; Thu, 1 Dec 2022 22:58:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuA-0007ay-VZ; Fri, 02 Dec 2022 01:52:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zu9-0007Zr-5K for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:14 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu7-0003ha-I7 for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:12 -0500 Received: by mail-pg1-x52b.google.com with SMTP id 82so3706292pgc.0 for ; Thu, 01 Dec 2022 22:52:11 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4sFX9yZOyM3r1MgjgBiirAQT8v3uQu+8pCAPlCWzIFM=; b=ra5DsSlWn/fRtlIkOKx5G1zuEUQd7IvkZzAb4bfpcN6vchWZoI/1n7RXKAS6YTNdM5 QnmDHSBI0tZMsu4+3RyZ/NJHsyMkfA7r6x6q+aqywFXENFI3xctJeHGQ1E3fwc3fQDoG kfoAlT4sgzDwkt+uiYA1JfxyPQzNQYhoXLMTvzorlH3tuHUTx/O7C4Lwwo8rQfTiuoN0 nRKErH7J4DD8vU0bH8zwzizGQOfNcwcmRVAt/hDAhmHvPbVdQkutc+zW/myOMFgHYJEw ocymuwgv8Dal8YCsmNk/1bmWOq2mcSfOMMURJBgw2PFo9NON/rV/WesyPeRhUvn3Krwi Gbng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4sFX9yZOyM3r1MgjgBiirAQT8v3uQu+8pCAPlCWzIFM=; b=Elw2CSfAH0KJQcWxf1JRMUC+THoVijAhMYQDDgOFiP+AHYH+GSRx3xijkFPMcd2jsN lF3zBWVhOlvVFMnFacCuwmZfPzkS7wrl4dg8L4LbYMoP5ngFb9FUKvM4zA7NTk0h9PXz +mzNyeHhhvXYryQa3saKDp0vuXq1l+2sSDDJx0RbMhQ8uoo0uhWIJT919fHcJFBW0hR5 HVYyro3KSWmMlpF6fKQnRgjYqLqwphVrH/UOQsxpCuJc18kKiNHhE/piNDYh8uZku69a zWBzReMEWBROMRkbe3xHazV14K56v+y5F3rTiiqw8KY0L04HWton0cqy3MztEYvNNTq2 vROQ== X-Gm-Message-State: ANoB5pkLExQ2++i46WNQWA1G2omJXnko1uuj9126jCksw8AmnivGi5eq KtLsLejSfkBDeci7aDr0CWSDIAqGi7lRyCj8 X-Google-Smtp-Source: AA0mqf5ucGRGKSDC2FG/4XKuCvHRecgWGEonWzKJmK7hBymh9O5zHf/Cb9cXC1kL7MgejSK3QrOpGQ== X-Received: by 2002:a05:6a00:216e:b0:56e:7b62:bba with SMTP id r14-20020a056a00216e00b0056e7b620bbamr50992281pff.55.1669963930247; Thu, 01 Dec 2022 22:52:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 09/13] tcg/s390x: Create tgen_cmp2 to simplify movcond Date: Thu, 1 Dec 2022 22:51:56 -0800 Message-Id: <20221202065200.224537-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964319704100001 Content-Type: text/plain; charset="utf-8" Return both regular and inverted condition codes from tgen_cmp2. This lets us choose after the fact which comparision we want. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4dcdad04c5..fad86f01f3 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1288,10 +1288,11 @@ static void tgen_xori(TCGContext *s, TCGType type, = TCGReg dest, uint64_t val) } } =20 -static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, - TCGArg c2, bool c2const, bool need_carry) +static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, + TCGArg c2, bool c2const, bool need_carry, int *inv_cc) { bool is_unsigned =3D is_unsigned_cond(c); + TCGCond inv_c =3D tcg_invert_cond(c); S390Opcode op; =20 if (c2const) { @@ -1302,6 +1303,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGC= ond c, TCGReg r1, } else { tcg_out_insn(s, RRE, LTGR, r1, r1); } + *inv_cc =3D tcg_cond_to_ltr_cond[inv_c]; return tcg_cond_to_ltr_cond[c]; } } @@ -1352,9 +1354,17 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCG= Cond c, TCGReg r1, } =20 exit: + *inv_cc =3D tcg_cond_to_s390_cond[inv_c]; return tcg_cond_to_s390_cond[c]; } =20 +static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, + TCGArg c2, bool c2const, bool need_carry) +{ + int inv_cc; + return tgen_cmp2(s, type, c, r1, c2, c2const, need_carry, &inv_cc); +} + static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int c2const) { @@ -1455,20 +1465,19 @@ static void tgen_movcond(TCGContext *s, TCGType typ= e, TCGCond c, TCGReg dest, TCGReg c1, TCGArg c2, int c2const, TCGArg v3, int v3const) { - int cc; + int cc, inv_cc; + + cc =3D tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); + if (HAVE_FACILITY(LOAD_ON_COND)) { - cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); if (v3const) { tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); } else { tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc); } } else { - c =3D tcg_invert_cond(c); - cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); - /* Emit: if (cc) goto over; dest =3D r3; over: */ - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_insn(s, RI, BRC, inv_cc, (4 + 4) >> 1); tcg_out_insn(s, RRE, LGR, dest, v3); } } --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964081; cv=none; d=zohomail.com; s=zohoarc; b=Ih1Q6bvtK4Xii6+2taGrVgs4hbh5rK9Bk7vJcmAVW0E7BXot2D0L02fc0FrRDCKkEJKuUrqGlhqZYiOzonC22RZsAzr3Mog/sfM0OlEPymFh6eFhPzlPiSqh5YYAXNaQ5cwknEWH+KOA2kVxqJOC1yP2u7IU8xDbc57/6fU6nbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964081; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k7bPsv0avo+ZkLhyF6N/wgL5oGyNcPHPmhD8reBv+lg=; b=ccCr1PAMdT1GJf27eQyd0wr3p3UlmYK48CGv6FP/DL+97ah639AuanMhXkT5k9ysd3pVJobD8ZOOFD7NOAQiv2xZCAdJlHjWma/CG0A2bipgyUZmyswak2+dbW0dtm+ZRBo94zBRfAr73fqzzLDFnI1gB927BVOHeW0kvttSpkU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964080995170.32568252325495; Thu, 1 Dec 2022 22:54:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuC-0007bt-IG; Fri, 02 Dec 2022 01:52:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zuA-0007aP-BY for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:14 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zu8-0003is-J6 for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:14 -0500 Received: by mail-pg1-x52d.google.com with SMTP id 82so3706314pgc.0 for ; Thu, 01 Dec 2022 22:52:12 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k7bPsv0avo+ZkLhyF6N/wgL5oGyNcPHPmhD8reBv+lg=; b=a/QhVP6e591p28Ut+mJWrJClvJvbngK/sGOVOrliTcpd8b7M0AFt7YLIS28hctdISg hxha21B2J3jlCWAdOneAQMgqQV8ly/UcnygYVCtPujdQJtzoboMmx8QvIFs8vcrFpx+e MjFans12mpIVNV2DtmRWewZ8Fsus2wjdxDkluOiJzEP4VWNDDm01sTA7MpbuK6G3GlX6 uWy+o7BRAPpRgN3gtINQo4tCXwbveD8zTPRiDXzidj+ioit+KEdsUq7z4qojQzNLbS/s X5niWwy1sRPDVFnp/DFAAs36LrTeighmwZHeMDKpS3FxEzLQoZDJXXcmks0iFq5uqC63 XT6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k7bPsv0avo+ZkLhyF6N/wgL5oGyNcPHPmhD8reBv+lg=; b=B3zP/cCjaEeWbh64Sk2+NfEOtZZ8V4aS99NpQEzN+U7+licHtdvV5auj7519R78o6C BLXmY4PObaPpjQD+UcsnQ1Ytr96XrKKKsxJ9TeJEs6xu1qcLWKhrYTHk+BbleyEXyr8B LeQG833KnROMqtAPkC7HpjLvMU83WQIMOtEICDggdFLihG5UNvUrKdI1NUinoFtJj/ZO 2Lsvo0NsoKgbAEPQ/hJHYizvYxmMfKpIXKP3XV1iMHr5XtyPp5K/drNRPP4UEZetL5X+ aP71wAFw8b4jc0VL3fA4Opq9WAyiaePteSO36rnTqP9UTxrP/oAUYpb3p5YJUs14UG+8 f95g== X-Gm-Message-State: ANoB5pkblxyVWr1umOO8VWJiZcMrZGDgyZrnI4tDuABpFqZ4DdUpGyyV teXmv+1GB4IDeuPnOeJRInWUdAdjopGwkC3I X-Google-Smtp-Source: AA0mqf6BCbJ2FLkyVbJKfBjUwU0Kb5FjKBLgwj5SC924bIZZtt7wWdhXUpqgQr7D5sm25S4r+i78Yw== X-Received: by 2002:a63:1c55:0:b0:477:d9fe:c3b0 with SMTP id c21-20020a631c55000000b00477d9fec3b0mr32561117pgm.445.1669963931256; Thu, 01 Dec 2022 22:52:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 10/13] tcg/s390x: Generalize movcond implementation Date: Thu, 1 Dec 2022 22:51:57 -0800 Message-Id: <20221202065200.224537-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964082271100004 Content-Type: text/plain; charset="utf-8" Generalize movcond to support pre-computed conditions, and the same set of arguments at all times. This will be assumed by a following patch, which needs to reuse tgen_movcond_int. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target-con-set.h | 3 +- tcg/s390x/tcg-target.c.inc | 78 ++++++++++++++++++++++++++-------- 2 files changed, 61 insertions(+), 20 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index dc271a6d11..86cdc248f2 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -29,8 +29,7 @@ C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) -C_O1_I4(r, r, ri, r, 0) -C_O1_I4(r, r, ri, rI, 0) +C_O1_I4(r, r, ri, rI, r) C_O2_I2(o, m, 0, r) C_O2_I2(o, m, r, r) C_O2_I3(o, m, 0, 1, r) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fad86f01f3..b2adbbe7de 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1461,25 +1461,69 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, } } =20 +static void tgen_movcond_int(TCGContext *s, TCGType type, TCGReg dest, + TCGArg v3, int v3const, TCGReg v4, + int cc, int inv_cc) +{ + TCGReg src; + + /* If dest !=3D v4, LGR+LOCGHI is larger than LGHI+{LOCGR,SELGR}. */ + if (HAVE_FACILITY(LOAD_ON_COND2) && v3const && dest =3D=3D v4) { + /* Emit: if (cc) dest =3D v3. */ + tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); + return; + } + + if (HAVE_FACILITY(LOAD_ON_COND)) { + if (dest =3D=3D v4) { + if (v3const) { + tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); + src =3D TCG_TMP0; + } else { + src =3D v3; + } + } else { + if (v3const) { + tcg_out_insn(s, RI, LGHI, dest, v3); + } else { + tcg_out_mov(s, type, dest, v3); + } + cc =3D inv_cc; + src =3D v4; + } + /* Emit: if (cc) dest =3D src. */ + tcg_out_insn(s, RRFc, LOCGR, dest, src, cc); + return; + } + + if (v3const) { + tcg_out_mov(s, type, dest, v4); + /* Emit: if (!cc) goto over; dest =3D r3; over: */ + tcg_out_insn(s, RI, BRC, inv_cc, (4 + 4) >> 1); + tcg_out_insn(s, RI, LGHI, dest, v3); + return; + } + + if (dest =3D=3D v4) { + src =3D v3; + } else { + tcg_out_mov(s, type, dest, v3); + inv_cc =3D cc; + src =3D v4; + } + /* Emit: if (!cc) goto over; dest =3D src; over: */ + tcg_out_insn(s, RI, BRC, inv_cc, (4 + 4) >> 1); + tcg_out_insn(s, RRE, LGR, dest, src); +} + static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg de= st, TCGReg c1, TCGArg c2, int c2const, - TCGArg v3, int v3const) + TCGArg v3, int v3const, TCGReg v4) { int cc, inv_cc; =20 cc =3D tgen_cmp2(s, type, c, c1, c2, c2const, false, &inv_cc); - - if (HAVE_FACILITY(LOAD_ON_COND)) { - if (v3const) { - tcg_out_insn(s, RIEg, LOCGHI, dest, v3, cc); - } else { - tcg_out_insn(s, RRFc, LOCGR, dest, v3, cc); - } - } else { - /* Emit: if (cc) goto over; dest =3D r3; over: */ - tcg_out_insn(s, RI, BRC, inv_cc, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, v3); - } + tgen_movcond_int(s, type, dest, v3, v3const, v4, cc, inv_cc); } =20 static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, @@ -2352,7 +2396,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_movcond_i32: tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + args[2], const_args[2], args[3], const_args[3], args[= 4]); break; =20 case INDEX_op_qemu_ld_i32: @@ -2644,7 +2688,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_movcond_i64: tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3], const_args[3]); + args[2], const_args[2], args[3], const_args[3], args[= 4]); break; =20 OP_32_64(deposit): @@ -3256,9 +3300,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return (HAVE_FACILITY(LOAD_ON_COND2) - ? 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([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Of98snGjT8xXsaEJexef1vyfcUCPe7JWl42fv+AP/9U=; b=oKCdyEw98+YbWJhS/mxQVeCvpeYsgyDbYk4uTue63SJl6LywVEglLDXMYsuL7cObtp eNMMIgiMk80bwUpwQzTiWqU2PNYh13f8F0ojgWwn0K1Eid1g4ZUPNVnDXQIl1U/ZJCQ7 Tn5MYfikmheVxIvUoJthNkDW4ogAZayD8WtOtgH2m4+hpLeHzESGKj6u33pOEgOxLhWw iW3Kk1wfjopdOvMhLEOUT4M9BF7LiGvU4yrZfmE63owcn6O4fpIIBSmPSekT+jFdNsg6 J/GBbvcK1CCeSqB6WPlQlotV8sp2fOwqjb5ZW4a9SnXLfpEtqOgqtnuCsels+nySm4Hs n/tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Of98snGjT8xXsaEJexef1vyfcUCPe7JWl42fv+AP/9U=; b=0rHKIVrfTT+E7iKufeRBGgeNP0wKJSD6gXGO5d+jUgRhPIyr8ib/tnbeOenNEVVSm6 xRxknvGrWE1FVSmiVzNCf6QghCM+AVWUuok+trvbUE9Ffpk9WnPtJSCl1Ukp2sDsB6JA bTjPpTSHRlInHucUeEY1Whyp0I65yhPM+32ual5BLE9AHgtYI23EqfzmeId54+VGtpt8 /HHFXIAVnhxbJAJzhOhT20Ry7bBDnyblXrLyZf0dmp2wlqtg6efmbzVwGHZ6xUpsbvjg m9HZ41HkpMfdTbF9QkcjdwQ1Fg3aIRb0ffY3uE+s0Dqo1F/1fLXKF6TLBQn/5WtkGCa5 UBcA== X-Gm-Message-State: ANoB5plF65ruBZqILYJpdUGoYhhsWs5QkXkUubWZOBpImH296IvBrMcc uAI9m7sms94b4O+hkxb6PSXajWaZSdPEzI/q X-Google-Smtp-Source: AA0mqf7YESFHXm0AyWThFFvmWGMoMCw1HLcmcsHC8bOokUP9u3ibWbADejbuCx09HSTB3TvYqbJAqA== X-Received: by 2002:a05:6a00:1814:b0:56b:d7a5:4be5 with SMTP id y20-20020a056a00181400b0056bd7a54be5mr52643505pfa.62.1669963932376; Thu, 01 Dec 2022 22:52:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 11/13] tcg/s390x: Support SELGR instruction in movcond Date: Thu, 1 Dec 2022 22:51:58 -0800 Message-Id: <20221202065200.224537-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964084277100009 Content-Type: text/plain; charset="utf-8" The new select instruction provides two separate register inputs, whereas the old load-on-condition instruction overlaps one of the register inputs with the destination. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.c.inc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b2adbbe7de..1e4947b598 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -204,6 +204,8 @@ typedef enum S390Opcode { RRFa_XRK =3D 0xb9f7, RRFa_XGRK =3D 0xb9e7, =20 + RRFam_SELGR =3D 0xb9e3, + RRFc_LOCR =3D 0xb9f2, RRFc_LOCGR =3D 0xb9e2, =20 @@ -560,12 +562,20 @@ static void tcg_out_insn_RRE(TCGContext *s, S390Opcod= e op, tcg_out32(s, (op << 16) | (r1 << 4) | r2); } =20 +/* RRF-a without the m4 field */ static void tcg_out_insn_RRFa(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2, TCGReg r3) { tcg_out32(s, (op << 16) | (r3 << 12) | (r1 << 4) | r2); } =20 +/* RRF-a with the m4 field */ +static void tcg_out_insn_RRFam(TCGContext *s, S390Opcode op, + TCGReg r1, TCGReg r2, TCGReg r3, int m4) +{ + tcg_out32(s, (op << 16) | (r3 << 12) | (m4 << 8) | (r1 << 4) | r2); +} + static void tcg_out_insn_RRFc(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2, int m3) { @@ -1474,6 +1484,17 @@ static void tgen_movcond_int(TCGContext *s, TCGType = type, TCGReg dest, return; } =20 + /* Note that while MIE3 implies LOC, it does not imply LOC2. */ + if (HAVE_FACILITY(MISC_INSN_EXT3)) { + if (v3const) { + tcg_out_insn(s, RI, LGHI, TCG_TMP0, v3); + v3 =3D TCG_TMP0; + } + /* Emit: dest =3D cc ? v3 : v4. */ + tcg_out_insn(s, RRFam, SELGR, dest, v3, v4, cc); + return; + } + if (HAVE_FACILITY(LOAD_ON_COND)) { if (dest =3D=3D v4) { if (v3const) { --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964288; cv=none; d=zohomail.com; s=zohoarc; b=Ul3TjyrO+cIabp4YwtLpd3zk28XtjoCj5LjdhHtmjBRNkvLD+5btDCA99uGutLgKlJSdLO/NoizoLjCB23Ad/g4ZotJKvFP9psH0RQjaHsxv5ZYSIZzNu/GFyqNzMvi6hmaIk74skEGh3VT8b0yWBAFQSPJy9P4Jo1jkU+dxg8A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964288; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lh58nWvDudjSuhn3rm5AM+63H/4nwM3lp5/LtDDXIfE=; b=LmjiRskhN+0Tm5Qb8BGpob2Oueadez5EPpWONXbfNvHvIJT4ZFHhzCGkyonPus7mJfu1LixKR9IHjrGFeEkQMCJP2dbHhXvThl17Z1PigR7tpsQORG/qrHhXs0EYM1keg7Y8ZiaHYnj++ydtgijX0/hesYYsWmIVI6vPhxzMdAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964288315714.8899087227161; Thu, 1 Dec 2022 22:58:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuD-0007cK-B8; Fri, 02 Dec 2022 01:52:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zuC-0007bZ-AP for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:16 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zuA-0003jG-MV for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:16 -0500 Received: by mail-pj1-x102c.google.com with SMTP id t11-20020a17090a024b00b0021932afece4so7446734pje.5 for ; Thu, 01 Dec 2022 22:52:14 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lh58nWvDudjSuhn3rm5AM+63H/4nwM3lp5/LtDDXIfE=; b=kD7xCOPTpQFWlssr3hvJtXzO/QEkTaqtF7CXHF7KMriEL9fnKIg15FEdqovFAIcumH PKVnjBaBOfUkEfE8v5XBgiGsbyxl4Ixx1Ja0xu2r6pJiFVURT8qgNRVS7+g1zgLv6Bl1 8yh90XdI8fjobYA6hywnGfBgBH62SgXLBOffF2h55RFF7wSpz4IxwoqVCsW7f8p/Dw0d F+r0N81XjuDnKIGrqbaXjtK/ojT2Z/oMqtN3JlV+maEEfIYND8tgbyDyedPs43jnALM0 W8j+wwlp9gWMMKKyVNQNQw9ZEPKJeI/drC9/ldm6rYk29MmIfqywgpb9rUQbLIWP3Oae dvTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lh58nWvDudjSuhn3rm5AM+63H/4nwM3lp5/LtDDXIfE=; b=de0tyYTVFJWiHwMIyeZjQNnm0PAFhQVRbbmIKrxYoMDzDMYu1dk0YrDP8nBNA5iCmg yGALjwKZru+OEwHDAPWJg8ZKhFvgWzIoz+nqig/DzsPxCSVnORL1VQTDSHsX74zCjE8D Wijeog4VFNicZbRS8uRCE539qZbRNLgx4LjR2025O9cXR11S3mVwDeb9DXbUi1teT69+ prO5dPc0nqnRWQu5uRnAxPlVjU1oweO8De+/djLDL6VYh9/DzS0qaWPIOSUdyyB4z//e 5bE1HUL6+FUhszWmsmD4muV3OZz7s6kPTQArn1PjQZKllSCZt96O2qKsyhZTzFqeXhS+ LH4w== X-Gm-Message-State: ANoB5pmJeK8gBIWzVM5dBVoB5oH2mGgtb1VwuHVam7Y7kmc2dzdFUrrC 0SrzfUU4dxztvBNBm5l1ie0Tpzi3++USCQOc X-Google-Smtp-Source: AA0mqf56juHjAi6H1cdvAUf1bQe8R6YTUD75eVyL0Il47Vj8KkV8T/xccGU+Yo71AXse7iTRC7WWNg== X-Received: by 2002:a17:90a:dd82:b0:212:fdb1:720b with SMTP id l2-20020a17090add8200b00212fdb1720bmr80782887pjv.66.1669963933342; Thu, 01 Dec 2022 22:52:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 12/13] tcg/s390x: Use tgen_movcond_int in tgen_clz Date: Thu, 1 Dec 2022 22:51:59 -0800 Message-Id: <20221202065200.224537-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964289759100004 Content-Type: text/plain; charset="utf-8" Reuse code from movcond to conditionally copy a2 to dest, based on the condition codes produced by FLOGR. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.c.inc | 26 +++++++++++--------------- 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 86cdc248f2..cfc0d405b3 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, r) C_O1_I2(r, r, ri) +C_O1_I2(r, r, rI) C_O1_I2(r, r, rJ) C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 1e4947b598..23cbb10168 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1557,21 +1557,15 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TC= GReg a1, =20 if (a2const && a2 =3D=3D 64) { tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0); - } else { - if (a2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, a2); - } else { - tcg_out_mov(s, TCG_TYPE_I64, dest, a2); - } - if (HAVE_FACILITY(LOAD_ON_COND)) { - /* Emit: if (one bit found) dest =3D r0. */ - tcg_out_insn(s, RRFc, LOCGR, dest, TCG_REG_R0, 2); - } else { - /* Emit: if (no one bit found) goto over; dest =3D r0; over: = */ - tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0); - } + return; } + + /* + * Conditions from FLOGR are: + * 2 -> one bit found + * 8 -> no one bit found + */ + tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); } =20 static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, @@ -3224,11 +3218,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - case INDEX_op_clz_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: return C_O1_I2(r, r, ri); =20 + case INDEX_op_clz_i64: + return C_O1_I2(r, r, rI); + case INDEX_op_sub_i32: case INDEX_op_sub_i64: case INDEX_op_and_i32: --=20 2.34.1 From nobody Fri May 3 10:20:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1669964080; cv=none; d=zohomail.com; s=zohoarc; b=YBwNdJxPiZCs34/H3f7HIwwaTRMiEmgHbwfWryrTQSU1Twv9RFyAifUOC+Ehmsmi6FIlNw8tL9rMd3vuFMwp571THTxnrJcHGjxe6SyHQX8lMbIabNL8e3OLBu6VN6Kk8AMSNE67rQXOcFohWJOnp7OpmNGqYvwXd1u1+NxvMJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669964080; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x4OQMsd27euNjrg+Wz7g0qoeJXgmOpScKCYJD/Ut1GE=; b=ZUcgwxg1pckfLP9WdeYobECLqruSUy6NUv7Pvrjssjy0fLerxa9f9QE4w23H9JvCIYbc7xi+XfUq6fue68sOaFrVeXDWxtjH5sAIaofudbvExw9VYe/rlXTJbC8iobEOZEdsMM2RuLB83/2SVIohsgGHaBjNQwZ4ZB9dDor2E4s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1669964080357865.8211778036809; Thu, 1 Dec 2022 22:54:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p0zuF-0007dH-5w; Fri, 02 Dec 2022 01:52:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p0zuD-0007cf-Nn for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:17 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p0zuB-0003je-K3 for qemu-devel@nongnu.org; Fri, 02 Dec 2022 01:52:17 -0500 Received: by mail-pl1-x630.google.com with SMTP id k7so3828048pll.6 for ; Thu, 01 Dec 2022 22:52:15 -0800 (PST) Received: from stoup.. ([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id q61-20020a17090a17c300b00218d894fac3sm6056649pja.3.2022.12.01.22.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 22:52:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x4OQMsd27euNjrg+Wz7g0qoeJXgmOpScKCYJD/Ut1GE=; b=WXaUhzOV+hSOl1IfDON4/iWoIVrz8ptl15RAMHwEV+xOELrjkKLkeckmgL23jZ9++K rdQV8TE67JsoY+6clVgMf2hfsawt9EbqbFZFHVZI0/lQAr4W7egjj1BA/Cya3XltQPkS jU8gHggy+TNv2grLHrGWKfx678xfOjZht8FNXy0ibPViLUL+GLAkDz7h/onOQLIsRr7u DyuuXF7oJtD04cfkiC8VzdwAiWWh0a+JhoynhKyCNYy+mAsXW/d7YjzkLxh/Citl36TC upaI/1Tfq+paXJcYXBVkfTwvZ5VOkfNmm/Ezeq81S3yHC9V3TImFahVU5kd7rTFuvoOh cCsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x4OQMsd27euNjrg+Wz7g0qoeJXgmOpScKCYJD/Ut1GE=; b=P7CZGUPMUdTN4EAUfyq7R90IdNeFlnmit8T9HBEk9RZdIqabNZrGe/TP8TTiax2e0E 7I3q7up5ztQd387PWUSQVOxt9wmTOGek0RvDKazNQyr6e/+6C0Y4JZV4+o9YRRVNRRzM BHS/TUZVs3HPL47k9nf2LM3j7lIYgSmiEBOXPYQHOWf/NupCzW6gvKMWPZZM5uObRyp5 ir7luMt0G8KHTteSfAtfUPVAFXXpcLN0LMn8axHhm/HTtboesj0F1RCZUevTeqcC0sZA jt7kTmTjffpOO7dEc+X39/4VzrvEpMDi1fgl8o4pD5LJWNnUKF3tG44x+9FR3g/UMyhG P34A== X-Gm-Message-State: ANoB5pk7mVXxzFZrN4e5reXowcQpHqffq/zVG+udJ7ZDndVhE4FTjA2W 3S3neKQPlVWizYW6IuN+FXl1W7uYiqZ4Cyye X-Google-Smtp-Source: AA0mqf5usPgOyzyWGLMvyicnhvpfPL5XbjEA6AG1XrxrQzL7yXif6Ff6H47wqbfxIAamHRwGMfhsEQ== X-Received: by 2002:a17:902:fe81:b0:189:b732:7671 with SMTP id x1-20020a170902fe8100b00189b7327671mr4437853plm.26.1669963934211; Thu, 01 Dec 2022 22:52:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: thuth@redhat.com, iii@linux.ibm.com Subject: [PATCH v3 13/13] tcg/s390x: Implement ctpop operation Date: Thu, 1 Dec 2022 22:52:00 -0800 Message-Id: <20221202065200.224537-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202065200.224537-1-richard.henderson@linaro.org> References: <20221202065200.224537-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669964082243100003 Content-Type: text/plain; charset="utf-8" There is an older form that produces per-byte results, and a newer form that produces per-register results, and a vector form that produces per-element results. Signed-off-by: Richard Henderson Reviewed-by: Ilya Leoshkevich --- tcg/s390x/tcg-target.h | 5 ++-- tcg/s390x/tcg-target.c.inc | 51 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 191c6a073e..5d184d8e14 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -62,6 +62,7 @@ typedef enum TCGReg { #define FACILITY_LOAD_ON_COND 45 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND +#define FACILITY_POPCOUNT FACILITY_LOAD_ON_COND #define FACILITY_LOAD_ON_COND2 53 #define FACILITY_MISC_INSN_EXT2 58 #define FACILITY_MISC_INSN_EXT3 61 @@ -91,7 +92,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_nor_i32 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 -#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_ctpop_i32 HAVE_FACILITY(POPCOUNT) #define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i32 0 @@ -128,7 +129,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_nor_i64 HAVE_FACILITY(MISC_INSN_EXT3) #define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM) #define TCG_TARGET_HAS_ctz_i64 0 -#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_ctpop_i64 HAVE_FACILITY(POPCOUNT) #define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 23cbb10168..7744c6ad54 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -208,6 +208,7 @@ typedef enum S390Opcode { =20 RRFc_LOCR =3D 0xb9f2, RRFc_LOCGR =3D 0xb9e2, + RRFc_POPCNT =3D 0xb9e1, =20 RR_AR =3D 0x1a, RR_ALR =3D 0x1e, @@ -259,6 +260,7 @@ typedef enum S390Opcode { RXY_LRVG =3D 0xe30f, RXY_LRVH =3D 0xe31f, RXY_LY =3D 0xe358, + RXY_MSG =3D 0xe30c, RXY_NG =3D 0xe380, RXY_OG =3D 0xe381, RXY_STCY =3D 0xe372, @@ -276,6 +278,7 @@ typedef enum S390Opcode { RX_L =3D 0x58, RX_LA =3D 0x41, RX_LH =3D 0x48, + RX_MS =3D 0x71, RX_ST =3D 0x50, RX_STC =3D 0x42, RX_STH =3D 0x40, @@ -1568,6 +1571,45 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCG= Reg a1, tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2); } =20 +static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg dest, TCGReg sr= c) +{ + /* With MIE3, and bit 0 of m4 set, we get the complete result. */ + if (HAVE_FACILITY(MISC_INSN_EXT3)) { + if (type =3D=3D TCG_TYPE_I32) { + tgen_ext32u(s, dest, src); + src =3D dest; + } + tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); + return; + } + + /* Without MIE3, each byte gets the count of bits for the byte. */ + tcg_out_insn(s, RRFc, POPCNT, dest, src, 0); + + /* Multiply to sum each byte at the top of the word. */ + if (type =3D=3D TCG_TYPE_I32 && HAVE_FACILITY(GEN_INST_EXT)) { + tcg_out_insn(s, RIL, MSFI, dest, 0x01010101); + } else { + /* No space to save: share the constant between TCG_TYPE_I32/I64. = */ + tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); + new_pool_label(s, 0x0101010101010101ull, + R_390_PC32DBL, s->code_ptr - 2, 2); + + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RX, MS, dest, TCG_TMP0, TCG_REG_NONE, 0); + } else { + tcg_out_insn(s, RXY, MSG, dest, TCG_TMP0, TCG_REG_NONE, 0); + } + } + + /* Shift result down from the top byte. */ + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_sh32(s, RS_SRL, dest, TCG_REG_NONE, 24); + } else { + tcg_out_sh64(s, RSY_SRLG, dest, dest, TCG_REG_NONE, 56); + } +} + static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src, int ofs, int len, int z) { @@ -2733,6 +2775,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tgen_clz(s, args[0], args[1], args[2], const_args[2]); break; =20 + case INDEX_op_ctpop_i32: + tgen_ctpop(s, TCG_TYPE_I32, args[0], args[1]); + break; + case INDEX_op_ctpop_i64: + tgen_ctpop(s, TCG_TYPE_I64, args[0], args[1]); + break; + case INDEX_op_mb: /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ @@ -3302,6 +3351,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extu_i32_i64: case INDEX_op_extract_i32: case INDEX_op_extract_i64: + case INDEX_op_ctpop_i32: + case INDEX_op_ctpop_i64: return C_O1_I1(r, r); =20 case INDEX_op_qemu_ld_i32: --=20 2.34.1