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([2602:47:d48a:1201:e3cc:2e37:17d4:f1d5]) by smtp.gmail.com with ESMTPSA id d12-20020a170903230c00b00186f0f59c85sm4637075plh.235.2022.12.01.21.40.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 21:40:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/U/vHQuPSCOPy8oTwpcQ9f3MBduH/phXh6PjwLEJr1I=; b=k3FxqtpJWry5HTl0MrCaYtxb1bgTGIQz97SvARejhB9TeDdnsmA+wPLvhfP2lsKQD1 +FK5BVCvgcqHebNhxjFvroNKfaQWqybeqvuxvtgfY0YMEeE2f6oDKsQbRDC5Wnz2BAju QOfMseRn+YjyiPQ8nRYe4flzhQfPw55FMmBE0pAy7nt4vM3sGPvSh1Ybw4/jd4lTOJ37 tBrmmjRvk9e0wUXabLGTHVaH+IZJluXih1Itf2Rg0Z5RM/wfogsYvCb4Vs0oJZA1UbEk 4CQglo4OUd5EV6lRmI4ZRQJXTy+wKyi/bxTObnK1fUIrPPZs96zmFCuTk+kqsuYiqKAv ibag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/U/vHQuPSCOPy8oTwpcQ9f3MBduH/phXh6PjwLEJr1I=; b=7hbJQwxF0Yxjpaoc5zhoa+3H+9KCsfm40mVoEARAm9B8znNXfmW2dmSWwBkMv1tEmG Ml8qrK13m7cDWoOloPEMXsX3KLjjmN6ZUTyAx0zjHznk1gKJTlHHERMJiXmZcoQMpjdV DA6Miu3g+RLFxKdLDkH/c7nXcR9TQdTIdgeof1sVh0Sa1QzgtkhTHhL9tr+WhpKS1bHk TqhfLozn6RN8o984jioyPVqOKKHHm+77jHKHB0DnsyYIZ5fWZrrh4v3A6V9oxF9sIxWH oKuyMX+akfzFZxHVOwkxVQGP463vkKzuCpBqgwS12gL9LZs6hwEzp0HwNjlIXCWZECtR Tf1w== X-Gm-Message-State: ANoB5plbDPqubPQzwTT5dxK/oFIB1Oe4EjGxzzqvKs3e/S1xlGBJi/+k CWb7QpebQ7M6llopjlHBr+Rt2Y69KzGLeSfR X-Google-Smtp-Source: AA0mqf4qJo3lgLVfNpoCW/UHD+qF/5HY4BNL17eq0Nulgb45jz/+D4h/9gkEiM5I65Q6Isj7NruL/g== X-Received: by 2002:a63:4b41:0:b0:477:fbed:369b with SMTP id k1-20020a634b41000000b00477fbed369bmr26324727pgl.57.1669959609423; Thu, 01 Dec 2022 21:40:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/34] tcg: Introduce paired register allocation Date: Thu, 1 Dec 2022 21:39:33 -0800 Message-Id: <20221202053958.223890-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221202053958.223890-1-richard.henderson@linaro.org> References: <20221202053958.223890-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1669960497090100005 Content-Type: text/plain; charset="utf-8" There are several instances where we need to be able to allocate a pair of registers to related inputs/outputs. Add 'p' and 'm' register constraints for this, in order to be able to allocate the even/odd register first or second. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 + tcg/tcg.c | 475 ++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 403 insertions(+), 74 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index d84bae6e3f..5c2254ce9f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -951,6 +951,8 @@ typedef struct TCGArgConstraint { unsigned ct : 16; unsigned alias_index : 4; unsigned sort_index : 4; + unsigned pair_index : 4; + unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ bool oalias : 1; bool ialias : 1; bool newreg : 1; diff --git a/tcg/tcg.c b/tcg/tcg.c index 3532de3715..72187887c1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1986,15 +1986,32 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bo= ol have_prefs) static int get_constraint_priority(const TCGOpDef *def, int k) { const TCGArgConstraint *arg_ct =3D &def->args_ct[k]; - int n; + int n =3D ctpop64(arg_ct->regs); =20 - if (arg_ct->oalias) { - /* an alias is equivalent to a single register */ - n =3D 1; - } else { - n =3D ctpop64(arg_ct->regs); + /* + * Sort constraints of a single register first, which includes output + * aliases (which must exactly match the input already allocated). + */ + if (n =3D=3D 1 || arg_ct->oalias) { + return INT_MAX; } - return TCG_TARGET_NB_REGS - n + 1; + + /* + * Sort register pairs next, first then second immediately after. + * Arbitrarily sort multiple pairs by the index of the first reg; + * there shouldn't be many pairs. + */ + switch (arg_ct->pair) { + case 1: + case 3: + return (k + 1) * 2; + case 2: + return (arg_ct->pair_index + 1) * 2 - 1; + } + + /* Finally, sort by decreasing register count. */ + assert(n > 1); + return -n; } =20 /* sort from highest priority to lowest */ @@ -2029,7 +2046,8 @@ static void process_op_defs(TCGContext *s) for (op =3D 0; op < NB_OPS; op++) { TCGOpDef *def =3D &tcg_op_defs[op]; const TCGTargetOpDef *tdefs; - int i, nb_args; + bool saw_alias_pair =3D false; + int i, o, i2, o2, nb_args; =20 if (def->flags & TCG_OPF_NOT_PRESENT) { continue; @@ -2051,58 +2069,175 @@ static void process_op_defs(TCGContext *s) =20 for (i =3D 0; i < nb_args; i++) { const char *ct_str =3D tdefs->args_ct_str[i]; + bool input_p =3D i >=3D def->nb_oargs; + /* Incomplete TCGTargetOpDef entry. */ tcg_debug_assert(ct_str !=3D NULL); =20 - while (*ct_str !=3D '\0') { - switch(*ct_str) { - case '0' ... '9': - { - int oarg =3D *ct_str - '0'; - tcg_debug_assert(ct_str =3D=3D tdefs->args_ct_str[= i]); - tcg_debug_assert(oarg < def->nb_oargs); - tcg_debug_assert(def->args_ct[oarg].regs !=3D 0); - def->args_ct[i] =3D def->args_ct[oarg]; - /* The output sets oalias. */ - def->args_ct[oarg].oalias =3D true; - def->args_ct[oarg].alias_index =3D i; - /* The input sets ialias. */ - def->args_ct[i].ialias =3D true; - def->args_ct[i].alias_index =3D oarg; - } - ct_str++; - break; - case '&': - def->args_ct[i].newreg =3D true; - ct_str++; - break; + switch (*ct_str) { + case '0' ... '9': + o =3D *ct_str - '0'; + tcg_debug_assert(input_p); + tcg_debug_assert(o < def->nb_oargs); + tcg_debug_assert(def->args_ct[o].regs !=3D 0); + tcg_debug_assert(!def->args_ct[o].oalias); + def->args_ct[i] =3D def->args_ct[o]; + /* The output sets oalias. */ + def->args_ct[o].oalias =3D 1; + def->args_ct[o].alias_index =3D i; + /* The input sets ialias. */ + def->args_ct[i].ialias =3D 1; + def->args_ct[i].alias_index =3D o; + if (def->args_ct[i].pair) { + saw_alias_pair =3D true; + } + tcg_debug_assert(ct_str[1] =3D=3D '\0'); + continue; + + case '&': + tcg_debug_assert(!input_p); + def->args_ct[i].newreg =3D true; + ct_str++; + break; + + case 'p': /* plus */ + /* Allocate to the register after the previous. */ + tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); + o =3D i - 1; + tcg_debug_assert(!def->args_ct[o].pair); + tcg_debug_assert(!def->args_ct[o].ct); + def->args_ct[i] =3D (TCGArgConstraint){ + .pair =3D 2, + .pair_index =3D o, + .regs =3D def->args_ct[o].regs << 1, + }; + def->args_ct[o].pair =3D 1; + def->args_ct[o].pair_index =3D i; + tcg_debug_assert(ct_str[1] =3D=3D '\0'); + continue; + + case 'm': /* minus */ + /* Allocate to the register before the previous. */ + tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); + o =3D i - 1; + tcg_debug_assert(!def->args_ct[o].pair); + tcg_debug_assert(!def->args_ct[o].ct); + def->args_ct[i] =3D (TCGArgConstraint){ + .pair =3D 1, + .pair_index =3D o, + .regs =3D def->args_ct[o].regs >> 1, + }; + def->args_ct[o].pair =3D 2; + def->args_ct[o].pair_index =3D i; + tcg_debug_assert(ct_str[1] =3D=3D '\0'); + continue; + } + + do { + switch (*ct_str) { case 'i': def->args_ct[i].ct |=3D TCG_CT_CONST; - ct_str++; break; =20 /* Include all of the target-specific constraints. */ =20 #undef CONST #define CONST(CASE, MASK) \ - case CASE: def->args_ct[i].ct |=3D MASK; ct_str++; break; + case CASE: def->args_ct[i].ct |=3D MASK; break; #define REGS(CASE, MASK) \ - case CASE: def->args_ct[i].regs |=3D MASK; ct_str++; break; + case CASE: def->args_ct[i].regs |=3D MASK; break; =20 #include "tcg-target-con-str.h" =20 #undef REGS #undef CONST default: + case '0' ... '9': + case '&': + case 'p': + case 'm': /* Typo in TCGTargetOpDef constraint. */ g_assert_not_reached(); } - } + } while (*++ct_str !=3D '\0'); } =20 /* TCGTargetOpDef entry with too much information? */ tcg_debug_assert(i =3D=3D TCG_MAX_OP_ARGS || tdefs->args_ct_str[i]= =3D=3D NULL); =20 + /* + * Fix up output pairs that are aliased with inputs. + * When we created the alias, we copied pair from the output. + * There are three cases: + * (1a) Pairs of inputs alias pairs of outputs. + * (1b) One input aliases the first of a pair of outputs. + * (2) One input aliases the second of a pair of outputs. + * + * Case 1a is handled by making sure that the pair_index'es are + * properly updated so that they appear the same as a pair of inpu= ts. + * + * Case 1b is handled by setting the pair_index of the input to + * itself, simply so it doesn't point to an unrelated argument. + * Since we don't encounter the "second" during the input allocati= on + * phase, nothing happens with the second half of the input pair. + * + * Case 2 is handled by setting the second input to pair=3D3, the + * first output to pair=3D3, and the pair_index'es to match. + */ + if (saw_alias_pair) { + for (i =3D def->nb_oargs; i < nb_args; i++) { + /* + * Since [0-9pm] must be alone in the constraint string, + * the only way they can both be set is if the pair comes + * from the output alias. + */ + if (!def->args_ct[i].ialias) { + continue; + } + switch (def->args_ct[i].pair) { + case 0: + break; + case 1: + o =3D def->args_ct[i].alias_index; + o2 =3D def->args_ct[o].pair_index; + tcg_debug_assert(def->args_ct[o].pair =3D=3D 1); + tcg_debug_assert(def->args_ct[o2].pair =3D=3D 2); + if (def->args_ct[o2].oalias) { + /* Case 1a */ + i2 =3D def->args_ct[o2].alias_index; + tcg_debug_assert(def->args_ct[i2].pair =3D=3D 2); + def->args_ct[i2].pair_index =3D i; + def->args_ct[i].pair_index =3D i2; + } else { + /* Case 1b */ + def->args_ct[i].pair_index =3D i; + } + break; + case 2: + o =3D def->args_ct[i].alias_index; + o2 =3D def->args_ct[o].pair_index; + tcg_debug_assert(def->args_ct[o].pair =3D=3D 2); + tcg_debug_assert(def->args_ct[o2].pair =3D=3D 1); + if (def->args_ct[o2].oalias) { + /* Case 1a */ + i2 =3D def->args_ct[o2].alias_index; + tcg_debug_assert(def->args_ct[i2].pair =3D=3D 1); + def->args_ct[i2].pair_index =3D i; + def->args_ct[i].pair_index =3D i2; + } else { + /* Case 2 */ + def->args_ct[i].pair =3D 3; + def->args_ct[o2].pair =3D 3; + def->args_ct[i].pair_index =3D o2; + def->args_ct[o2].pair_index =3D i; + } + break; + default: + g_assert_not_reached(); + } + } + } + /* sort the constraints (XXX: this is just an heuristic) */ sort_constraints(def, 0, def->nb_oargs); sort_constraints(def, def->nb_oargs, def->nb_iargs); @@ -3151,6 +3286,52 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet= required_regs, tcg_abort(); } =20 +static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, + TCGRegSet allocated_regs, + TCGRegSet preferred_regs, bool rev) +{ + int i, j, k, fmin, n =3D ARRAY_SIZE(tcg_target_reg_alloc_order); + TCGRegSet reg_ct[2]; + const int *order; + + /* Ensure that if I is not in allocated_regs, I+1 is not either. */ + reg_ct[1] =3D required_regs & ~(allocated_regs | (allocated_regs >> 1)= ); + tcg_debug_assert(reg_ct[1] !=3D 0); + reg_ct[0] =3D reg_ct[1] & preferred_regs; + + order =3D rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; + + /* + * Skip the preferred_regs option if it cannot be satisfied, + * or if the preference made no difference. + */ + k =3D reg_ct[0] =3D=3D 0 || reg_ct[0] =3D=3D reg_ct[1]; + + /* + * Minimize the number of flushes by looking for 2 free registers firs= t, + * then a single flush, then two flushes. + */ + for (fmin =3D 2; fmin >=3D 0; fmin--) { + for (j =3D k; j < 2; j++) { + TCGRegSet set =3D reg_ct[j]; + + for (i =3D 0; i < n; i++) { + TCGReg reg =3D order[i]; + + if (tcg_regset_test_reg(set, reg)) { + int f =3D !s->reg_to_temp[reg] + !s->reg_to_temp[reg += 1]; + if (f >=3D fmin) { + tcg_reg_free(s, reg, allocated_regs); + tcg_reg_free(s, reg + 1, allocated_regs); + return reg; + } + } + } + } + } + tcg_abort(); +} + /* Make sure the temporary is in a register. If needed, allocate the regi= ster from DESIRED while avoiding ALLOCATED. */ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, @@ -3560,8 +3741,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) =20 /* satisfy input constraints */ for (k =3D 0; k < nb_iargs; k++) { - TCGRegSet i_preferred_regs; - bool allocate_new_reg; + TCGRegSet i_preferred_regs, i_required_regs; + bool allocate_new_reg, copyto_new_reg; + TCGTemp *ts2; + int i1, i2; =20 i =3D def->args_ct[nb_oargs + k].sort_index; arg =3D op->args[i]; @@ -3578,43 +3761,156 @@ static void tcg_reg_alloc_op(TCGContext *s, const = TCGOp *op) =20 reg =3D ts->reg; i_preferred_regs =3D 0; + i_required_regs =3D arg_ct->regs; allocate_new_reg =3D false; + copyto_new_reg =3D false; =20 - if (arg_ct->ialias) { + switch (arg_ct->pair) { + case 0: /* not paired */ + if (arg_ct->ialias) { + i_preferred_regs =3D op->output_pref[arg_ct->alias_index]; + + /* + * If the input is not dead after the instruction, + * we must allocate a new register and move it. + */ + if (!IS_DEAD_ARG(i)) { + allocate_new_reg =3D true; + } else if (ts->val_type =3D=3D TEMP_VAL_REG) { + /* + * Check if the current register has already been + * allocated for another input. + */ + allocate_new_reg =3D + tcg_regset_test_reg(i_allocated_regs, reg); + } + } + if (!allocate_new_reg) { + temp_load(s, ts, i_required_regs, i_allocated_regs, + i_preferred_regs); + reg =3D ts->reg; + allocate_new_reg =3D !tcg_regset_test_reg(i_required_regs,= reg); + } + if (allocate_new_reg) { + /* + * Allocate a new register matching the constraint + * and move the temporary register into it. + */ + temp_load(s, ts, tcg_target_available_regs[ts->type], + i_allocated_regs, 0); + reg =3D tcg_reg_alloc(s, i_required_regs, i_allocated_regs, + i_preferred_regs, ts->indirect_base); + copyto_new_reg =3D true; + } + break; + + case 1: + /* First of an input pair; if i1 =3D=3D i2, the second is an o= utput. */ + i1 =3D i; + i2 =3D arg_ct->pair_index; + ts2 =3D i1 !=3D i2 ? arg_temp(op->args[i2]) : NULL; + + /* + * It is easier to default to allocating a new pair + * and to identify a few cases where it's not required. + */ + if (arg_ct->ialias) { + i_preferred_regs =3D op->output_pref[arg_ct->alias_index]; + if (IS_DEAD_ARG(i1) && + IS_DEAD_ARG(i2) && + ts->val_type =3D=3D TEMP_VAL_REG && + ts->reg < TCG_TARGET_NB_REGS - 1 && + tcg_regset_test_reg(i_required_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg + 1) && + (ts2 + ? ts2->val_type =3D=3D TEMP_VAL_REG && + ts2->reg =3D=3D reg + 1 + : s->reg_to_temp[reg + 1] =3D=3D NULL)) { + break; + } + } else { + /* Without aliasing, the pair must also be an input. */ + tcg_debug_assert(ts2); + if (ts->val_type =3D=3D TEMP_VAL_REG && + ts2->val_type =3D=3D TEMP_VAL_REG && + ts2->reg =3D=3D reg + 1 && + tcg_regset_test_reg(i_required_regs, reg)) { + break; + } + } + reg =3D tcg_reg_alloc_pair(s, i_required_regs, i_allocated_reg= s, + 0, ts->indirect_base); + goto do_pair; + + case 2: /* pair second */ + reg =3D new_args[arg_ct->pair_index] + 1; + goto do_pair; + + case 3: /* ialias with second output, no first input */ + tcg_debug_assert(arg_ct->ialias); i_preferred_regs =3D op->output_pref[arg_ct->alias_index]; =20 - /* - * If the input is readonly, then it cannot also be an - * output and aliased to itself. If the input is not - * dead after the instruction, we must allocate a new - * register and move it. - */ - if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { - allocate_new_reg =3D true; - } else if (ts->val_type =3D=3D TEMP_VAL_REG) { - /* - * Check if the current register has already been - * allocated for another input. - */ - allocate_new_reg =3D tcg_regset_test_reg(i_allocated_regs,= reg); + if (IS_DEAD_ARG(i) && + ts->val_type =3D=3D TEMP_VAL_REG && + reg > 0 && + s->reg_to_temp[reg - 1] =3D=3D NULL && + tcg_regset_test_reg(i_required_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg) && + !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { + tcg_regset_set_reg(i_allocated_regs, reg - 1); + break; } - } + reg =3D tcg_reg_alloc_pair(s, i_required_regs >> 1, + i_allocated_regs, 0, + ts->indirect_base); + tcg_regset_set_reg(i_allocated_regs, reg); + reg +=3D 1; + goto do_pair; =20 - if (!allocate_new_reg) { - temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_r= egs); - reg =3D ts->reg; - allocate_new_reg =3D !tcg_regset_test_reg(arg_ct->regs, reg); - } - - if (allocate_new_reg) { + do_pair: /* - * Allocate a new register matching the constraint - * and move the temporary register into it. + * If an aliased input is not dead after the instruction, + * we must allocate a new register and move it. */ - temp_load(s, ts, tcg_target_available_regs[ts->type], - i_allocated_regs, 0); - reg =3D tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs, - i_preferred_regs, ts->indirect_base); + if (arg_ct->ialias && !IS_DEAD_ARG(i)) { + /* + * Because of the alias, and the continued life, make sure + * that the temp is somewhere *other* than reg, and we get + * a copy in reg. + */ + tcg_regset_set_reg(i_allocated_regs, reg); + if (ts->val_type =3D=3D TEMP_VAL_REG && ts->reg =3D=3D reg= ) { + /* If ts was already in reg, copy it somewhere else. */ + TCGReg nr; + bool ok; + + tcg_debug_assert(ts->kind !=3D TEMP_FIXED); + nr =3D tcg_reg_alloc(s, tcg_target_available_regs[ts->= type], + i_allocated_regs, 0, ts->indirect_b= ase); + ok =3D tcg_out_mov(s, ts->type, nr, reg); + tcg_debug_assert(ok); + + set_temp_val_reg(s, ts, nr); + } else { + temp_load(s, ts, tcg_target_available_regs[ts->type], + i_allocated_regs, 0); + copyto_new_reg =3D true; + } + } else { + /* Preferably allocate to reg, otherwise copy. */ + i_required_regs =3D (TCGRegSet)1 << reg; + temp_load(s, ts, i_required_regs, i_allocated_regs, + i_preferred_regs); + copyto_new_reg =3D ts->reg !=3D reg; + } + break; + + default: + g_assert_not_reached(); + } + + if (copyto_new_reg) { if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { /* * Cross register class move not supported. Sync the @@ -3666,15 +3962,46 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); =20 - if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { - reg =3D new_args[arg_ct->alias_index]; - } else if (arg_ct->newreg) { - reg =3D tcg_reg_alloc(s, arg_ct->regs, - i_allocated_regs | o_allocated_regs, - op->output_pref[k], ts->indirect_base); - } else { - reg =3D tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, - op->output_pref[k], ts->indirect_base); + switch (arg_ct->pair) { + case 0: /* not paired */ + if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { + reg =3D new_args[arg_ct->alias_index]; + } else if (arg_ct->newreg) { + reg =3D tcg_reg_alloc(s, arg_ct->regs, + i_allocated_regs | o_allocated_reg= s, + op->output_pref[k], ts->indirect_b= ase); + } else { + reg =3D tcg_reg_alloc(s, arg_ct->regs, o_allocated_reg= s, + op->output_pref[k], ts->indirect_b= ase); + } + break; + + case 1: /* first of pair */ + tcg_debug_assert(!arg_ct->newreg); + if (arg_ct->oalias) { + reg =3D new_args[arg_ct->alias_index]; + break; + } + reg =3D tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_re= gs, + op->output_pref[k], ts->indirect_= base); + break; + + case 2: /* second of pair */ + tcg_debug_assert(!arg_ct->newreg); + if (arg_ct->oalias) { + reg =3D new_args[arg_ct->alias_index]; + } else { + reg =3D new_args[arg_ct->pair_index] + 1; + } + break; + + case 3: /* first of pair, aliasing with a second input */ + tcg_debug_assert(!arg_ct->newreg); + reg =3D new_args[arg_ct->pair_index] - 1; + break; + + default: + g_assert_not_reached(); } tcg_regset_set_reg(o_allocated_regs, reg); set_temp_val_reg(s, ts, reg); --=20 2.34.1